From: Jie Luo <jie.luo@oss.qualcomm.com>
To: sashiko-reviews@lists.linux.dev
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org
Subject: Re: [PATCH net-next 03/11] dt-bindings: net: qcom,ipq9574-ppe: Add IPQ5424 PPE support
Date: Sat, 10 Oct 2026 10:56:23 +0800 [thread overview]
Message-ID: <2befe56f-dd6b-402e-992c-a2e55ce0d1a6@oss.qualcomm.com> (raw)
In-Reply-To: <sashiko-outbox-165733@kernel.org>
On 10/9/2026 10:52 PM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [Medium] dt-bindings: missing minItems/maxItems in conditionals allows incorrect array lengths
> - [Low] dt-bindings: incomplete ethernet-ports restriction allows out-of-bounds ports
> --
>
> commit dead4fe7fe0227c2a98000bdee56dfba287669d7
> Author: Luo Jie <jie.luo@oss.qualcomm.com>
>
> dt-bindings: net: qcom,ipq9574-ppe: Add IPQ5424 PPE support
>
> This commit adds the IPQ5424 compatible to the IPQ9574 PPE binding. It
> describes the interconnect paths for each SoC and limits the Ethernet ports
> for IPQ5424 to ports 1-3.
>
>> diff --git a/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml
>> --- a/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml
>> +++ b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml
> [ ... ]
>> @@ -236,6 +233,62 @@ required:
>>
>> allOf:
>> - $ref: ethernet-switch.yaml
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: qcom,ipq9574-ppe
>> + then:
>> + properties:
>> + interconnects:
>> + items:
>> + - description: Bus interconnect path leading to PPE switch core function
>> + - description: Bus interconnect path leading to PPE register access
>> + - description: Bus interconnect path leading to QoS generation
>> + - description: Bus interconnect path leading to timeout reference
>> + - description: Bus interconnect path leading to NSS NOC from memory NOC
>> + - description: Bus interconnect path leading to memory NOC from NSS NOC
>> + - description: Bus interconnect path leading to enhanced memory NOC from NSS NOC
>
> [Severity: Medium]
> Does this array need explicit minItems and maxItems to strictly enforce the
> length?
>
> According to standard JSON Schema rules, an items array inside a conditional
> block validates the matching indices but does not enforce the array length
> unless minItems and maxItems are explicitly declared.
>
> Since the global schema allows minItems: 5, could an incomplete IPQ9574
> node with only 5 interconnects falsely pass validation here?
>
dtschema already sets minItems/maxItems to the length of an items list,
No change needed.
>> +
>> + interconnect-names:
>> + items:
>> + - const: ppe
>> + - const: ppe_cfg
>> + - const: qos_gen
>> + - const: timeout_ref
>> + - const: nssnoc_memnoc
>> + - const: memnoc_nssnoc
>> + - const: memnoc_nssnoc_1
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: qcom,ipq5424-ppe
>> + then:
>> + properties:
>> + interconnects:
>> + items:
>> + - description: Bus interconnect path leading to PPE switch core function
>> + - description: Bus interconnect path leading to PPE register access
>> + - description: Bus interconnect path leading to CE AXI
>> + - description: Bus interconnect path leading to CE APB
>> + - description: Bus interconnect path leading to NSS CSR access
>
> [Severity: Medium]
> Similarly, should minItems and maxItems be explicitly set to 5 here?
>
> Without these limits, an IPQ5424 node could declare 7 interconnects and pass
> because it satisfies the global maxItems: 7 constraint, leaving the trailing
> 2 elements unchecked.
>
No change is needed here either, for the same reason as above.
>> +
>> + interconnect-names:
>> + items:
>> + - const: ppe
>> + - const: ppe_cfg
>> + - const: nssnoc_ce_axi
>> + - const: nssnoc_ce_apb
>> + - const: nssnoc_nss_csr
>> +
>> + ethernet-ports:
>> + patternProperties:
>> + "^ethernet-port@[1-3]$":
>> + properties:
>> + reg:
>> + maximum: 3
>> + "^ethernet-port@[4-6]$": false
>
> [Severity: Low]
> Does this workaround fully restrict the out-of-bounds ports for IPQ5424?
>
> The top-level ethernet-ports container lacks an unevaluatedProperties: false
> constraint. Because ethernet-switch.yaml (included via allOf) dynamically
> matches any port matching ^(ethernet-)?port@[0-9a-f]+$ as a generic object,
> out-of-bounds nodes like ethernet-port@7 would pass ethernet-switch.yaml's
> checks.
>
> Since this block explicitly sets ^ethernet-port@[4-6]$: false but does not
> cap the container itself, will ports 7 and above silently pass schema
> validation?
>
I will update it in the next version by matching all ethernet-port@
nodes and relying on the reg range limits.
next prev parent reply other threads:[~2026-10-10 2:56 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-08 14:51 [PATCH net-next 00/11] net: ethernet: qualcomm: ppe: Add support for IPQ5424 SoC Luo Jie
2026-10-08 14:51 ` [PATCH net-next 01/11] dt-bindings: net: qcom,ipq9574-ppe: Split EDMA reset into sys and apb Luo Jie
2026-10-08 19:49 ` Rob Herring (Arm)
2026-10-08 14:51 ` [PATCH net-next 02/11] net: ethernet: qualcomm: ppe: Fix multicast queue config table index Luo Jie
2026-10-09 14:52 ` sashiko-bot
2026-10-10 3:00 ` Jie Luo
2026-10-08 14:51 ` [PATCH net-next 03/11] dt-bindings: net: qcom,ipq9574-ppe: Add IPQ5424 PPE support Luo Jie
2026-10-08 20:08 ` Rob Herring (Arm)
2026-10-09 14:52 ` sashiko-bot
2026-10-10 2:56 ` Jie Luo [this message]
2026-10-08 14:51 ` [PATCH net-next 04/11] docs: networking: Document IPQ5424 as a supported SoC Luo Jie
2026-10-08 14:51 ` [PATCH net-next 05/11] net: ethernet: qualcomm: ppe: Add platform support for IPQ5424 Luo Jie
2026-10-08 14:51 ` [PATCH net-next 06/11] net: ethernet: qualcomm: ppe: Add IPQ5424 BM buffer configuration Luo Jie
2026-10-08 14:51 ` [PATCH net-next 07/11] net: ethernet: qualcomm: ppe: Add IPQ5424 QM configuration Luo Jie
2026-10-09 14:52 ` sashiko-bot
2026-10-10 2:44 ` Jie Luo
2026-10-08 14:51 ` [PATCH net-next 08/11] net: ethernet: qualcomm: ppe: Add IPQ5424 scheduler resource configuration Luo Jie
2026-10-08 14:51 ` [PATCH net-next 09/11] net: ethernet: qualcomm: ppe: Add IPQ5424 scheduler configuration Luo Jie
2026-10-08 14:51 ` [PATCH net-next 10/11] net: ethernet: qualcomm: ppe: Add IPQ5424 service code configuration Luo Jie
2026-10-08 14:51 ` [PATCH net-next 11/11] net: ethernet: qualcomm: ppe: Add IPQ5424 counter debugfs support Luo Jie
2026-10-08 14:54 ` [PATCH net-next 00/11] net: ethernet: qualcomm: ppe: Add support for IPQ5424 SoC netdev-bot+sinfo
2026-10-09 3:42 ` Jie Luo
2026-10-08 19:07 ` Andrew Lunn
2026-10-09 3:31 ` Jie Luo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=2befe56f-dd6b-402e-992c-a2e55ce0d1a6@oss.qualcomm.com \
--to=jie.luo@oss.qualcomm.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=robh@kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox