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[2.80.170.125]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4771900dad7sm4540145e9.6.2025.10.27.16.22.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 16:22:28 -0700 (PDT) Message-ID: <2c3e4bdefb306dc89c15bebc549d854ea2b4cc32.camel@gmail.com> Subject: Re: [PATCH v1 1/2] dt-bindings: PCI: ti,j721e-pci-host: Add optional regulator supplies From: Vitor Soares To: Krzysztof Kozlowski Cc: Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?UTF-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Vitor Soares , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Date: Mon, 27 Oct 2025 23:22:26 +0000 In-Reply-To: <20251020-kickass-fervent-capybara-9c48a0@kuoka> References: <20251014112553.398845-1-ivitro@gmail.com> <20251014112553.398845-2-ivitro@gmail.com> <20251020-kickass-fervent-capybara-9c48a0@kuoka> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.4-0ubuntu2 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Krzysztof, Thank you for the feedback. On Mon, 2025-10-20 at 13:14 +0200, Krzysztof Kozlowski wrote: > On Tue, Oct 14, 2025 at 12:25:48PM +0100, Vitor Soares wrote: > > From: Vitor Soares > >=20 > > Add optional regulator supply properties for PCIe endpoints on TI SoCs. > > Some boards provide dedicated regulators for PCIe devices, such as > > 1.5V (miniPCIe), 3.3V (common for M.2 or miniPCIe), or 12V > > (for high-power devices). These supplies are now described as optional > > properties to allow the driver to control endpoint power where supporte= d. >=20 > Last sentence is completely redundant. Please do not describe DT, we > all can read the patch. Driver is irrelevant here. >=20 >=20 Ack, I will remove last sentence. >=20 > How you described here and in descriptions, suggests these are rather > port properties, not the controller. You are right - these supplies power the PCIe slot/connector, not the contr= oller itself. However, as per my understanding, the current kernel practice is to place slot supplies in the root complex node rather than the endpoint node.= as seen in e.g.: - imx6q-pcie.yaml - rockchip-dw-pcie.yaml - rcar-pci-host.yaml This seems consistent with those existing bindings, but please let me know = if I=E2=80=99m overlooking something specific to this case. >=20 > >=20 > > Signed-off-by: Vitor Soares > > --- > > =C2=A0.../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 14 +++++++++= +++++ > > =C2=A01 file changed, 14 insertions(+) > >=20 > > diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.ya= ml > > b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > > index c704099f134b..a20b03406448 100644 > > --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > > +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > > @@ -110,6 +110,18 @@ properties: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 interrupts: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 maxItems: 1 > > =C2=A0 > > +=C2=A0 vpcie1v5-supply: >=20 > How is it called in this device datasheet (not the board schematics)? The TI SoC datasheet describes the controller interface but doesn=E2=80=99t= define these external supply rails - they are board-level regulators specific to the slo= t. >=20 > > +=C2=A0=C2=A0=C2=A0 description: 1.5V regulator used to power PCIe inte= rfaces, > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 typically present on miniPCIe slots. >=20 > Best regards, > Krzysztof >=20 Best regards, Vitor Soares