[PATCH v7 0/7] clk: meson-axg: Add AO Cloclk and Reset driver

[PATCH v7 0/7] clk: meson-axg: Add AO Cloclk and Reset driver

[Yixun Lan]

  This patch try to add AO clock and Reset driver for Amlogic's
Meson-AXG SoC.
  Please note that patch 7 need to wait for the DTS changes[3] merged
into mainline first, otherwise it will break the serial console.

 patch 2: factor the common code into a dedicated file
 patch 3-5: add the aoclk driver for AXG SoC
 patch 6-7: drop unnecessary clock flags

changes since v6 at [7]: 
 - fix over 80 chars chechpatch error
 - add Philip's Ack on patch 5
 - drop extra end of newline

changes since v5 at [6]: 
 - drop unnecessary header files
 - add 'axg_aoclk' prefix to clk driver, make them more consistent
 - add missing end new line..

changes since v4 at [5]: 
 - fix return err
 - introduce CONFIG_COMMON_CLK_MESON_AO
 - format/style minor fix

changes since v3 at [4]: 
 - add 'const' contraint to the read-only data
 - switch to devm_of_clk_add_hw_provider API
 - check return value of devm_reset_controller_register

changes since v2 at [2]: 
 - rework meson_aoclkc_probe() which leverage the of_match_data
 - merge patch 5-6 into this series
 - seperate DTS patch, will send to Kevin Hilman independently
 
changes since v1 at [0]: 
 - rebase to clk-meson's branch 'next/drivers' [1]
 - fix license, update to BSD-3-Clause
 - drop un-used include header file

[0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan@amlogic.com
[1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
[2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan@amlogic.com
[3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan@amlogic.com
[4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan@amlogic.com
[5] https://lkml.kernel.org/r/20180408031938.153474-1-yixun.lan@amlogic.com
[6] https://lkml.kernel.org/r/20180409143749.71197-1-yixun.lan@amlogic.com
[7] https://lkml.kernel.org/r/20180419135426.155794-1-yixun.lan@amlogic.com


Qiufang Dai (1):
  clk: meson-axg: Add AO Clock and Reset controller driver

Yixun Lan (6):
  clk: meson: migrate to devm_of_clk_add_hw_provider API
  clk: meson: aoclk: refactor common code into dedicated file
  dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
  dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
  clk: meson: drop CLK_SET_RATE_PARENT flag
  clk: meson: drop CLK_IGNORE_UNUSED flag

 .../bindings/clock/amlogic,gxbb-aoclkc.txt    |   1 +
 drivers/clk/meson/Kconfig                     |   8 +
 drivers/clk/meson/Makefile                    |   3 +-
 drivers/clk/meson/axg-aoclk.c                 | 163 ++++++++++++++++++
 drivers/clk/meson/axg-aoclk.h                 |  29 ++++
 drivers/clk/meson/gxbb-aoclk.c                |  95 ++++------
 drivers/clk/meson/gxbb-aoclk.h                |   5 +
 drivers/clk/meson/meson-aoclk.c               |  81 +++++++++
 drivers/clk/meson/meson-aoclk.h               |  34 ++++
 include/dt-bindings/clock/axg-aoclkc.h        |  26 +++
 include/dt-bindings/reset/axg-aoclkc.h        |  20 +++
 11 files changed, 401 insertions(+), 64 deletions(-)
 create mode 100644 drivers/clk/meson/axg-aoclk.c
 create mode 100644 drivers/clk/meson/axg-aoclk.h
 create mode 100644 drivers/clk/meson/meson-aoclk.c
 create mode 100644 drivers/clk/meson/meson-aoclk.h
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

-- 
2.17.0

[PATCH v7 3/7] dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC

[Yixun Lan]

Update the dt-binding documentation to support new compatible string
for the Amlogic's Meson-AXG SoC.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
index 786dc39ca904..3a880528030e 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -9,6 +9,7 @@ Required Properties:
 	- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
 	- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
 	- GXM (S912) : "amlogic,meson-gxm-aoclkc"
+	- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
 	followed by the common "amlogic,meson-gx-aoclkc"
 
 - #clock-cells: should be 1.
-- 
2.17.0

[PATCH v7 4/7] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings

[Yixun Lan]

Add dt-bindings headers for the Meson-AXG's AO clock and
reset controller.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 include/dt-bindings/clock/axg-aoclkc.h | 26 ++++++++++++++++++++++++++
 include/dt-bindings/reset/axg-aoclkc.h | 20 ++++++++++++++++++++
 2 files changed, 46 insertions(+)
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 000000000000..61955016a55b
--- /dev/null
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_SAR_ADC	6
+#define CLKID_AO_CLK81		7
+#define CLKID_AO_SAR_ADC_SEL	8
+#define CLKID_AO_SAR_ADC_DIV	9
+#define CLKID_AO_SAR_ADC_CLK	10
+#define CLKID_AO_ALT_XTAL	11
+
+#endif
diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h
new file mode 100644
index 000000000000..d342c0b6b2a7
--- /dev/null
+++ b/include/dt-bindings/reset/axg-aoclkc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+
+#define RESET_AO_REMOTE		0
+#define RESET_AO_I2C_MASTER	1
+#define RESET_AO_I2C_SLAVE	2
+#define RESET_AO_UART1		3
+#define RESET_AO_UART2		4
+#define RESET_AO_IR_BLASTER	5
+
+#endif
-- 
2.17.0

Re: [PATCH v7 4/7] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings

[Philipp Zabel]

On Thu, 2018-04-26 at 16:44 +0800, Yixun Lan wrote:
> Add dt-bindings headers for the Meson-AXG's AO clock and
> reset controller.
> 
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>

This one is
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>

regards
Philipp

Re: [PATCH v7 4/7] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings

[Yixun Lan]

On 04/26/18 16:59, Philipp Zabel wrote:
> On Thu, 2018-04-26 at 16:44 +0800, Yixun Lan wrote:
>> Add dt-bindings headers for the Meson-AXG's AO clock and
>> reset controller.
>>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> 
> This one is
> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
> 

Hi Philipp
 My bad, Indeed, I made a mistake..

HI Jerome:
 Could you fix this once apply the patch series?
or do you want me send another version?

Yixun

Re: [PATCH v7 0/7] clk: meson-axg: Add AO Cloclk and Reset driver

[Jerome Brunet]

On Thu, 2018-04-26 at 16:44 +0800, Yixun Lan wrote:
>   This patch try to add AO clock and Reset driver for Amlogic's
> Meson-AXG SoC.
>   Please note that patch 7 need to wait for the DTS changes[3] merged
> into mainline first, otherwise it will break the serial console.
> 
>  patch 2: factor the common code into a dedicated file
>  patch 3-5: add the aoclk driver for AXG SoC
>  patch 6-7: drop unnecessary clock flags
> 
> changes since v6 at [7]: 
>  - fix over 80 chars chechpatch error
>  - add Philip's Ack on patch 5
>  - drop extra end of newline
> 
> changes since v5 at [6]: 
>  - drop unnecessary header files
>  - add 'axg_aoclk' prefix to clk driver, make them more consistent
>  - add missing end new line..
> 
> changes since v4 at [5]: 
>  - fix return err
>  - introduce CONFIG_COMMON_CLK_MESON_AO
>  - format/style minor fix
> 
> changes since v3 at [4]: 
>  - add 'const' contraint to the read-only data
>  - switch to devm_of_clk_add_hw_provider API
>  - check return value of devm_reset_controller_register
> 
> changes since v2 at [2]: 
>  - rework meson_aoclkc_probe() which leverage the of_match_data
>  - merge patch 5-6 into this series
>  - seperate DTS patch, will send to Kevin Hilman independently
>  
> changes since v1 at [0]: 
>  - rebase to clk-meson's branch 'next/drivers' [1]
>  - fix license, update to BSD-3-Clause
>  - drop un-used include header file
> 
> [0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan@amlogic.com
> [1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
> [2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan@amlogic.com
> [3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan@amlogic.com
> [4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan@amlogic.com
> [5] https://lkml.kernel.org/r/20180408031938.153474-1-yixun.lan@amlogic.com
> [6] https://lkml.kernel.org/r/20180409143749.71197-1-yixun.lan@amlogic.com
> [7] https://lkml.kernel.org/r/20180419135426.155794-1-yixun.lan@amlogic.com

Yixun,

Your series looks mostly Ok to me, apart from the problem reported by Philipp.

However, once applied, if the clkc ao controller is enabled, both gxl and axg
fail to complete the boot. Could you please explain how this was tested ??

Not merging it until we get to the bottom of this.

> 
> 
> Qiufang Dai (1):
>   clk: meson-axg: Add AO Clock and Reset controller driver
> 
> Yixun Lan (6):
>   clk: meson: migrate to devm_of_clk_add_hw_provider API
>   clk: meson: aoclk: refactor common code into dedicated file
>   dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
>   dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
>   clk: meson: drop CLK_SET_RATE_PARENT flag
>   clk: meson: drop CLK_IGNORE_UNUSED flag
> 
>  .../bindings/clock/amlogic,gxbb-aoclkc.txt    |   1 +
>  drivers/clk/meson/Kconfig                     |   8 +
>  drivers/clk/meson/Makefile                    |   3 +-
>  drivers/clk/meson/axg-aoclk.c                 | 163 ++++++++++++++++++
>  drivers/clk/meson/axg-aoclk.h                 |  29 ++++
>  drivers/clk/meson/gxbb-aoclk.c                |  95 ++++------
>  drivers/clk/meson/gxbb-aoclk.h                |   5 +
>  drivers/clk/meson/meson-aoclk.c               |  81 +++++++++
>  drivers/clk/meson/meson-aoclk.h               |  34 ++++
>  include/dt-bindings/clock/axg-aoclkc.h        |  26 +++
>  include/dt-bindings/reset/axg-aoclkc.h        |  20 +++
>  11 files changed, 401 insertions(+), 64 deletions(-)
>  create mode 100644 drivers/clk/meson/axg-aoclk.c
>  create mode 100644 drivers/clk/meson/axg-aoclk.h
>  create mode 100644 drivers/clk/meson/meson-aoclk.c
>  create mode 100644 drivers/clk/meson/meson-aoclk.h
>  create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
>  create mode 100644 include/dt-bindings/reset/axg-aoclkc.h
> 

Re: [PATCH v7 0/7] clk: meson-axg: Add AO Cloclk and Reset driver

[Yixun Lan]

hi Jerome:


On 04/27/18 17:20, Jerome Brunet wrote:
> On Thu, 2018-04-26 at 16:44 +0800, Yixun Lan wrote:
>>   This patch try to add AO clock and Reset driver for Amlogic's
>> Meson-AXG SoC.
>>   Please note that patch 7 need to wait for the DTS changes[3] merged
>> into mainline first, otherwise it will break the serial console.
>>
>>  patch 2: factor the common code into a dedicated file
>>  patch 3-5: add the aoclk driver for AXG SoC
>>  patch 6-7: drop unnecessary clock flags
>>
>> changes since v6 at [7]: 
>>  - fix over 80 chars chechpatch error
>>  - add Philip's Ack on patch 5
>>  - drop extra end of newline
>>
>> changes since v5 at [6]: 
>>  - drop unnecessary header files
>>  - add 'axg_aoclk' prefix to clk driver, make them more consistent
>>  - add missing end new line..
>>
>> changes since v4 at [5]: 
>>  - fix return err
>>  - introduce CONFIG_COMMON_CLK_MESON_AO
>>  - format/style minor fix
>>
>> changes since v3 at [4]: 
>>  - add 'const' contraint to the read-only data
>>  - switch to devm_of_clk_add_hw_provider API
>>  - check return value of devm_reset_controller_register
>>
>> changes since v2 at [2]: 
>>  - rework meson_aoclkc_probe() which leverage the of_match_data
>>  - merge patch 5-6 into this series
>>  - seperate DTS patch, will send to Kevin Hilman independently
>>  
>> changes since v1 at [0]: 
>>  - rebase to clk-meson's branch 'next/drivers' [1]
>>  - fix license, update to BSD-3-Clause
>>  - drop un-used include header file
>>
>> [0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan@amlogic.com
>> [1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
>> [2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan@amlogic.com
>> [3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan@amlogic.com
>> [4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan@amlogic.com
>> [5] https://lkml.kernel.org/r/20180408031938.153474-1-yixun.lan@amlogic.com
>> [6] https://lkml.kernel.org/r/20180409143749.71197-1-yixun.lan@amlogic.com
>> [7] https://lkml.kernel.org/r/20180419135426.155794-1-yixun.lan@amlogic.com
> 
> Yixun,
> 
> Your series looks mostly Ok to me, apart from the problem reported by Philipp.
> 
> However, once applied, if the clkc ao controller is enabled, both gxl and axg
> fail to complete the boot. Could you please explain how this was tested ??
> 

isn't this caused by the patch 7?
 [PATCH v7 7/7] clk: meson: drop CLK_IGNORE_UNUSED flag


you need to also apply this DT patch which I've sent[1]:
 [PATCH v3 3/3] ARM64: dts: meson: fix clock source of the pclk for UART_AO

could you exclude the patch 7 for now until Kevin merged the DT part?

[1] https://lkml.kernel.org/r/20180328030130.240336-4-yixun.lan@amlogic.com


> Not merging it until we get to the bottom of this.
> 
>>
>>
>> Qiufang Dai (1):
>>   clk: meson-axg: Add AO Clock and Reset controller driver
>>
>> Yixun Lan (6):
>>   clk: meson: migrate to devm_of_clk_add_hw_provider API
>>   clk: meson: aoclk: refactor common code into dedicated file
>>   dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
>>   dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
>>   clk: meson: drop CLK_SET_RATE_PARENT flag
>>   clk: meson: drop CLK_IGNORE_UNUSED flag
>>
>>  .../bindings/clock/amlogic,gxbb-aoclkc.txt    |   1 +
>>  drivers/clk/meson/Kconfig                     |   8 +
>>  drivers/clk/meson/Makefile                    |   3 +-
>>  drivers/clk/meson/axg-aoclk.c                 | 163 ++++++++++++++++++
>>  drivers/clk/meson/axg-aoclk.h                 |  29 ++++
>>  drivers/clk/meson/gxbb-aoclk.c                |  95 ++++------
>>  drivers/clk/meson/gxbb-aoclk.h                |   5 +
>>  drivers/clk/meson/meson-aoclk.c               |  81 +++++++++
>>  drivers/clk/meson/meson-aoclk.h               |  34 ++++
>>  include/dt-bindings/clock/axg-aoclkc.h        |  26 +++
>>  include/dt-bindings/reset/axg-aoclkc.h        |  20 +++
>>  11 files changed, 401 insertions(+), 64 deletions(-)
>>  create mode 100644 drivers/clk/meson/axg-aoclk.c
>>  create mode 100644 drivers/clk/meson/axg-aoclk.h
>>  create mode 100644 drivers/clk/meson/meson-aoclk.c
>>  create mode 100644 drivers/clk/meson/meson-aoclk.h
>>  create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
>>  create mode 100644 include/dt-bindings/reset/axg-aoclkc.h
>>
> 
> .
> 

Re: [PATCH v7 0/7] clk: meson-axg: Add AO Cloclk and Reset driver

[Jerome Brunet]

On Fri, 2018-04-27 at 17:31 +0800, Yixun Lan wrote:
> hi Jerome:
> 
> 
> On 04/27/18 17:20, Jerome Brunet wrote:
> > On Thu, 2018-04-26 at 16:44 +0800, Yixun Lan wrote:
> > >   This patch try to add AO clock and Reset driver for Amlogic's
> > > Meson-AXG SoC.
> > >   Please note that patch 7 need to wait for the DTS changes[3] merged
> > > into mainline first, otherwise it will break the serial console.
> > > 
> > >  patch 2: factor the common code into a dedicated file
> > >  patch 3-5: add the aoclk driver for AXG SoC
> > >  patch 6-7: drop unnecessary clock flags
> > > 
> > > changes since v6 at [7]: 
> > >  - fix over 80 chars chechpatch error
> > >  - add Philip's Ack on patch 5
> > >  - drop extra end of newline
> > > 
> > > changes since v5 at [6]: 
> > >  - drop unnecessary header files
> > >  - add 'axg_aoclk' prefix to clk driver, make them more consistent
> > >  - add missing end new line..
> > > 
> > > changes since v4 at [5]: 
> > >  - fix return err
> > >  - introduce CONFIG_COMMON_CLK_MESON_AO
> > >  - format/style minor fix
> > > 
> > > changes since v3 at [4]: 
> > >  - add 'const' contraint to the read-only data
> > >  - switch to devm_of_clk_add_hw_provider API
> > >  - check return value of devm_reset_controller_register
> > > 
> > > changes since v2 at [2]: 
> > >  - rework meson_aoclkc_probe() which leverage the of_match_data
> > >  - merge patch 5-6 into this series
> > >  - seperate DTS patch, will send to Kevin Hilman independently
> > >  
> > > changes since v1 at [0]: 
> > >  - rebase to clk-meson's branch 'next/drivers' [1]
> > >  - fix license, update to BSD-3-Clause
> > >  - drop un-used include header file
> > > 
> > > [0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan@amlogic.com
> > > [1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
> > > [2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan@amlogic.com
> > > [3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan@amlogic.com
> > > [4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan@amlogic.com
> > > [5] https://lkml.kernel.org/r/20180408031938.153474-1-yixun.lan@amlogic.com
> > > [6] https://lkml.kernel.org/r/20180409143749.71197-1-yixun.lan@amlogic.com
> > > [7] https://lkml.kernel.org/r/20180419135426.155794-1-yixun.lan@amlogic.com
> > 
> > Yixun,
> > 
> > Your series looks mostly Ok to me, apart from the problem reported by Philipp.
> > 
> > However, once applied, if the clkc ao controller is enabled, both gxl and axg
> > fail to complete the boot. Could you please explain how this was tested ??
> > 
> 
> isn't this caused by the patch 7?
>  [PATCH v7 7/7] clk: meson: drop CLK_IGNORE_UNUSED flag
> 
> 
> you need to also apply this DT patch which I've sent[1]:
>  [PATCH v3 3/3] ARM64: dts: meson: fix clock source of the pclk for UART_AO
> 
> could you exclude the patch 7 for now until Kevin merged the DT part?
> 
> [1] https://lkml.kernel.org/r/20180328030130.240336-4-yixun.lan@amlogic.com

Looks to be the problem indeed. But it is still an issue with how your patchset
in organized.

I can't merge this until Kevin merges the patch above, which he can't merge
until there is the clkc_ao support in axg, which is given by this series.

1# You should remove the axg part of the patch above. Kevin will be able to
merge it w/o any dependencies. (BTW, the patch is broken for axg because 1) you
did not include the dt-binding header for the clkc_ao in axg and 2) the clkc_ao
does not exist at this stage)
2# I can then safely merge this series - w/o breaking gxbb and gxl.
3# Finally you'll have to make a DT change for the axg, enabling the clkc_ao and
changes the uart clocks at the same time.

> 
> 
> > Not merging it until we get to the bottom of this.
> > 
> > > 
> > > 
> > > Qiufang Dai (1):
> > >   clk: meson-axg: Add AO Clock and Reset controller driver
> > > 
> > > Yixun Lan (6):
> > >   clk: meson: migrate to devm_of_clk_add_hw_provider API
> > >   clk: meson: aoclk: refactor common code into dedicated file
> > >   dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
> > >   dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
> > >   clk: meson: drop CLK_SET_RATE_PARENT flag
> > >   clk: meson: drop CLK_IGNORE_UNUSED flag
> > > 
> > >  .../bindings/clock/amlogic,gxbb-aoclkc.txt    |   1 +
> > >  drivers/clk/meson/Kconfig                     |   8 +
> > >  drivers/clk/meson/Makefile                    |   3 +-
> > >  drivers/clk/meson/axg-aoclk.c                 | 163 ++++++++++++++++++
> > >  drivers/clk/meson/axg-aoclk.h                 |  29 ++++
> > >  drivers/clk/meson/gxbb-aoclk.c                |  95 ++++------
> > >  drivers/clk/meson/gxbb-aoclk.h                |   5 +
> > >  drivers/clk/meson/meson-aoclk.c               |  81 +++++++++
> > >  drivers/clk/meson/meson-aoclk.h               |  34 ++++
> > >  include/dt-bindings/clock/axg-aoclkc.h        |  26 +++
> > >  include/dt-bindings/reset/axg-aoclkc.h        |  20 +++
> > >  11 files changed, 401 insertions(+), 64 deletions(-)
> > >  create mode 100644 drivers/clk/meson/axg-aoclk.c
> > >  create mode 100644 drivers/clk/meson/axg-aoclk.h
> > >  create mode 100644 drivers/clk/meson/meson-aoclk.c
> > >  create mode 100644 drivers/clk/meson/meson-aoclk.h
> > >  create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
> > >  create mode 100644 include/dt-bindings/reset/axg-aoclkc.h
> > > 
> > 
> > .
> > 
> 
> 

Re: [PATCH v7 0/7] clk: meson-axg: Add AO Cloclk and Reset driver

[Yixun Lan]

Hi Jerome:


On 04/27/2018 05:59 PM, Jerome Brunet wrote:
> On Fri, 2018-04-27 at 17:31 +0800, Yixun Lan wrote:
>> hi Jerome:
>>
>>
>> On 04/27/18 17:20, Jerome Brunet wrote:
>>> On Thu, 2018-04-26 at 16:44 +0800, Yixun Lan wrote:
>>>>   This patch try to add AO clock and Reset driver for Amlogic's
>>>> Meson-AXG SoC.
>>>>   Please note that patch 7 need to wait for the DTS changes[3] merged
>>>> into mainline first, otherwise it will break the serial console.
>>>>
>>>>  patch 2: factor the common code into a dedicated file
>>>>  patch 3-5: add the aoclk driver for AXG SoC
>>>>  patch 6-7: drop unnecessary clock flags
>>>>
>>>> changes since v6 at [7]: 
>>>>  - fix over 80 chars chechpatch error
>>>>  - add Philip's Ack on patch 5
>>>>  - drop extra end of newline
>>>>
>>>> changes since v5 at [6]: 
>>>>  - drop unnecessary header files
>>>>  - add 'axg_aoclk' prefix to clk driver, make them more consistent
>>>>  - add missing end new line..
>>>>
>>>> changes since v4 at [5]: 
>>>>  - fix return err
>>>>  - introduce CONFIG_COMMON_CLK_MESON_AO
>>>>  - format/style minor fix
>>>>
>>>> changes since v3 at [4]: 
>>>>  - add 'const' contraint to the read-only data
>>>>  - switch to devm_of_clk_add_hw_provider API
>>>>  - check return value of devm_reset_controller_register
>>>>
>>>> changes since v2 at [2]: 
>>>>  - rework meson_aoclkc_probe() which leverage the of_match_data
>>>>  - merge patch 5-6 into this series
>>>>  - seperate DTS patch, will send to Kevin Hilman independently
>>>>  
>>>> changes since v1 at [0]: 
>>>>  - rebase to clk-meson's branch 'next/drivers' [1]
>>>>  - fix license, update to BSD-3-Clause
>>>>  - drop un-used include header file
>>>>
>>>> [0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan@amlogic.com
>>>> [1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
>>>> [2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan@amlogic.com
>>>> [3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan@amlogic.com
>>>> [4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan@amlogic.com
>>>> [5] https://lkml.kernel.org/r/20180408031938.153474-1-yixun.lan@amlogic.com
>>>> [6] https://lkml.kernel.org/r/20180409143749.71197-1-yixun.lan@amlogic.com
>>>> [7] https://lkml.kernel.org/r/20180419135426.155794-1-yixun.lan@amlogic.com
>>>
>>> Yixun,
>>>
>>> Your series looks mostly Ok to me, apart from the problem reported by Philipp.
>>>
>>> However, once applied, if the clkc ao controller is enabled, both gxl and axg
>>> fail to complete the boot. Could you please explain how this was tested ??
>>>
>>
>> isn't this caused by the patch 7?
>>  [PATCH v7 7/7] clk: meson: drop CLK_IGNORE_UNUSED flag
>>
>>
>> you need to also apply this DT patch which I've sent[1]:
>>  [PATCH v3 3/3] ARM64: dts: meson: fix clock source of the pclk for UART_AO
>>
>> could you exclude the patch 7 for now until Kevin merged the DT part?
>>
>> [1] https://lkml.kernel.org/r/20180328030130.240336-4-yixun.lan@amlogic.com
> 
> Looks to be the problem indeed. But it is still an issue with how your patchset
> in organized.
> 
> I can't merge this until Kevin merges the patch above, which he can't merge
> until there is the clkc_ao support in axg, which is given by this series.
> 
> 1# You should remove the axg part of the patch above. Kevin will be able to
> merge it w/o any dependencies. (BTW, the patch is broken for axg because 1) you
> did not include the dt-binding header for the clkc_ao in axg and 2) the clkc_ao
> does not exist at this stage)
> 2# I can then safely merge this series - w/o breaking gxbb and gxl.
> 3# Finally you'll have to make a DT change for the axg, enabling the clkc_ao and
> changes the uart clocks at the same time.
> 

  I didn't make myself clear in previous email

  I mean, could you merge patch 1-6, just exclude the patch 7
then kevin can merge the DT part (there are three patches) [1]
after the DT patches merged, then you can take this patch 7
This way, it won't break gxl or any other SoCs

  I'm sending patch 7 along with this series, it would be better if I
give a warning about it.

[1] https://lkml.kernel.org/r20180328030130.240336-1-yixun.lan@amlogic.com

>>
>>
>>> Not merging it until we get to the bottom of this.
>>>
>>>>
>>>>
>>>> Qiufang Dai (1):
>>>>   clk: meson-axg: Add AO Clock and Reset controller driver
>>>>
>>>> Yixun Lan (6):
>>>>   clk: meson: migrate to devm_of_clk_add_hw_provider API
>>>>   clk: meson: aoclk: refactor common code into dedicated file
>>>>   dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
>>>>   dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
>>>>   clk: meson: drop CLK_SET_RATE_PARENT flag
>>>>   clk: meson: drop CLK_IGNORE_UNUSED flag
>>>>
>>>>  .../bindings/clock/amlogic,gxbb-aoclkc.txt    |   1 +
>>>>  drivers/clk/meson/Kconfig                     |   8 +
>>>>  drivers/clk/meson/Makefile                    |   3 +-
>>>>  drivers/clk/meson/axg-aoclk.c                 | 163 ++++++++++++++++++
>>>>  drivers/clk/meson/axg-aoclk.h                 |  29 ++++
>>>>  drivers/clk/meson/gxbb-aoclk.c                |  95 ++++------
>>>>  drivers/clk/meson/gxbb-aoclk.h                |   5 +
>>>>  drivers/clk/meson/meson-aoclk.c               |  81 +++++++++
>>>>  drivers/clk/meson/meson-aoclk.h               |  34 ++++
>>>>  include/dt-bindings/clock/axg-aoclkc.h        |  26 +++
>>>>  include/dt-bindings/reset/axg-aoclkc.h        |  20 +++
>>>>  11 files changed, 401 insertions(+), 64 deletions(-)
>>>>  create mode 100644 drivers/clk/meson/axg-aoclk.c
>>>>  create mode 100644 drivers/clk/meson/axg-aoclk.h
>>>>  create mode 100644 drivers/clk/meson/meson-aoclk.c
>>>>  create mode 100644 drivers/clk/meson/meson-aoclk.h
>>>>  create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
>>>>  create mode 100644 include/dt-bindings/reset/axg-aoclkc.h
>>>>
>>>
>>> .
>>>
>>
>>
> 
> .
> 

Re: [PATCH v7 0/7] clk: meson-axg: Add AO Cloclk and Reset driver

[Kevin Hilman]

Hi Yixun,

Yixun Lan <yixun.lan@amlogic.com> writes:

> On 04/27/2018 05:59 PM, Jerome Brunet wrote:

[...]

>> 
>> Looks to be the problem indeed. But it is still an issue with how your patchset
>> in organized.
>> 
>> I can't merge this until Kevin merges the patch above, which he can't merge
>> until there is the clkc_ao support in axg, which is given by this series.
>> 
>> 1# You should remove the axg part of the patch above. Kevin will be able to
>> merge it w/o any dependencies. (BTW, the patch is broken for axg because 1) you
>> did not include the dt-binding header for the clkc_ao in axg and 2) the clkc_ao
>> does not exist at this stage)
>> 2# I can then safely merge this series - w/o breaking gxbb and gxl.
>> 3# Finally you'll have to make a DT change for the axg, enabling the clkc_ao and
>> changes the uart clocks at the same time.
>> 
>
>   I didn't make myself clear in previous email
>
>   I mean, could you merge patch 1-6, just exclude the patch 7
> then kevin can merge the DT part (there are three patches) [1]
> after the DT patches merged, then you can take this patch 7
> This way, it won't break gxl or any other SoCs
>
>   I'm sending patch 7 along with this series, it would be better if I
> give a warning about it.

Your proposal requires extra work from a couple different maintainers to
track all the dependencies, and is very error prone.  Sometimes
maintainers may do this for you if they have time and are feeling
generous, but you will have much more success if you can ease the
process.

Jerome has provided lots of guidance throughout this series and just
above has provided you with a very good proposal above which minimizes
the dependencies, and provides the changes in the right order.

Please follow Jerome's suggestion,

Thanks,

Kevin

Re: [PATCH v7 0/7] clk: meson-axg: Add AO Cloclk and Reset driver

[Yixun Lan]

Hi Kevin

On 04/28/18 02:49, Kevin Hilman wrote:
> Hi Yixun,
> 
> Yixun Lan <yixun.lan@amlogic.com> writes:
> 
>> On 04/27/2018 05:59 PM, Jerome Brunet wrote:
> 
> [...]
> 
>>>
>>> Looks to be the problem indeed. But it is still an issue with how your patchset
>>> in organized.
>>>
>>> I can't merge this until Kevin merges the patch above, which he can't merge
>>> until there is the clkc_ao support in axg, which is given by this series.
>>>
>>> 1# You should remove the axg part of the patch above. Kevin will be able to
>>> merge it w/o any dependencies. (BTW, the patch is broken for axg because 1) you
>>> did not include the dt-binding header for the clkc_ao in axg and 2) the clkc_ao
>>> does not exist at this stage)
>>> 2# I can then safely merge this series - w/o breaking gxbb and gxl.
>>> 3# Finally you'll have to make a DT change for the axg, enabling the clkc_ao and
>>> changes the uart clocks at the same time.
>>>
>>
>>   I didn't make myself clear in previous email
>>
>>   I mean, could you merge patch 1-6, just exclude the patch 7
>> then kevin can merge the DT part (there are three patches) [1]
>> after the DT patches merged, then you can take this patch 7
>> This way, it won't break gxl or any other SoCs
>>

>>   I'm sending patch 7 along with this series, it would be better if I
>> give a warning about it.
> 
> Your proposal requires extra work from a couple different maintainers to
> track all the dependencies, and is very error prone.  Sometimes
> maintainers may do this for you if they have time and are feeling
> generous, but you will have much more success if you can ease the
> process.
> 
Indeed

 I've actually put a note in the cover letter to highlight special
attention needed for patch 7, but turns out rely on maintainers to
handle the dependencies isn't a wise idea
 Lesson has been learned here, and I'll handle dependencies myself next
time.


> Jerome has provided lots of guidance throughout this series and just
> above has provided you with a very good proposal above which minimizes
> the dependencies, and provides the changes in the right order.
> 
> Please follow Jerome's suggestion,
> 
as already replied in my previous email, again here is my approach

a) I'll send patch 2-6, just leave out patch 7 for now, and as patch 1
is already accepted.. this way it won't break gxbb/gxl (the OLD SoC)
b) will pin you to require DT patch merged or re-send if necessary (as
till now the clkao driver is merged)
c) send out the patch 7 for UART AO clock fix

this is exactly what Jerome suggested..

Thank you

Yixun