From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E033FA3740 for ; Thu, 27 Oct 2022 21:59:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237168AbiJ0V7h (ORCPT ); Thu, 27 Oct 2022 17:59:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236639AbiJ0V7f (ORCPT ); Thu, 27 Oct 2022 17:59:35 -0400 Received: from mail-qv1-xf2c.google.com (mail-qv1-xf2c.google.com [IPv6:2607:f8b0:4864:20::f2c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D621126D3 for ; Thu, 27 Oct 2022 14:59:31 -0700 (PDT) Received: by mail-qv1-xf2c.google.com with SMTP id e15so2733890qvo.4 for ; Thu, 27 Oct 2022 14:59:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=q7ugP0tq/kTqwapqa/g5RjNpPzZRDaE9uddOPhLuISc=; b=o7sW47GHzXAoiD2j6H6QFu/7GUf/pA0/oDdbcm6+sZ9bOmjpAo/qB24B0IowZvt9P+ uEs+wbUUSlkmnLlVdNkn65fxdk5zBa5isbU+FAL+wpT+pO1YhGTdX2/pgOan1gvHNCPl 9qVN6T8ALdciWQ3Oo6k2+p55TKJ4AkaLgvxO0mveT+TCFzB/fAyxkViEbfJuupiToNIT NQQWZo2QRbvY79zCmS+btF6flLLVtGFS+nGdVlM9nxoJw0C4oyKnyiBlDa+GMxDYAbRT Yl7yiRraviHFOwYRsvBF8ogkgaSuOEtsuk8P1O7ywuqYPLFqDn6QWUmaDLBhaxsQL30e +N2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=q7ugP0tq/kTqwapqa/g5RjNpPzZRDaE9uddOPhLuISc=; b=NgZW5sBz3DVQRyShHowWFj/QA2VRUheyOf7KPmw9U6ESM6V2LA2Qh5GcGP2jRp0gZE w6X0NHx10b8uoPeLZaM8f7tg2lQBhauuIahQBejZgQpfi4WR1jOId3k/Px301FWd4/r7 0EbxFjEYrTIxByxH5HXX1kF6NgeBI3SLASFjgDz6UvICjII06bph8JyufF1Hde/QNOgf ZGjxd1L1UUyxqlVMeBb7mf2tXxtvZPu1KtvVzz6rUqCOVvW54A/WLy9aZKK4nWdBj08P SW2FYkT8ZavtSarbi184SMY9rnn0p41lGvP8gZoiPmK5IIiRk5DpGAjP2W7g4U1J/PhU S7cw== X-Gm-Message-State: ACrzQf2nrSHA810amgOv6n00vuyPpfrpOvd+IWMJ5UYU20Y5vmNb/6Hg KS+/kClHuh8hRLKdUduvCKspRA== X-Google-Smtp-Source: AMsMyM4FZ19Rf+aeDh57uIFiQqlt84X/FMAN2OviCklU/tLpK688yp4VPjiM2ZG3IyKbfArb+7ea7Q== X-Received: by 2002:a05:6214:20a7:b0:4bb:9359:8368 with SMTP id 7-20020a05621420a700b004bb93598368mr10237414qvd.122.1666907971077; Thu, 27 Oct 2022 14:59:31 -0700 (PDT) Received: from [192.168.1.11] ([64.57.193.93]) by smtp.gmail.com with ESMTPSA id k10-20020a05620a414a00b006be8713f742sm1794489qko.38.2022.10.27.14.59.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Oct 2022 14:59:30 -0700 (PDT) Message-ID: <2c8c4642-8aee-3da3-7698-5e08b4c5894d@linaro.org> Date: Thu, 27 Oct 2022 17:59:28 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Subject: Re: [PATCH v3 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings Content-Language: en-US To: Melody Olvera , Stephen Boyd , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Marc Zyngier , Michael Turquette , Rob Herring , Thomas Gleixner Cc: Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221026190441.4002212-1-quic_molvera@quicinc.com> <20221026190441.4002212-2-quic_molvera@quicinc.com> <20221027182449.366AEC433D6@smtp.kernel.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 27/10/2022 17:28, Melody Olvera wrote: >>>>> + - description: Board XO source >>>>> + - description: Sleep clock source >>>>> + - description: PCIE 0 Pipe clock source >>>>> + - description: PCIE 0 Phy Auxiliary clock source >>>>> + - description: USB3 Phy wrapper pipe clock source >>>>> + minItems: 2 >>>> Why the clocks are optional? >>> They should not be optional. They're always there. >> Just to be sure - I refer to last three clocks here as indicated by >> minItems:2. >> >> DTS does not define them, so something here is not complete or correct. >> > DT is incomplete; I don't have that in my current patchset. Will add later when PCIE and > USB nodes are complete. Bindings should be complete as much as possible, therefore please define in the DTS stub clocks (fixed clocks) to fill these with a TODO notes. Best regards, Krzysztof