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Mon, 12 Oct 2026 00:40:28 -0700 (PDT) X-Received: by 2002:a05:622a:e0cf:10b0:533:6948:3d2b with SMTP id d75a77b69052e-5359f4990d7mr117219061cf.1.1791790827961; Mon, 12 Oct 2026 00:40:27 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c31a9accf47sm429403466b.76.2026.10.12.00.40.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 12 Oct 2026 00:40:26 -0700 (PDT) Message-ID: <2ca0fff3-aadc-4dcd-93e8-df2ffbac08ab@oss.qualcomm.com> Date: Mon, 12 Oct 2026 09:40:24 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/5] arm64: dts: qcom: nord: Add PCIe PHY and controller nodes To: Shawn Guo , Krishna Chaitanya Chundru Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Yu Zhang , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Bartosz Golaszewski References: <20260915015632.283642-1-shengchao.guo@oss.qualcomm.com> <20260915015632.283642-2-shengchao.guo@oss.qualcomm.com> <086f87b9-9b9a-4acb-b18c-be37cd6558da@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEyMDAzMCBTYWx0ZWRfX6XLB+maFDqVY 5F0DHKLX34lI1Xle5ml0DmSeNvfXhwQEehAYcnpSrGGgmAWN79H5FD/9I4lmTOytpRoTeaITdIC J54+CchcWh4oRsPgQB1+DaNniOkV5IM= X-Proofpoint-GUID: ZHyEoWEgsYf6CCsiA0bQovWSwz21MgII X-Proofpoint-ORIG-GUID: ZHyEoWEgsYf6CCsiA0bQovWSwz21MgII X-Authority-Analysis: v=2.4 cv=ePGGH3p1 c=1 sm=1 tr=0 ts=6acc8eed cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=BjiBRVP3CVE4MUQrlPQA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEyMDAzMCBTYWx0ZWRfX1s567ZZMsSec YuN/uBzEetq99kzY37hiKy0OrVFYtlGcE60n7y96oFHFLIstZtCvArP9NSygpU6Rp5HULCL0Akr QLZG/HDGB3kkobXQJ/i5s2jXIbrwF5nVU8RZ9p1UVKlKcsUZ3Wy3M9Kh9pCDY3MtKDgs7v+/lIb 1AW6NJCwjcpfSLmCp9u5OM3orI89XN/uATAJlcfM9xmQmx3t7rDCMWb0R9I7+oKaXVgniwhE5LI bG6fGXO5Qt35FjMy6vPLkUm0lzBEg0NJRoRYroJObRvgC8MS76G//FJTjWK4UWSnXgHxfxhwA98 NSVcJ8FFbZlNuQl3DkG2w69TuTn8Ad8EYR3Bq6LGjdY9djOThp/uf7khKzn/VfwnYqWvTosZlNZ zKKcx8aw5CAcGHflTQVZthUimbR/ES0NTwUwTFb5h8jzZfqBD098gfozb4H0P1ESXMm+rmX6VgJ EsQUYW8oHw+ZCsjM+tw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-12_02,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 impostorscore=0 malwarescore=0 adultscore=0 bulkscore=0 phishscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610120030 On 10/12/26 8:37 AM, Shawn Guo wrote: > On Mon, Oct 12, 2026 at 10:52:34AM +0530, Krishna Chaitanya Chundru wrote: >> >> >> On 10/10/2026 8:04 AM, Shawn Guo wrote: >>> On Tue, Sep 15, 2026 at 09:56:28AM +0800, Shawn Guo wrote: >>>> From: Krishna Chaitanya Chundru [...] >>>> + perst-pins { >>>> + pins = "gpio2"; >>>> + function = "gpio"; >>>> + drive-strength = <2>; >>>> + bias-disable; >>>> + }; >>> pcie0_clk_req_n is a SoC level pin function, so it has a good reason to >>> stay here. But wake and perst are board chosen GPIOs. I think they should >>> go to board DTS. >> Shawn, I don't see perst and wake gpios are changing per board, for that >> reason I added them here, but such requirement is coming we can move them to >> board file. > > Well, we have only seen Ride and RRD so far. We never know how other Nord > based boards to come will choose the perst and wake GPIOs. This is > simply a board level configuration and should go to board dts. They never do in practice (for a good reason, the reference-chosen pins are consecutive and presumably next to each other) and we have no occurences of that in the tree across the hundreds of devices. Konrad