* [PATCH 0/5] Add UFS support for SM8750
@ 2025-01-13 21:46 Melody Olvera
2025-01-13 21:46 ` [PATCH 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY Melody Olvera
` (5 more replies)
0 siblings, 6 replies; 37+ messages in thread
From: Melody Olvera @ 2025-01-13 21:46 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
Melody Olvera, Nitin Rawat, Manish Pandey
Add UFS support for SM8750 SoCs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
Nitin Rawat (5):
dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY
phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
dt-bindings: ufs: qcom: Document the SM8750 UFS Controller
arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards
.../bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 +
.../devicetree/bindings/ufs/qcom,ufs.yaml | 2 +
arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 18 +++
arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 18 +++
arch/arm64/boot/dts/qcom/sm8750.dtsi | 81 ++++++++++
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 12 ++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h | 68 ++++++++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 174 ++++++++++++++++++++-
8 files changed, 374 insertions(+), 1 deletion(-)
---
base-commit: 37136bf5c3a6f6b686d74f41837a6406bec6b7bc
change-id: 20250107-sm8750_ufs_master-9a41106104a7
Best regards,
--
Melody Olvera <quic_molvera@quicinc.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY
2025-01-13 21:46 [PATCH 0/5] Add UFS support for SM8750 Melody Olvera
@ 2025-01-13 21:46 ` Melody Olvera
2025-01-18 14:44 ` Krzysztof Kozlowski
2025-01-13 21:46 ` [PATCH 2/5] phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750 Melody Olvera
` (4 subsequent siblings)
5 siblings, 1 reply; 37+ messages in thread
From: Melody Olvera @ 2025-01-13 21:46 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
Melody Olvera, Nitin Rawat
From: Nitin Rawat <quic_nitirawa@quicinc.com>
Document the QMP UFS PHY on the SM8750 Platform.
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index 72bed2933b034ff61a29fafebfa176383086e440..a58370a6a5d389cd0118e7b4650c6ff960bf86fa 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -44,6 +44,7 @@ properties:
- qcom,sm8475-qmp-ufs-phy
- qcom,sm8550-qmp-ufs-phy
- qcom,sm8650-qmp-ufs-phy
+ - qcom,sm8750-qmp-ufs-phy
reg:
maxItems: 1
@@ -111,6 +112,7 @@ allOf:
- qcom,sm8475-qmp-ufs-phy
- qcom,sm8550-qmp-ufs-phy
- qcom,sm8650-qmp-ufs-phy
+ - qcom,sm8750-qmp-ufs-phy
then:
properties:
clocks:
--
2.46.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 2/5] phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
2025-01-13 21:46 [PATCH 0/5] Add UFS support for SM8750 Melody Olvera
2025-01-13 21:46 ` [PATCH 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY Melody Olvera
@ 2025-01-13 21:46 ` Melody Olvera
2025-01-14 9:00 ` neil.armstrong
2025-01-14 10:49 ` Dmitry Baryshkov
2025-01-13 21:46 ` [PATCH 3/5] dt-bindings: ufs: qcom: Document the SM8750 UFS Controller Melody Olvera
` (3 subsequent siblings)
5 siblings, 2 replies; 37+ messages in thread
From: Melody Olvera @ 2025-01-13 21:46 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
Melody Olvera, Nitin Rawat, Manish Pandey
From: Nitin Rawat <quic_nitirawa@quicinc.com>
Add SM8750 specific register layout and table configs. The serdes
TX RX register offset has changed for SM8750 and hence keep UFS
specific serdes offsets in a dedicated header file.
Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 12 ++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h | 68 ++++++++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 174 ++++++++++++++++++++-
3 files changed, 253 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
index 328c6c0b0b09ae4ff5bf14e846772e6d0f31ce5a..aa2278f9377408b3c602f6fa0de5021804f21f52 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
@@ -86,4 +86,16 @@
#define QSERDES_V6_COM_CMN_STATUS 0x1d0
#define QSERDES_V6_COM_C_READY_STATUS 0x1f8
+#define QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG 0x268
+#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0 0x26c
+#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x270
+#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x274
+#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58
+
+#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c
+#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1 0x278
+#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x27c
+#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x280
+#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
+#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
new file mode 100644
index 0000000000000000000000000000000000000000..73b3857e0277ce6cdbe658066772172a94f25d6e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
+
+#define QSERDES_UFS_V7_TX_RES_CODE_LANE_TX 0x28
+#define QSERDES_UFS_V7_TX_RES_CODE_LANE_RX 0x2c
+#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX 0x30
+#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX 0x34
+#define QSERDES_UFS_V7_TX_LANE_MODE_1 0x7c
+#define QSERDES_UFS_V7_TX_FR_DCC_CTRL 0x108
+
+#define QSERDES_UFS_V7_RX_UCDR_SO_SATURATION 0x28
+#define QSERDES_UFS_V7_RX_UCDR_PI_CTRL1 0x58
+#define QSERDES_UFS_V7_RX_TERM_BW_CTRL0 0xC4
+#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0 0x218
+#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1 0x21C
+#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2 0x220
+#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3 0x224
+#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4 0x228
+#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6 0x230
+#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7 0x234
+#define QSERDES_UFS_V7_RX_MODE_RATE2_B3 0x248
+#define QSERDES_UFS_V7_RX_MODE_RATE2_B6 0x254
+#define QSERDES_UFS_V7_RX_MODE_RATE2_B7 0x258
+#define QSERDES_UFS_V7_RX_MODE_RATE3_B0 0x260
+#define QSERDES_UFS_V7_RX_MODE_RATE3_B1 0x264
+#define QSERDES_UFS_V7_RX_MODE_RATE3_B2 0x268
+#define QSERDES_UFS_V7_RX_MODE_RATE3_B3 0x26C
+#define QSERDES_UFS_V7_RX_MODE_RATE3_B4 0x270
+#define QSERDES_UFS_V7_RX_MODE_RATE3_B5 0x274
+#define QSERDES_UFS_V7_RX_MODE_RATE3_B7 0x27C
+#define QSERDES_UFS_V7_RX_MODE_RATE3_B8 0x280
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0 0x284
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1 0x288
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2 0x28C
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3 0x290
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4 0x294
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5 0x298
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6 0x29C
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7 0x2A0
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0 0x2A8
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1 0x2AC
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2 0x2B0
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3 0x2B4
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4 0x2B8
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5 0x2BC
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6 0x2C0
+#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7 0x2C4
+#define QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL 0x348
+#define QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM 0x380
+#define QSERDES_UFS_V7_RX_INTERFACE_MODE 0x1F0
+#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2 0xD4
+#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4 0xDC
+#define QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4 0xF0
+#define QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS 0xF4
+#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
+#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
+#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
+#define QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1CC
+#define QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3 0x1D4
+#define QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4 0x1B4
+#define QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL 0x178
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index d964bdfe870029226482f264c78a27d0ec43bf2b..a1695b368fe7622bf8663343d0241b4d0d40ab59 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -31,6 +31,7 @@
#include "phy-qcom-qmp-pcs-ufs-v6.h"
#include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
+#include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h"
/* QPHY_PCS_READY_STATUS bit */
#define PCS_READY BIT(0)
@@ -949,6 +950,132 @@ static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
};
+static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xD9),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x60),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1F),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1F),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7F),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4C),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xBE),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
+};
+
+static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_LANE_MODE_1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x17),
+};
+
+static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0C),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0C),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0E),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1C),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0x8E),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0F),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xCE),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xCE),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1A),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0F),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9A),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xE2),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1B),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1B),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9B),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2A),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5F),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xE3),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x9B),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x9B),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0x60),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5F),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xFB),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1F),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xFA),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77),
+};
+
+static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0F),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0E),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19),
+};
+
+static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
+};
+
+static const struct qmp_phy_init_tbl sm8750_ufsphy_g5_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
+};
+
+static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x41),
+};
+
struct qmp_ufs_offsets {
u16 serdes;
u16 pcs;
@@ -1523,6 +1650,45 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
.regs = ufsphy_v6_regs_layout,
};
+static const struct qmp_phy_cfg sm8750_ufsphy_cfg = {
+ .lanes = 2,
+
+ .offsets = &qmp_ufs_offsets_v6,
+ .max_supported_gear = UFS_HS_G5,
+
+ .tbls = {
+ .serdes = sm8750_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes),
+ .tx = sm8750_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8750_ufsphy_tx),
+ .rx = sm8750_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm8750_ufsphy_rx),
+ .pcs = sm8750_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs),
+ },
+
+ .tbls_hs_b = {
+ .pcs = sm8750_ufsphy_hs_b_pcs,
+ .pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs),
+ },
+
+ .tbls_hs_overlay[0] = {
+ .pcs = sm8750_ufsphy_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
+ },
+ .tbls_hs_overlay[1] = {
+ .pcs = sm8750_ufsphy_g5_pcs,
+ .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g5_pcs),
+ .max_gear = UFS_HS_G5,
+ },
+
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = ufsphy_v6_regs_layout,
+
+};
+
static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
{
void __iomem *serdes = qmp->serdes;
@@ -1593,8 +1759,10 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg
qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
}
- if (qmp->mode == PHY_MODE_UFS_HS_B)
+ if (qmp->mode == PHY_MODE_UFS_HS_B) {
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
+ qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_b);
+ }
}
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
@@ -2061,7 +2229,11 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
}, {
.compatible = "qcom,sm8650-qmp-ufs-phy",
.data = &sm8650_ufsphy_cfg,
+ }, {
+ .compatible = "qcom,sm8750-qmp-ufs-phy",
+ .data = &sm8750_ufsphy_cfg,
},
+
{ },
};
MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);
--
2.46.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 3/5] dt-bindings: ufs: qcom: Document the SM8750 UFS Controller
2025-01-13 21:46 [PATCH 0/5] Add UFS support for SM8750 Melody Olvera
2025-01-13 21:46 ` [PATCH 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY Melody Olvera
2025-01-13 21:46 ` [PATCH 2/5] phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750 Melody Olvera
@ 2025-01-13 21:46 ` Melody Olvera
2025-01-18 14:45 ` Krzysztof Kozlowski
2025-01-13 21:46 ` [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC Melody Olvera
` (2 subsequent siblings)
5 siblings, 1 reply; 37+ messages in thread
From: Melody Olvera @ 2025-01-13 21:46 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
Melody Olvera, Nitin Rawat
From: Nitin Rawat <quic_nitirawa@quicinc.com>
Document the UFS Controller on the SM8750 Platform.
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index cde334e3206b0aa07ff18db0765eb17e7466b1e5..4bf980f6cf2b1b10d909f27fb4ee7afa2a5be484 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -42,6 +42,7 @@ properties:
- qcom,sm8450-ufshc
- qcom,sm8550-ufshc
- qcom,sm8650-ufshc
+ - qcom,sm8750-ufshc
- const: qcom,ufshc
- const: jedec,ufs-2.0
@@ -157,6 +158,7 @@ allOf:
- qcom,sm8450-ufshc
- qcom,sm8550-ufshc
- qcom,sm8650-ufshc
+ - qcom,sm8750-ufshc
then:
properties:
clocks:
--
2.46.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
2025-01-13 21:46 [PATCH 0/5] Add UFS support for SM8750 Melody Olvera
` (2 preceding siblings ...)
2025-01-13 21:46 ` [PATCH 3/5] dt-bindings: ufs: qcom: Document the SM8750 UFS Controller Melody Olvera
@ 2025-01-13 21:46 ` Melody Olvera
2025-01-14 10:52 ` Dmitry Baryshkov
` (3 more replies)
2025-01-13 21:46 ` [PATCH 5/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards Melody Olvera
2025-02-07 22:47 ` [PATCH 0/5] Add UFS support for SM8750 Konrad Dybcio
5 siblings, 4 replies; 37+ messages in thread
From: Melody Olvera @ 2025-01-13 21:46 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
Melody Olvera, Nitin Rawat, Manish Pandey
From: Nitin Rawat <quic_nitirawa@quicinc.com>
Add UFS host controller and PHY nodes for SM8750 SoC.
Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 81 ++++++++++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..20690c102244b337847a6482dd83c37e19746de9 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
interrupt-parent = <&intc>;
@@ -1939,6 +1940,86 @@ mmss_noc: interconnect@1780000 {
#interconnect-cells = <2>;
};
+ ufs_mem_phy: phy@1d80000 {
+ compatible = "qcom,sm8750-qmp-ufs-phy";
+ reg = <0x0 0x01d80000 0x0 0x2000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&tcsrcc TCSR_UFS_CLKREF_EN>;
+ clock-names = "ref",
+ "ref_aux",
+ "qref";
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+
+ power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ufs_mem_hc: ufs@1d84000 {
+ compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+ reg = <0x0 0x01d84000 0x0 0x3000>;
+
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_LN_BB_CLK3>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ freq-table-hz = <100000000 403000000>,
+ <0 0>,
+ <0 0>,
+ <100000000 403000000>,
+ <100000000 403000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+
+ interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ufs-ddr",
+ "cpu-ufs";
+
+ power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ iommus = <&apps_smmu 0x60 0>;
+ dma-coherent;
+
+ lanes-per-direction = <2>;
+
+ phys = <&ufs_mem_phy>;
+ phy-names = "ufsphy";
+
+ #reset-cells = <1>;
+
+ status = "disabled";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
--
2.46.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 5/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards
2025-01-13 21:46 [PATCH 0/5] Add UFS support for SM8750 Melody Olvera
` (3 preceding siblings ...)
2025-01-13 21:46 ` [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC Melody Olvera
@ 2025-01-13 21:46 ` Melody Olvera
2025-01-18 15:26 ` Krzysztof Kozlowski
2025-01-27 10:20 ` Konrad Dybcio
2025-02-07 22:47 ` [PATCH 0/5] Add UFS support for SM8750 Konrad Dybcio
5 siblings, 2 replies; 37+ messages in thread
From: Melody Olvera @ 2025-01-13 21:46 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
Melody Olvera, Nitin Rawat, Manish Pandey
From: Nitin Rawat <quic_nitirawa@quicinc.com>
Add UFS host controller and PHY nodes for SM8750 QRD and MTP boards.
Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 18 ++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 18 ++++++++++++++++++
2 files changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
index 9e3aacad7bdab6848e86f8e45e04907e1c752a07..9d34159e73948e7f3f939593d1ace444cc5dcd15 100644
--- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
@@ -792,3 +792,21 @@ &tlmm {
&uart7 {
status = "okay";
};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1j_0p91>;
+ vdda-pll-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 215 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1d_1p2>;
+ vccq-max-microamp = <1200000>;
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
index f77efab0aef9bab751a947173bcdcc27df7295a8..8dd82494ba5aea6e6b5ddafc9299ec68dfb84bcd 100644
--- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
@@ -790,3 +790,21 @@ &tlmm {
&uart7 {
status = "okay";
};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1j_0p91>;
+ vdda-pll-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 215 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1d_1p2>;
+ vccq-max-microamp = <1200000>;
+
+ status = "okay";
+};
--
2.46.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH 2/5] phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
2025-01-13 21:46 ` [PATCH 2/5] phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750 Melody Olvera
@ 2025-01-14 9:00 ` neil.armstrong
2025-01-14 10:49 ` Dmitry Baryshkov
1 sibling, 0 replies; 37+ messages in thread
From: neil.armstrong @ 2025-01-14 9:00 UTC (permalink / raw)
To: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
Nitin Rawat, Manish Pandey
On 13/01/2025 22:46, Melody Olvera wrote:
> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>
> Add SM8750 specific register layout and table configs. The serdes
> TX RX register offset has changed for SM8750 and hence keep UFS
> specific serdes offsets in a dedicated header file.
>
> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 12 ++
> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h | 68 ++++++++
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 174 ++++++++++++++++++++-
> 3 files changed, 253 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> index 328c6c0b0b09ae4ff5bf14e846772e6d0f31ce5a..aa2278f9377408b3c602f6fa0de5021804f21f52 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> @@ -86,4 +86,16 @@
> #define QSERDES_V6_COM_CMN_STATUS 0x1d0
> #define QSERDES_V6_COM_C_READY_STATUS 0x1f8
>
> +#define QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG 0x268
> +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0 0x26c
> +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x270
> +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x274
> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58
> +
> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c
> +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1 0x278
> +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x27c
> +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x280
> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54
> #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..73b3857e0277ce6cdbe658066772172a94f25d6e
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
> @@ -0,0 +1,68 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2024, Linaro Limited
> + */
> +
> +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
> +#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
> +
> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_TX 0x28
> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_RX 0x2c
> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX 0x30
> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX 0x34
> +#define QSERDES_UFS_V7_TX_LANE_MODE_1 0x7c
> +#define QSERDES_UFS_V7_TX_FR_DCC_CTRL 0x108
> +
> +#define QSERDES_UFS_V7_RX_UCDR_SO_SATURATION 0x28
> +#define QSERDES_UFS_V7_RX_UCDR_PI_CTRL1 0x58
> +#define QSERDES_UFS_V7_RX_TERM_BW_CTRL0 0xC4
> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0 0x218
> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1 0x21C
> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2 0x220
> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3 0x224
> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4 0x228
> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6 0x230
> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7 0x234
> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B3 0x248
> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B6 0x254
> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B7 0x258
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B0 0x260
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B1 0x264
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B2 0x268
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B3 0x26C
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B4 0x270
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B5 0x274
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B7 0x27C
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B8 0x280
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0 0x284
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1 0x288
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2 0x28C
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3 0x290
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4 0x294
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5 0x298
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6 0x29C
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7 0x2A0
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0 0x2A8
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1 0x2AC
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2 0x2B0
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3 0x2B4
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4 0x2B8
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5 0x2BC
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6 0x2C0
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7 0x2C4
> +#define QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL 0x348
> +#define QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM 0x380
> +#define QSERDES_UFS_V7_RX_INTERFACE_MODE 0x1F0
> +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2 0xD4
> +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4 0xDC
> +#define QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4 0xF0
> +#define QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS 0xF4
> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> +#define QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1CC
> +#define QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3 0x1D4
> +#define QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4 0x1B4
> +#define QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL 0x178
> +
> +#endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index d964bdfe870029226482f264c78a27d0ec43bf2b..a1695b368fe7622bf8663343d0241b4d0d40ab59 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -31,6 +31,7 @@
> #include "phy-qcom-qmp-pcs-ufs-v6.h"
>
> #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
> +#include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h"
>
> /* QPHY_PCS_READY_STATUS bit */
> #define PCS_READY BIT(0)
> @@ -949,6 +950,132 @@ static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = {
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> };
>
> +static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xD9),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1F),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1F),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7F),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4C),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xBE),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_LANE_MODE_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x17),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0C),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0C),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0E),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1C),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0x8E),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0F),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xCE),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xCE),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1A),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0F),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9A),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xE2),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1B),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1B),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9B),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2A),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5F),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xE3),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x9B),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x9B),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5F),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xFB),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1F),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xFA),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0F),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0E),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8750_ufsphy_g5_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x41),
> +};
> +
> struct qmp_ufs_offsets {
> u16 serdes;
> u16 pcs;
> @@ -1523,6 +1650,45 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
> .regs = ufsphy_v6_regs_layout,
> };
>
> +static const struct qmp_phy_cfg sm8750_ufsphy_cfg = {
> + .lanes = 2,
> +
> + .offsets = &qmp_ufs_offsets_v6,
> + .max_supported_gear = UFS_HS_G5,
> +
> + .tbls = {
> + .serdes = sm8750_ufsphy_serdes,
> + .serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes),
> + .tx = sm8750_ufsphy_tx,
> + .tx_num = ARRAY_SIZE(sm8750_ufsphy_tx),
> + .rx = sm8750_ufsphy_rx,
> + .rx_num = ARRAY_SIZE(sm8750_ufsphy_rx),
> + .pcs = sm8750_ufsphy_pcs,
> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs),
> + },
> +
> + .tbls_hs_b = {
> + .pcs = sm8750_ufsphy_hs_b_pcs,
> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs),
> + },
> +
> + .tbls_hs_overlay[0] = {
> + .pcs = sm8750_ufsphy_g4_pcs,
> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs),
> + .max_gear = UFS_HS_G4,
> + },
> + .tbls_hs_overlay[1] = {
> + .pcs = sm8750_ufsphy_g5_pcs,
> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g5_pcs),
> + .max_gear = UFS_HS_G5,
> + },
> +
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = ufsphy_v6_regs_layout,
> +
> +};
> +
> static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
> {
> void __iomem *serdes = qmp->serdes;
> @@ -1593,8 +1759,10 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg
> qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
> }
>
> - if (qmp->mode == PHY_MODE_UFS_HS_B)
> + if (qmp->mode == PHY_MODE_UFS_HS_B) {
> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
> + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_b);
> + }
> }
>
> static int qmp_ufs_com_init(struct qmp_ufs *qmp)
> @@ -2061,7 +2229,11 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
> }, {
> .compatible = "qcom,sm8650-qmp-ufs-phy",
> .data = &sm8650_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8750-qmp-ufs-phy",
> + .data = &sm8750_ufsphy_cfg,
> },
> +
> { },
> };
> MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);
>
Looks good
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 2/5] phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
2025-01-13 21:46 ` [PATCH 2/5] phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750 Melody Olvera
2025-01-14 9:00 ` neil.armstrong
@ 2025-01-14 10:49 ` Dmitry Baryshkov
[not found] ` <6873e397-dbc0-4c30-8c08-a65ee7cd6e01@quicinc.com>
2025-02-05 11:33 ` Nitin Rawat
1 sibling, 2 replies; 37+ messages in thread
From: Dmitry Baryshkov @ 2025-01-14 10:49 UTC (permalink / raw)
To: Melody Olvera
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Nitin Rawat, Manish Pandey
On Mon, Jan 13, 2025 at 01:46:25PM -0800, Melody Olvera wrote:
> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>
> Add SM8750 specific register layout and table configs. The serdes
> TX RX register offset has changed for SM8750 and hence keep UFS
> specific serdes offsets in a dedicated header file.
>
> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 12 ++
> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h | 68 ++++++++
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 174 ++++++++++++++++++++-
> 3 files changed, 253 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> index 328c6c0b0b09ae4ff5bf14e846772e6d0f31ce5a..aa2278f9377408b3c602f6fa0de5021804f21f52 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> @@ -86,4 +86,16 @@
> #define QSERDES_V6_COM_CMN_STATUS 0x1d0
> #define QSERDES_V6_COM_C_READY_STATUS 0x1f8
>
> +#define QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG 0x268
> +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0 0x26c
> +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x270
> +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x274
> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58
> +
> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c
> +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1 0x278
> +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x27c
> +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x280
> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54
> #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..73b3857e0277ce6cdbe658066772172a94f25d6e
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
> @@ -0,0 +1,68 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2024, Linaro Limited
> + */
> +
> +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
> +#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
> +
> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_TX 0x28
> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_RX 0x2c
> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX 0x30
> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX 0x34
> +#define QSERDES_UFS_V7_TX_LANE_MODE_1 0x7c
> +#define QSERDES_UFS_V7_TX_FR_DCC_CTRL 0x108
> +
> +#define QSERDES_UFS_V7_RX_UCDR_SO_SATURATION 0x28
> +#define QSERDES_UFS_V7_RX_UCDR_PI_CTRL1 0x58
> +#define QSERDES_UFS_V7_RX_TERM_BW_CTRL0 0xC4
> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0 0x218
> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1 0x21C
> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2 0x220
> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3 0x224
> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4 0x228
> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6 0x230
> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7 0x234
> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B3 0x248
> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B6 0x254
> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B7 0x258
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B0 0x260
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B1 0x264
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B2 0x268
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B3 0x26C
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B4 0x270
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B5 0x274
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B7 0x27C
> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B8 0x280
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0 0x284
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1 0x288
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2 0x28C
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3 0x290
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4 0x294
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5 0x298
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6 0x29C
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7 0x2A0
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0 0x2A8
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1 0x2AC
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2 0x2B0
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3 0x2B4
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4 0x2B8
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5 0x2BC
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6 0x2C0
> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7 0x2C4
> +#define QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL 0x348
> +#define QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM 0x380
> +#define QSERDES_UFS_V7_RX_INTERFACE_MODE 0x1F0
> +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2 0xD4
> +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4 0xDC
> +#define QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4 0xF0
> +#define QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS 0xF4
> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> +#define QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1CC
> +#define QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3 0x1D4
> +#define QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4 0x1B4
> +#define QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL 0x178
- Lowercase hex
- Sort RX by the register offset
> +
> +#endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index d964bdfe870029226482f264c78a27d0ec43bf2b..a1695b368fe7622bf8663343d0241b4d0d40ab59 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -31,6 +31,7 @@
> #include "phy-qcom-qmp-pcs-ufs-v6.h"
>
> #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
> +#include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h"
>
> /* QPHY_PCS_READY_STATUS bit */
> #define PCS_READY BIT(0)
> @@ -949,6 +950,132 @@ static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = {
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> };
>
> +static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xD9),
Lowercase hex
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1F),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1F),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7F),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4C),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xBE),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_LANE_MODE_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x17),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0C),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0C),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0E),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1C),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0x8E),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0F),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xCE),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xCE),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1A),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0F),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9A),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xE2),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1B),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1B),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9B),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2A),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5F),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xE3),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x9B),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x9B),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0x60),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5F),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xFB),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1F),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xFA),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40),
Why does SM8650 have 0xc1 here?
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0F),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0E),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = {
Missing QPHY_V6_PCS_UFS_PLL_CNTL, then it becomes sm8650_ufsphy_g4_pcs
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8750_ufsphy_g5_pcs[] = {
sm8650_ufsphy_g5_pcs?
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x41),
> +};
> +
> struct qmp_ufs_offsets {
> u16 serdes;
> u16 pcs;
> @@ -1523,6 +1650,45 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
> .regs = ufsphy_v6_regs_layout,
> };
>
> +static const struct qmp_phy_cfg sm8750_ufsphy_cfg = {
> + .lanes = 2,
> +
> + .offsets = &qmp_ufs_offsets_v6,
> + .max_supported_gear = UFS_HS_G5,
> +
> + .tbls = {
> + .serdes = sm8750_ufsphy_serdes,
> + .serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes),
> + .tx = sm8750_ufsphy_tx,
> + .tx_num = ARRAY_SIZE(sm8750_ufsphy_tx),
> + .rx = sm8750_ufsphy_rx,
> + .rx_num = ARRAY_SIZE(sm8750_ufsphy_rx),
> + .pcs = sm8750_ufsphy_pcs,
> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs),
> + },
> +
> + .tbls_hs_b = {
> + .pcs = sm8750_ufsphy_hs_b_pcs,
> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs),
> + },
> +
> + .tbls_hs_overlay[0] = {
> + .pcs = sm8750_ufsphy_g4_pcs,
> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs),
> + .max_gear = UFS_HS_G4,
> + },
> + .tbls_hs_overlay[1] = {
> + .pcs = sm8750_ufsphy_g5_pcs,
> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g5_pcs),
> + .max_gear = UFS_HS_G5,
> + },
> +
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = ufsphy_v6_regs_layout,
> +
> +};
> +
> static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
> {
> void __iomem *serdes = qmp->serdes;
> @@ -1593,8 +1759,10 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg
> qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
> }
>
> - if (qmp->mode == PHY_MODE_UFS_HS_B)
> + if (qmp->mode == PHY_MODE_UFS_HS_B) {
> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
> + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_b);
Extract the serdes+lanes+pcs helper, use it in this function.
> + }
> }
>
> static int qmp_ufs_com_init(struct qmp_ufs *qmp)
> @@ -2061,7 +2229,11 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
> }, {
> .compatible = "qcom,sm8650-qmp-ufs-phy",
> .data = &sm8650_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8750-qmp-ufs-phy",
> + .data = &sm8750_ufsphy_cfg,
> },
> +
> { },
> };
> MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);
>
> --
> 2.46.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
2025-01-13 21:46 ` [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC Melody Olvera
@ 2025-01-14 10:52 ` Dmitry Baryshkov
2025-02-08 19:17 ` Nitin Rawat
2025-01-18 15:28 ` Krzysztof Kozlowski
` (2 subsequent siblings)
3 siblings, 1 reply; 37+ messages in thread
From: Dmitry Baryshkov @ 2025-01-14 10:52 UTC (permalink / raw)
To: Melody Olvera
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Nitin Rawat, Manish Pandey
On Mon, Jan 13, 2025 at 01:46:27PM -0800, Melody Olvera wrote:
> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>
> Add UFS host controller and PHY nodes for SM8750 SoC.
>
> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 81 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 81 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..20690c102244b337847a6482dd83c37e19746de9 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -13,6 +13,7 @@
> #include <dt-bindings/power/qcom,rpmhpd.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/gpio/gpio.h>
>
> / {
> interrupt-parent = <&intc>;
> @@ -1939,6 +1940,86 @@ mmss_noc: interconnect@1780000 {
> #interconnect-cells = <2>;
> };
>
> + ufs_mem_phy: phy@1d80000 {
> + compatible = "qcom,sm8750-qmp-ufs-phy";
> + reg = <0x0 0x01d80000 0x0 0x2000>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> + <&tcsrcc TCSR_UFS_CLKREF_EN>;
> + clock-names = "ref",
> + "ref_aux",
> + "qref";
> +
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> +
> + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + ufs_mem_hc: ufs@1d84000 {
> + compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
> + reg = <0x0 0x01d84000 0x0 0x3000>;
> +
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_UFS_PHY_AHB_CLK>,
> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> + <&rpmhcc RPMH_LN_BB_CLK3>,
> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> + clock-names = "core_clk",
> + "bus_aggr_clk",
> + "iface_clk",
> + "core_clk_unipro",
> + "ref_clk",
> + "tx_lane0_sync_clk",
> + "rx_lane0_sync_clk",
> + "rx_lane1_sync_clk";
> + freq-table-hz = <100000000 403000000>,
> + <0 0>,
> + <0 0>,
> + <100000000 403000000>,
> + <100000000 403000000>,
> + <0 0>,
> + <0 0>,
> + <0 0>;
Use OPP table instead
> +
> + resets = <&gcc GCC_UFS_PHY_BCR>;
> + reset-names = "rst";
> +
> +
> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
Shouldn't cpu-ufs be ACTIVE_ONLY?
> + interconnect-names = "ufs-ddr",
> + "cpu-ufs";
> +
> + power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> + required-opps = <&rpmhpd_opp_nom>;
> +
> + iommus = <&apps_smmu 0x60 0>;
> + dma-coherent;
> +
> + lanes-per-direction = <2>;
> +
> + phys = <&ufs_mem_phy>;
> + phy-names = "ufsphy";
> +
> + #reset-cells = <1>;
> +
> + status = "disabled";
> + };
> +
> tcsr_mutex: hwlock@1f40000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0x0 0x01f40000 0x0 0x20000>;
>
> --
> 2.46.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY
2025-01-13 21:46 ` [PATCH 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY Melody Olvera
@ 2025-01-18 14:44 ` Krzysztof Kozlowski
0 siblings, 0 replies; 37+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-18 14:44 UTC (permalink / raw)
To: Melody Olvera
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Nitin Rawat
On Mon, Jan 13, 2025 at 01:46:24PM -0800, Melody Olvera wrote:
> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>
> Document the QMP UFS PHY on the SM8750 Platform.
Pretty obvious commit msg, duplicating subject. Say something useful,
e.g. why this is not compatible with sm8650.
>
> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 3/5] dt-bindings: ufs: qcom: Document the SM8750 UFS Controller
2025-01-13 21:46 ` [PATCH 3/5] dt-bindings: ufs: qcom: Document the SM8750 UFS Controller Melody Olvera
@ 2025-01-18 14:45 ` Krzysztof Kozlowski
0 siblings, 0 replies; 37+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-18 14:45 UTC (permalink / raw)
To: Melody Olvera
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Nitin Rawat
On Mon, Jan 13, 2025 at 01:46:26PM -0800, Melody Olvera wrote:
> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>
> Document the UFS Controller on the SM8750 Platform.
>
> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 5/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards
2025-01-13 21:46 ` [PATCH 5/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards Melody Olvera
@ 2025-01-18 15:26 ` Krzysztof Kozlowski
2025-01-27 10:20 ` Konrad Dybcio
1 sibling, 0 replies; 37+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-18 15:26 UTC (permalink / raw)
To: Melody Olvera
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Nitin Rawat, Manish Pandey
On Mon, Jan 13, 2025 at 01:46:28PM -0800, Melody Olvera wrote:
> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>
> Add UFS host controller and PHY nodes for SM8750 QRD and MTP boards.
>
> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 18 ++++++++++++++++++
> arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 18 ++++++++++++++++++
> 2 files changed, 36 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
2025-01-13 21:46 ` [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC Melody Olvera
2025-01-14 10:52 ` Dmitry Baryshkov
@ 2025-01-18 15:28 ` Krzysztof Kozlowski
2025-01-27 10:23 ` Konrad Dybcio
2025-02-08 1:43 ` Konrad Dybcio
3 siblings, 0 replies; 37+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-18 15:28 UTC (permalink / raw)
To: Melody Olvera
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Nitin Rawat, Manish Pandey
On Mon, Jan 13, 2025 at 01:46:27PM -0800, Melody Olvera wrote:
> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>
> Add UFS host controller and PHY nodes for SM8750 SoC.
>
> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 81 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 81 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..20690c102244b337847a6482dd83c37e19746de9 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -13,6 +13,7 @@
> #include <dt-bindings/power/qcom,rpmhpd.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/gpio/gpio.h>
>
> / {
> interrupt-parent = <&intc>;
> @@ -1939,6 +1940,86 @@ mmss_noc: interconnect@1780000 {
> #interconnect-cells = <2>;
> };
>
> + ufs_mem_phy: phy@1d80000 {
> + compatible = "qcom,sm8750-qmp-ufs-phy";
> + reg = <0x0 0x01d80000 0x0 0x2000>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> + <&tcsrcc TCSR_UFS_CLKREF_EN>;
> + clock-names = "ref",
Since there is going to be resend, let's save me one commit afterwards:
Incorrect space after '='. There is always only one before and one
after.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 5/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards
2025-01-13 21:46 ` [PATCH 5/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards Melody Olvera
2025-01-18 15:26 ` Krzysztof Kozlowski
@ 2025-01-27 10:20 ` Konrad Dybcio
1 sibling, 0 replies; 37+ messages in thread
From: Konrad Dybcio @ 2025-01-27 10:20 UTC (permalink / raw)
To: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
Nitin Rawat, Manish Pandey
On 13.01.2025 10:46 PM, Melody Olvera wrote:
> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>
> Add UFS host controller and PHY nodes for SM8750 QRD and MTP boards.
>
> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
2025-01-13 21:46 ` [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC Melody Olvera
2025-01-14 10:52 ` Dmitry Baryshkov
2025-01-18 15:28 ` Krzysztof Kozlowski
@ 2025-01-27 10:23 ` Konrad Dybcio
2025-02-08 1:43 ` Konrad Dybcio
3 siblings, 0 replies; 37+ messages in thread
From: Konrad Dybcio @ 2025-01-27 10:23 UTC (permalink / raw)
To: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
Nitin Rawat, Manish Pandey
On 13.01.2025 10:46 PM, Melody Olvera wrote:
> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>
> Add UFS host controller and PHY nodes for SM8750 SoC.
>
> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
I don't see anything wrong per se here, just some style nits
atop the other replies:
[...]
> + ufs_mem_hc: ufs@1d84000 {
> + compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1 compatible per lines, please
> + reg = <0x0 0x01d84000 0x0 0x3000>;
> +
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_UFS_PHY_AHB_CLK>,
> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> + <&rpmhcc RPMH_LN_BB_CLK3>,
> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> + clock-names = "core_clk",
> + "bus_aggr_clk",
> + "iface_clk",
> + "core_clk_unipro",
> + "ref_clk",
> + "tx_lane0_sync_clk",
> + "rx_lane0_sync_clk",
> + "rx_lane1_sync_clk";
> + freq-table-hz = <100000000 403000000>,
> + <0 0>,
> + <0 0>,
> + <100000000 403000000>,
> + <100000000 403000000>,
> + <0 0>,
> + <0 0>,
> + <0 0>;
> +
> + resets = <&gcc GCC_UFS_PHY_BCR>;
> + reset-names = "rst";
> +
> +
> +
stray double \n
Konrad
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 2/5] phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
[not found] ` <6873e397-dbc0-4c30-8c08-a65ee7cd6e01@quicinc.com>
@ 2025-02-04 1:36 ` Dmitry Baryshkov
2025-02-05 11:41 ` Nitin Rawat
0 siblings, 1 reply; 37+ messages in thread
From: Dmitry Baryshkov @ 2025-02-04 1:36 UTC (permalink / raw)
To: Nitin Rawat
Cc: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Manish Pandey
Hello,
On Mon, 3 Feb 2025 at 10:03, Nitin Rawat <quic_nitirawa@quicinc.com> wrote:
Your email client has corrupted all quotation levels. Please fix its
configuration so that you can not compose HTML email. Or switch to a
normal text-based email client like Mutt or Gnus.
No additional comments can be provided to this email.
>
>
> On 1/14/2025 4:19 PM, Dmitry Baryshkov wrote:
>
> On Mon, Jan 13, 2025 at 01:46:25PM -0800, Melody Olvera wrote:
>
> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>
> Add SM8750 specific register layout and table configs. The serdes
> TX RX register offset has changed for SM8750 and hence keep UFS
> specific serdes offsets in a dedicated header file.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 2/5] phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
2025-01-14 10:49 ` Dmitry Baryshkov
[not found] ` <6873e397-dbc0-4c30-8c08-a65ee7cd6e01@quicinc.com>
@ 2025-02-05 11:33 ` Nitin Rawat
2025-02-05 11:44 ` Dmitry Baryshkov
1 sibling, 1 reply; 37+ messages in thread
From: Nitin Rawat @ 2025-02-05 11:33 UTC (permalink / raw)
To: Dmitry Baryshkov, Melody Olvera
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Manish Pandey
On 1/14/2025 4:19 PM, Dmitry Baryshkov wrote:
> On Mon, Jan 13, 2025 at 01:46:25PM -0800, Melody Olvera wrote:
>> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>>
>> Add SM8750 specific register layout and table configs. The serdes
>> TX RX register offset has changed for SM8750 and hence keep UFS
>> specific serdes offsets in a dedicated header file.
>>
>> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
>> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 12 ++
>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h | 68 ++++++++
>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 174 ++++++++++++++++++++-
>> 3 files changed, 253 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>> index 328c6c0b0b09ae4ff5bf14e846772e6d0f31ce5a..aa2278f9377408b3c602f6fa0de5021804f21f52 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>> @@ -86,4 +86,16 @@
>> #define QSERDES_V6_COM_CMN_STATUS 0x1d0
>> #define QSERDES_V6_COM_C_READY_STATUS 0x1f8
>>
>> +#define QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG 0x268
>> +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0 0x26c
>> +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x270
>> +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x274
>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58
>> +
>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c
>> +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1 0x278
>> +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x27c
>> +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x280
>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54
>> #endif
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..73b3857e0277ce6cdbe658066772172a94f25d6e
>> --- /dev/null
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
>> @@ -0,0 +1,68 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (c) 2024, Linaro Limited
>> + */
>> +
>> +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
>> +#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
>> +
>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_TX 0x28
>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_RX 0x2c
>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX 0x30
>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX 0x34
>> +#define QSERDES_UFS_V7_TX_LANE_MODE_1 0x7c
>> +#define QSERDES_UFS_V7_TX_FR_DCC_CTRL 0x108
>> +
>> +#define QSERDES_UFS_V7_RX_UCDR_SO_SATURATION 0x28
>> +#define QSERDES_UFS_V7_RX_UCDR_PI_CTRL1 0x58
>> +#define QSERDES_UFS_V7_RX_TERM_BW_CTRL0 0xC4
>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0 0x218
>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1 0x21C
>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2 0x220
>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3 0x224
>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4 0x228
>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6 0x230
>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7 0x234
>> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B3 0x248
>> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B6 0x254
>> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B7 0x258
>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B0 0x260
>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B1 0x264
>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B2 0x268
>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B3 0x26C
>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B4 0x270
>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B5 0x274
>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B7 0x27C
>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B8 0x280
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0 0x284
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1 0x288
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2 0x28C
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3 0x290
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4 0x294
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5 0x298
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6 0x29C
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7 0x2A0
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0 0x2A8
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1 0x2AC
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2 0x2B0
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3 0x2B4
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4 0x2B8
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5 0x2BC
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6 0x2C0
>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7 0x2C4
>> +#define QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL 0x348
>> +#define QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM 0x380
>> +#define QSERDES_UFS_V7_RX_INTERFACE_MODE 0x1F0
>> +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2 0xD4
>> +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4 0xDC
>> +#define QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4 0xF0
>> +#define QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS 0xF4
>> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
>> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
>> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
>> +#define QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1CC
>> +#define QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3 0x1D4
>> +#define QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4 0x1B4
>> +#define QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL 0x178
>
> - Lowercase hex
> - Sort RX by the register offset
Sure Will take care in next patchset.
>
>
>> +
>> +#endif
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> index d964bdfe870029226482f264c78a27d0ec43bf2b..a1695b368fe7622bf8663343d0241b4d0d40ab59 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> @@ -31,6 +31,7 @@
>> #include "phy-qcom-qmp-pcs-ufs-v6.h"
>>
>> #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
>> +#include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h"
>>
>> /* QPHY_PCS_READY_STATUS bit */
>> #define PCS_READY BIT(0)
>> @@ -949,6 +950,132 @@ static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = {
>> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
>> };
>>
>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = {
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xD9),
>
> Lowercase hex
Sure Will take care in next patchset.
>
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x60),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1F),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1F),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x07),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x20),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x40),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7F),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4C),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xBE),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = {
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_LANE_MODE_1, 0x00),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x17),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = {
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0C),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0C),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0E),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1C),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0x8E),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0F),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xCE),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xCE),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1A),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0F),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9A),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xE2),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1B),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1B),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9B),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2A),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5F),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xE3),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x9B),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x9B),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0x60),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5F),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xFB),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1F),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xFA),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = {
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40),
>
> Why does SM8650 have 0xc1 here?
SM8750 phy is different from SM8650 and hence it is using different phy
calibration setting. This value is as per Hardware programming guide.
>
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0F),
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0E),
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12),
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15),
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = {
>
> Missing QPHY_V6_PCS_UFS_PLL_CNTL, then it becomes sm8650_ufsphy_g4_pcs
The value of QPHY_V6_PCS_UFS_PLL_CNTL is 0x33 for SM8750 as it is
operating on 80bit mode. Similiar change needs to be done for SM8650.
>
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_g5_pcs[] = {
>
> sm8650_ufsphy_g5_pcs?
Agree with you. Good Finding. I will replace sm8750_ufsphy_g5_pcs with
sm8650_ufsphy_g5_pcs.
>
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05),
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05),
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d),
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = {
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x41),
>> +};
>> +
>> struct qmp_ufs_offsets {
>> u16 serdes;
>> u16 pcs;
>> @@ -1523,6 +1650,45 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
>> .regs = ufsphy_v6_regs_layout,
>> };
>>
>> +static const struct qmp_phy_cfg sm8750_ufsphy_cfg = {
>> + .lanes = 2,
>> +
>> + .offsets = &qmp_ufs_offsets_v6,
>> + .max_supported_gear = UFS_HS_G5,
>> +
>> + .tbls = {
>> + .serdes = sm8750_ufsphy_serdes,
>> + .serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes),
>> + .tx = sm8750_ufsphy_tx,
>> + .tx_num = ARRAY_SIZE(sm8750_ufsphy_tx),
>> + .rx = sm8750_ufsphy_rx,
>> + .rx_num = ARRAY_SIZE(sm8750_ufsphy_rx),
>> + .pcs = sm8750_ufsphy_pcs,
>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs),
>> + },
>> +
>> + .tbls_hs_b = {
>> + .pcs = sm8750_ufsphy_hs_b_pcs,
>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs),
>> + },
>> +
>> + .tbls_hs_overlay[0] = {
>> + .pcs = sm8750_ufsphy_g4_pcs,
>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs),
>> + .max_gear = UFS_HS_G4,
>> + },
>> + .tbls_hs_overlay[1] = {
>> + .pcs = sm8750_ufsphy_g5_pcs,
>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g5_pcs),
>> + .max_gear = UFS_HS_G5,
>> + },
>> +
>> + .vreg_list = qmp_phy_vreg_l,
>> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
>> + .regs = ufsphy_v6_regs_layout,
>> +
>> +};
>> +
>> static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
>> {
>> void __iomem *serdes = qmp->serdes;
>> @@ -1593,8 +1759,10 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg
>> qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
>> }
>>
>> - if (qmp->mode == PHY_MODE_UFS_HS_B)
>> + if (qmp->mode == PHY_MODE_UFS_HS_B) {
>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
>> + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_b);
>
> Extract the serdes+lanes+pcs helper, use it in this function.
Lane init is already a different helper and is already being called from
function (qmp_ufs_init_register). Here we just adding few extra PCS
registers needed to support Rate B.
>
>> + }
>> }
>>
>> static int qmp_ufs_com_init(struct qmp_ufs *qmp)
>> @@ -2061,7 +2229,11 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
>> }, {
>> .compatible = "qcom,sm8650-qmp-ufs-phy",
>> .data = &sm8650_ufsphy_cfg,
>> + }, {
>> + .compatible = "qcom,sm8750-qmp-ufs-phy",
>> + .data = &sm8750_ufsphy_cfg,
>> },
>> +
>> { },
>> };
>> MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);
>>
>> --
>> 2.46.1
>>
>
Thanks,
Nitin
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 2/5] phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
2025-02-04 1:36 ` Dmitry Baryshkov
@ 2025-02-05 11:41 ` Nitin Rawat
0 siblings, 0 replies; 37+ messages in thread
From: Nitin Rawat @ 2025-02-05 11:41 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Manish Pandey
On 2/4/2025 7:06 AM, Dmitry Baryshkov wrote:
> Hello,
>
> On Mon, 3 Feb 2025 at 10:03, Nitin Rawat <quic_nitirawa@quicinc.com> wrote:
>
> Your email client has corrupted all quotation levels. Please fix its
> configuration so that you can not compose HTML email. Or switch to a
> normal text-based email client like Mutt or Gnus.
>
> No additional comments can be provided to this email.
>
>>
Hi Dmitry,
Sorry for the inconvenience. After software update seems there was some
issue with email client configuration . I have updated the configuration
and resent my reply.
Regards,
Nitin
>>
>> On 1/14/2025 4:19 PM, Dmitry Baryshkov wrote:
>>
>> On Mon, Jan 13, 2025 at 01:46:25PM -0800, Melody Olvera wrote:
>>
>> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>>
>> Add SM8750 specific register layout and table configs. The serdes
>> TX RX register offset has changed for SM8750 and hence keep UFS
>> specific serdes offsets in a dedicated header file.
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 2/5] phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
2025-02-05 11:33 ` Nitin Rawat
@ 2025-02-05 11:44 ` Dmitry Baryshkov
2025-02-05 13:57 ` Nitin Rawat
0 siblings, 1 reply; 37+ messages in thread
From: Dmitry Baryshkov @ 2025-02-05 11:44 UTC (permalink / raw)
To: Nitin Rawat
Cc: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Manish Pandey
On Wed, 5 Feb 2025 at 13:34, Nitin Rawat <quic_nitirawa@quicinc.com> wrote:
>
>
>
> On 1/14/2025 4:19 PM, Dmitry Baryshkov wrote:
> > On Mon, Jan 13, 2025 at 01:46:25PM -0800, Melody Olvera wrote:
> >> From: Nitin Rawat <quic_nitirawa@quicinc.com>
> >>
> >> Add SM8750 specific register layout and table configs. The serdes
> >> TX RX register offset has changed for SM8750 and hence keep UFS
> >> specific serdes offsets in a dedicated header file.
> >>
> >> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> >> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> >> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> >> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> >> ---
> >> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 12 ++
> >> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h | 68 ++++++++
> >> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 174 ++++++++++++++++++++-
> >> 3 files changed, 253 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> >> index 328c6c0b0b09ae4ff5bf14e846772e6d0f31ce5a..aa2278f9377408b3c602f6fa0de5021804f21f52 100644
> >> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> >> @@ -86,4 +86,16 @@
> >> #define QSERDES_V6_COM_CMN_STATUS 0x1d0
> >> #define QSERDES_V6_COM_C_READY_STATUS 0x1f8
> >>
> >> +#define QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG 0x268
> >> +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0 0x26c
> >> +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x270
> >> +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x274
> >> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58
> >> +
> >> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c
> >> +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1 0x278
> >> +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x27c
> >> +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x280
> >> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
> >> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54
> >> #endif
> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
> >> new file mode 100644
> >> index 0000000000000000000000000000000000000000..73b3857e0277ce6cdbe658066772172a94f25d6e
> >> --- /dev/null
> >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
> >> @@ -0,0 +1,68 @@
> >> +/* SPDX-License-Identifier: GPL-2.0 */
> >> +/*
> >> + * Copyright (c) 2024, Linaro Limited
> >> + */
> >> +
> >> +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
> >> +#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
> >> +
> >> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_TX 0x28
> >> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_RX 0x2c
> >> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX 0x30
> >> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX 0x34
> >> +#define QSERDES_UFS_V7_TX_LANE_MODE_1 0x7c
> >> +#define QSERDES_UFS_V7_TX_FR_DCC_CTRL 0x108
> >> +
> >> +#define QSERDES_UFS_V7_RX_UCDR_SO_SATURATION 0x28
> >> +#define QSERDES_UFS_V7_RX_UCDR_PI_CTRL1 0x58
> >> +#define QSERDES_UFS_V7_RX_TERM_BW_CTRL0 0xC4
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0 0x218
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1 0x21C
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2 0x220
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3 0x224
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4 0x228
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6 0x230
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7 0x234
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B3 0x248
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B6 0x254
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B7 0x258
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B0 0x260
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B1 0x264
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B2 0x268
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B3 0x26C
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B4 0x270
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B5 0x274
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B7 0x27C
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B8 0x280
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0 0x284
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1 0x288
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2 0x28C
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3 0x290
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4 0x294
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5 0x298
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6 0x29C
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7 0x2A0
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0 0x2A8
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1 0x2AC
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2 0x2B0
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3 0x2B4
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4 0x2B8
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5 0x2BC
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6 0x2C0
> >> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7 0x2C4
> >> +#define QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL 0x348
> >> +#define QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM 0x380
> >> +#define QSERDES_UFS_V7_RX_INTERFACE_MODE 0x1F0
> >> +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2 0xD4
> >> +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4 0xDC
> >> +#define QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4 0xF0
> >> +#define QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS 0xF4
> >> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> >> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> >> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> >> +#define QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1CC
> >> +#define QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3 0x1D4
> >> +#define QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4 0x1B4
> >> +#define QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL 0x178
> >
> > - Lowercase hex
> > - Sort RX by the register offset
>
> Sure Will take care in next patchset.
Just to note, please sort QSERDES_V6_COM regs too.
>
> >
> >
> >> +
> >> +#endif
> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >> index d964bdfe870029226482f264c78a27d0ec43bf2b..a1695b368fe7622bf8663343d0241b4d0d40ab59 100644
> >> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >> @@ -31,6 +31,7 @@
> >> #include "phy-qcom-qmp-pcs-ufs-v6.h"
> >>
> >> #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
> >> +#include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h"
> >>
> >> /* QPHY_PCS_READY_STATUS bit */
> >> #define PCS_READY BIT(0)
> >> @@ -949,6 +950,132 @@ static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = {
> >> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> >> };
> >>
> >> +static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = {
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xD9),
> >
> > Lowercase hex
>
> Sure Will take care in next patchset.
> >
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x60),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1F),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1F),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x07),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x20),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x40),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG, 0x06),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7F),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4C),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xBE),
> >> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
> >> +};
> >> +
> >> +static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = {
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_LANE_MODE_1, 0x00),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x17),
> >> +};
> >> +
> >> +static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = {
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0C),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0C),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0E),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1C),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0x8E),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0F),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xCE),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xCE),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1A),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0F),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9A),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xE2),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1B),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1B),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9B),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2A),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5F),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xE3),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x9B),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x9B),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0x60),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5F),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xFB),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1F),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xFA),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30),
> >> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77),
> >> +};
> >> +
> >> +static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = {
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40),
> >
> > Why does SM8650 have 0xc1 here?
>
> SM8750 phy is different from SM8650 and hence it is using different phy
> calibration setting. This value is as per Hardware programming guide.'
Ack.
>
> >
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0F),
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0E),
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12),
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15),
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19),
> >> +};
> >> +
> >> +static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = {
> >
> > Missing QPHY_V6_PCS_UFS_PLL_CNTL, then it becomes sm8650_ufsphy_g4_pcs
>
> The value of QPHY_V6_PCS_UFS_PLL_CNTL is 0x33 for SM8750 as it is
> operating on 80bit mode. Similiar change needs to be done for SM8650.
Ack, please check if that allows the driver to use the same set of
tables for SM8650 and SM8750.
> >
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> >> +};
> >> +
> >> +static const struct qmp_phy_init_tbl sm8750_ufsphy_g5_pcs[] = {
> >
> > sm8650_ufsphy_g5_pcs?
> Agree with you. Good Finding. I will replace sm8750_ufsphy_g5_pcs with
> sm8650_ufsphy_g5_pcs.
>
>
> >
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05),
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05),
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d),
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> >> +};
> >> +
> >> +static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = {
> >> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x41),
> >> +};
> >> +
> >> struct qmp_ufs_offsets {
> >> u16 serdes;
> >> u16 pcs;
> >> @@ -1523,6 +1650,45 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
> >> .regs = ufsphy_v6_regs_layout,
> >> };
> >>
> >> +static const struct qmp_phy_cfg sm8750_ufsphy_cfg = {
> >> + .lanes = 2,
> >> +
> >> + .offsets = &qmp_ufs_offsets_v6,
> >> + .max_supported_gear = UFS_HS_G5,
> >> +
> >> + .tbls = {
> >> + .serdes = sm8750_ufsphy_serdes,
> >> + .serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes),
> >> + .tx = sm8750_ufsphy_tx,
> >> + .tx_num = ARRAY_SIZE(sm8750_ufsphy_tx),
> >> + .rx = sm8750_ufsphy_rx,
> >> + .rx_num = ARRAY_SIZE(sm8750_ufsphy_rx),
> >> + .pcs = sm8750_ufsphy_pcs,
> >> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs),
> >> + },
> >> +
> >> + .tbls_hs_b = {
> >> + .pcs = sm8750_ufsphy_hs_b_pcs,
> >> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs),
> >> + },
> >> +
> >> + .tbls_hs_overlay[0] = {
> >> + .pcs = sm8750_ufsphy_g4_pcs,
> >> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs),
> >> + .max_gear = UFS_HS_G4,
> >> + },
> >> + .tbls_hs_overlay[1] = {
> >> + .pcs = sm8750_ufsphy_g5_pcs,
> >> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g5_pcs),
> >> + .max_gear = UFS_HS_G5,
> >> + },
> >> +
> >> + .vreg_list = qmp_phy_vreg_l,
> >> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> >> + .regs = ufsphy_v6_regs_layout,
> >> +
> >> +};
> >> +
> >> static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
> >> {
> >> void __iomem *serdes = qmp->serdes;
> >> @@ -1593,8 +1759,10 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg
> >> qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
> >> }
> >>
> >> - if (qmp->mode == PHY_MODE_UFS_HS_B)
> >> + if (qmp->mode == PHY_MODE_UFS_HS_B) {
> >> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
> >> + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_b);
> >
> > Extract the serdes+lanes+pcs helper, use it in this function.
>
> Lane init is already a different helper and is already being called from
> function (qmp_ufs_init_register). Here we just adding few extra PCS
> registers needed to support Rate B.
Please extract the helper that calls qmp_ufs_serdes_init() +
qmp_ufs_lanes_init() + qmp_ufs_pcs_init() over a particular table.
>
> >
> >> + }
> >> }
> >>
> >> static int qmp_ufs_com_init(struct qmp_ufs *qmp)
> >> @@ -2061,7 +2229,11 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
> >> }, {
> >> .compatible = "qcom,sm8650-qmp-ufs-phy",
> >> .data = &sm8650_ufsphy_cfg,
> >> + }, {
> >> + .compatible = "qcom,sm8750-qmp-ufs-phy",
> >> + .data = &sm8750_ufsphy_cfg,
> >> },
> >> +
> >> { },
> >> };
> >> MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);
> >>
> >> --
> >> 2.46.1
> >>
> >
> Thanks,
> Nitin
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 2/5] phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
2025-02-05 11:44 ` Dmitry Baryshkov
@ 2025-02-05 13:57 ` Nitin Rawat
2025-02-05 14:28 ` Dmitry Baryshkov
0 siblings, 1 reply; 37+ messages in thread
From: Nitin Rawat @ 2025-02-05 13:57 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Manish Pandey
On 2/5/2025 5:14 PM, Dmitry Baryshkov wrote:
> On Wed, 5 Feb 2025 at 13:34, Nitin Rawat <quic_nitirawa@quicinc.com> wrote:
>>
>>
>>
>> On 1/14/2025 4:19 PM, Dmitry Baryshkov wrote:
>>> On Mon, Jan 13, 2025 at 01:46:25PM -0800, Melody Olvera wrote:
>>>> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>>>>
>>>> Add SM8750 specific register layout and table configs. The serdes
>>>> TX RX register offset has changed for SM8750 and hence keep UFS
>>>> specific serdes offsets in a dedicated header file.
>>>>
>>>> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
>>>> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
>>>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>> ---
>>>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 12 ++
>>>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h | 68 ++++++++
>>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 174 ++++++++++++++++++++-
>>>> 3 files changed, 253 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>> index 328c6c0b0b09ae4ff5bf14e846772e6d0f31ce5a..aa2278f9377408b3c602f6fa0de5021804f21f52 100644
>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>> @@ -86,4 +86,16 @@
>>>> #define QSERDES_V6_COM_CMN_STATUS 0x1d0
>>>> #define QSERDES_V6_COM_C_READY_STATUS 0x1f8
>>>>
>>>> +#define QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG 0x268
>>>> +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0 0x26c
>>>> +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x270
>>>> +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x274
>>>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58
>>>> +
>>>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c
>>>> +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1 0x278
>>>> +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x27c
>>>> +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x280
>>>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
>>>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54
>>>> #endif
>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
>>>> new file mode 100644
>>>> index 0000000000000000000000000000000000000000..73b3857e0277ce6cdbe658066772172a94f25d6e
>>>> --- /dev/null
>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
>>>> @@ -0,0 +1,68 @@
>>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>>> +/*
>>>> + * Copyright (c) 2024, Linaro Limited
>>>> + */
>>>> +
>>>> +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
>>>> +#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
>>>> +
>>>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_TX 0x28
>>>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_RX 0x2c
>>>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX 0x30
>>>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX 0x34
>>>> +#define QSERDES_UFS_V7_TX_LANE_MODE_1 0x7c
>>>> +#define QSERDES_UFS_V7_TX_FR_DCC_CTRL 0x108
>>>> +
>>>> +#define QSERDES_UFS_V7_RX_UCDR_SO_SATURATION 0x28
>>>> +#define QSERDES_UFS_V7_RX_UCDR_PI_CTRL1 0x58
>>>> +#define QSERDES_UFS_V7_RX_TERM_BW_CTRL0 0xC4
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0 0x218
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1 0x21C
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2 0x220
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3 0x224
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4 0x228
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6 0x230
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7 0x234
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B3 0x248
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B6 0x254
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B7 0x258
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B0 0x260
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B1 0x264
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B2 0x268
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B3 0x26C
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B4 0x270
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B5 0x274
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B7 0x27C
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B8 0x280
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0 0x284
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1 0x288
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2 0x28C
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3 0x290
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4 0x294
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5 0x298
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6 0x29C
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7 0x2A0
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0 0x2A8
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1 0x2AC
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2 0x2B0
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3 0x2B4
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4 0x2B8
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5 0x2BC
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6 0x2C0
>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7 0x2C4
>>>> +#define QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL 0x348
>>>> +#define QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM 0x380
>>>> +#define QSERDES_UFS_V7_RX_INTERFACE_MODE 0x1F0
>>>> +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2 0xD4
>>>> +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4 0xDC
>>>> +#define QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4 0xF0
>>>> +#define QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS 0xF4
>>>> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
>>>> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
>>>> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
>>>> +#define QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1CC
>>>> +#define QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3 0x1D4
>>>> +#define QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4 0x1B4
>>>> +#define QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL 0x178
>>>
>>> - Lowercase hex
>>> - Sort RX by the register offset
>>
>> Sure Will take care in next patchset.
>
> Just to note, please sort QSERDES_V6_COM regs too.
>
>>
>>>
>>>
>>>> +
>>>> +#endif
>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>> index d964bdfe870029226482f264c78a27d0ec43bf2b..a1695b368fe7622bf8663343d0241b4d0d40ab59 100644
>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>> @@ -31,6 +31,7 @@
>>>> #include "phy-qcom-qmp-pcs-ufs-v6.h"
>>>>
>>>> #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
>>>> +#include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h"
>>>>
>>>> /* QPHY_PCS_READY_STATUS bit */
>>>> #define PCS_READY BIT(0)
>>>> @@ -949,6 +950,132 @@ static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = {
>>>> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
>>>> };
>>>>
>>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = {
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xD9),
>>>
>>> Lowercase hex
>>
>> Sure Will take care in next patchset.
>>>
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x60),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1F),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1F),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x07),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x20),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x40),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG, 0x06),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7F),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4C),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xBE),
>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
>>>> +};
>>>> +
>>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = {
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_LANE_MODE_1, 0x00),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x17),
>>>> +};
>>>> +
>>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = {
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0C),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0C),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0E),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1C),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0x8E),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0F),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xCE),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xCE),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1A),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0F),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9A),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xE2),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1B),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1B),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9B),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2A),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5F),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xE3),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x9B),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x9B),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0x60),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5F),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xFB),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1F),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xFA),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30),
>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77),
>>>> +};
>>>> +
>>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = {
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40),
>>>
>>> Why does SM8650 have 0xc1 here?
>>
>> SM8750 phy is different from SM8650 and hence it is using different phy
>> calibration setting. This value is as per Hardware programming guide.'
>
> Ack.
>
>>
>>>
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0F),
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0E),
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12),
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15),
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19),
>>>> +};
>>>> +
>>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = {
>>>
>>> Missing QPHY_V6_PCS_UFS_PLL_CNTL, then it becomes sm8650_ufsphy_g4_pcs
>>
>> The value of QPHY_V6_PCS_UFS_PLL_CNTL is 0x33 for SM8750 as it is
>> operating on 80bit mode. Similiar change needs to be done for SM8650.
>
> Ack, please check if that allows the driver to use the same set of
> tables for SM8650 and SM8750.
>
>>>
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
>>>> +};
>>>> +
>>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_g5_pcs[] = {
>>>
>>> sm8650_ufsphy_g5_pcs?
>> Agree with you. Good Finding. I will replace sm8750_ufsphy_g5_pcs with
>> sm8650_ufsphy_g5_pcs.
>>
>>
>>>
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05),
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05),
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d),
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
>>>> +};
>>>> +
>>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = {
>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x41),
>>>> +};
>>>> +
>>>> struct qmp_ufs_offsets {
>>>> u16 serdes;
>>>> u16 pcs;
>>>> @@ -1523,6 +1650,45 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
>>>> .regs = ufsphy_v6_regs_layout,
>>>> };
>>>>
>>>> +static const struct qmp_phy_cfg sm8750_ufsphy_cfg = {
>>>> + .lanes = 2,
>>>> +
>>>> + .offsets = &qmp_ufs_offsets_v6,
>>>> + .max_supported_gear = UFS_HS_G5,
>>>> +
>>>> + .tbls = {
>>>> + .serdes = sm8750_ufsphy_serdes,
>>>> + .serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes),
>>>> + .tx = sm8750_ufsphy_tx,
>>>> + .tx_num = ARRAY_SIZE(sm8750_ufsphy_tx),
>>>> + .rx = sm8750_ufsphy_rx,
>>>> + .rx_num = ARRAY_SIZE(sm8750_ufsphy_rx),
>>>> + .pcs = sm8750_ufsphy_pcs,
>>>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs),
>>>> + },
>>>> +
>>>> + .tbls_hs_b = {
>>>> + .pcs = sm8750_ufsphy_hs_b_pcs,
>>>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs),
>>>> + },
>>>> +
>>>> + .tbls_hs_overlay[0] = {
>>>> + .pcs = sm8750_ufsphy_g4_pcs,
>>>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs),
>>>> + .max_gear = UFS_HS_G4,
>>>> + },
>>>> + .tbls_hs_overlay[1] = {
>>>> + .pcs = sm8750_ufsphy_g5_pcs,
>>>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g5_pcs),
>>>> + .max_gear = UFS_HS_G5,
>>>> + },
>>>> +
>>>> + .vreg_list = qmp_phy_vreg_l,
>>>> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
>>>> + .regs = ufsphy_v6_regs_layout,
>>>> +
>>>> +};
>>>> +
>>>> static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
>>>> {
>>>> void __iomem *serdes = qmp->serdes;
>>>> @@ -1593,8 +1759,10 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg
>>>> qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
>>>> }
>>>>
>>>> - if (qmp->mode == PHY_MODE_UFS_HS_B)
>>>> + if (qmp->mode == PHY_MODE_UFS_HS_B) {
>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
>>>> + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_b);
>>>
>>> Extract the serdes+lanes+pcs helper, use it in this function.
>>
>> Lane init is already a different helper and is already being called from
>> function (qmp_ufs_init_register). Here we just adding few extra PCS
>> registers needed to support Rate B.
>
> Please extract the helper that calls qmp_ufs_serdes_init() +
> qmp_ufs_lanes_init() + qmp_ufs_pcs_init() over a particular table.
Hi Dmitry,
Do you mean to move qmp_ufs_serdes_init , qmp_ufs_lanes_init and
qmp_ufs_pcs_init into a different wrapper function and call this wrapper
from qmp_ufs_init_registers for each table.
But for tbls_hs_b, we just need qmp_ufs_serdes_init and
qmp_ufs_pcs_init. qmp_ufs_lanes_init is not required for tbls_hs_b.
So wrapper API won't be of much help.
Regards,
Nitin
>
>>
>>>
>>>> + }
>>>> }
>>>>
>>>> static int qmp_ufs_com_init(struct qmp_ufs *qmp)
>>>> @@ -2061,7 +2229,11 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
>>>> }, {
>>>> .compatible = "qcom,sm8650-qmp-ufs-phy",
>>>> .data = &sm8650_ufsphy_cfg,
>>>> + }, {
>>>> + .compatible = "qcom,sm8750-qmp-ufs-phy",
>>>> + .data = &sm8750_ufsphy_cfg,
>>>> },
>>>> +
>>>> { },
>>>> };
>>>> MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);
>>>>
>>>> --
>>>> 2.46.1
>>>>
>>>
>> Thanks,
>> Nitin
>>
>
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 2/5] phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
2025-02-05 13:57 ` Nitin Rawat
@ 2025-02-05 14:28 ` Dmitry Baryshkov
2025-02-07 9:14 ` Nitin Rawat
0 siblings, 1 reply; 37+ messages in thread
From: Dmitry Baryshkov @ 2025-02-05 14:28 UTC (permalink / raw)
To: Nitin Rawat
Cc: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Manish Pandey
On Wed, 5 Feb 2025 at 15:57, Nitin Rawat <quic_nitirawa@quicinc.com> wrote:
>
>
>
> On 2/5/2025 5:14 PM, Dmitry Baryshkov wrote:
> > On Wed, 5 Feb 2025 at 13:34, Nitin Rawat <quic_nitirawa@quicinc.com> wrote:
> >>
> >>
> >>
> >> On 1/14/2025 4:19 PM, Dmitry Baryshkov wrote:
> >>> On Mon, Jan 13, 2025 at 01:46:25PM -0800, Melody Olvera wrote:
> >>>> From: Nitin Rawat <quic_nitirawa@quicinc.com>
> >>>>
> >>>> Add SM8750 specific register layout and table configs. The serdes
> >>>> TX RX register offset has changed for SM8750 and hence keep UFS
> >>>> specific serdes offsets in a dedicated header file.
> >>>>
> >>>> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> >>>> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> >>>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> >>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> >>>> ---
> >>>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 12 ++
> >>>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h | 68 ++++++++
> >>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 174 ++++++++++++++++++++-
> >>>> 3 files changed, 253 insertions(+), 1 deletion(-)
> >>>>
> >>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> >>>> index 328c6c0b0b09ae4ff5bf14e846772e6d0f31ce5a..aa2278f9377408b3c602f6fa0de5021804f21f52 100644
> >>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> >>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> >>>> @@ -86,4 +86,16 @@
> >>>> #define QSERDES_V6_COM_CMN_STATUS 0x1d0
> >>>> #define QSERDES_V6_COM_C_READY_STATUS 0x1f8
> >>>>
> >>>> +#define QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG 0x268
> >>>> +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0 0x26c
> >>>> +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x270
> >>>> +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x274
> >>>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58
> >>>> +
> >>>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c
> >>>> +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1 0x278
> >>>> +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x27c
> >>>> +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x280
> >>>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
> >>>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54
> >>>> #endif
> >>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
> >>>> new file mode 100644
> >>>> index 0000000000000000000000000000000000000000..73b3857e0277ce6cdbe658066772172a94f25d6e
> >>>> --- /dev/null
> >>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
> >>>> @@ -0,0 +1,68 @@
> >>>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>>> +/*
> >>>> + * Copyright (c) 2024, Linaro Limited
> >>>> + */
> >>>> +
> >>>> +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
> >>>> +#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
> >>>> +
> >>>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_TX 0x28
> >>>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_RX 0x2c
> >>>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX 0x30
> >>>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX 0x34
> >>>> +#define QSERDES_UFS_V7_TX_LANE_MODE_1 0x7c
> >>>> +#define QSERDES_UFS_V7_TX_FR_DCC_CTRL 0x108
> >>>> +
> >>>> +#define QSERDES_UFS_V7_RX_UCDR_SO_SATURATION 0x28
> >>>> +#define QSERDES_UFS_V7_RX_UCDR_PI_CTRL1 0x58
> >>>> +#define QSERDES_UFS_V7_RX_TERM_BW_CTRL0 0xC4
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0 0x218
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1 0x21C
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2 0x220
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3 0x224
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4 0x228
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6 0x230
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7 0x234
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B3 0x248
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B6 0x254
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B7 0x258
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B0 0x260
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B1 0x264
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B2 0x268
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B3 0x26C
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B4 0x270
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B5 0x274
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B7 0x27C
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B8 0x280
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0 0x284
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1 0x288
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2 0x28C
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3 0x290
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4 0x294
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5 0x298
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6 0x29C
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7 0x2A0
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0 0x2A8
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1 0x2AC
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2 0x2B0
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3 0x2B4
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4 0x2B8
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5 0x2BC
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6 0x2C0
> >>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7 0x2C4
> >>>> +#define QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL 0x348
> >>>> +#define QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM 0x380
> >>>> +#define QSERDES_UFS_V7_RX_INTERFACE_MODE 0x1F0
> >>>> +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2 0xD4
> >>>> +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4 0xDC
> >>>> +#define QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4 0xF0
> >>>> +#define QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS 0xF4
> >>>> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> >>>> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> >>>> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> >>>> +#define QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1CC
> >>>> +#define QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3 0x1D4
> >>>> +#define QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4 0x1B4
> >>>> +#define QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL 0x178
> >>>
> >>> - Lowercase hex
> >>> - Sort RX by the register offset
> >>
> >> Sure Will take care in next patchset.
> >
> > Just to note, please sort QSERDES_V6_COM regs too.
> >
> >>
> >>>
> >>>
> >>>> +
> >>>> +#endif
> >>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>>> index d964bdfe870029226482f264c78a27d0ec43bf2b..a1695b368fe7622bf8663343d0241b4d0d40ab59 100644
> >>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>>> @@ -31,6 +31,7 @@
> >>>> #include "phy-qcom-qmp-pcs-ufs-v6.h"
> >>>>
> >>>> #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
> >>>> +#include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h"
> >>>>
> >>>> /* QPHY_PCS_READY_STATUS bit */
> >>>> #define PCS_READY BIT(0)
> >>>> @@ -949,6 +950,132 @@ static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = {
> >>>> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> >>>> };
> >>>>
> >>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = {
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xD9),
> >>>
> >>> Lowercase hex
> >>
> >> Sure Will take care in next patchset.
> >>>
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x60),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1F),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1F),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x07),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x20),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x40),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG, 0x06),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7F),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4C),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xBE),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
> >>>> +};
> >>>> +
> >>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = {
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_LANE_MODE_1, 0x00),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x17),
> >>>> +};
> >>>> +
> >>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = {
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0C),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0C),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0E),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1C),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0x8E),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0F),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xCE),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xCE),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1A),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0F),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9A),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xE2),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1B),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1B),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9B),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2A),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5F),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xE3),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x9B),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x9B),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0x60),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5F),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xFB),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1F),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xFA),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30),
> >>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77),
> >>>> +};
> >>>> +
> >>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = {
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40),
> >>>
> >>> Why does SM8650 have 0xc1 here?
> >>
> >> SM8750 phy is different from SM8650 and hence it is using different phy
> >> calibration setting. This value is as per Hardware programming guide.'
> >
> > Ack.
> >
> >>
> >>>
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0F),
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0E),
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12),
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15),
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19),
> >>>> +};
> >>>> +
> >>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = {
> >>>
> >>> Missing QPHY_V6_PCS_UFS_PLL_CNTL, then it becomes sm8650_ufsphy_g4_pcs
> >>
> >> The value of QPHY_V6_PCS_UFS_PLL_CNTL is 0x33 for SM8750 as it is
> >> operating on 80bit mode. Similiar change needs to be done for SM8650.
> >
> > Ack, please check if that allows the driver to use the same set of
> > tables for SM8650 and SM8750.
> >
> >>>
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> >>>> +};
> >>>> +
> >>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_g5_pcs[] = {
> >>>
> >>> sm8650_ufsphy_g5_pcs?
> >> Agree with you. Good Finding. I will replace sm8750_ufsphy_g5_pcs with
> >> sm8650_ufsphy_g5_pcs.
> >>
> >>
> >>>
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05),
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05),
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d),
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> >>>> +};
> >>>> +
> >>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = {
> >>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x41),
> >>>> +};
> >>>> +
> >>>> struct qmp_ufs_offsets {
> >>>> u16 serdes;
> >>>> u16 pcs;
> >>>> @@ -1523,6 +1650,45 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
> >>>> .regs = ufsphy_v6_regs_layout,
> >>>> };
> >>>>
> >>>> +static const struct qmp_phy_cfg sm8750_ufsphy_cfg = {
> >>>> + .lanes = 2,
> >>>> +
> >>>> + .offsets = &qmp_ufs_offsets_v6,
> >>>> + .max_supported_gear = UFS_HS_G5,
> >>>> +
> >>>> + .tbls = {
> >>>> + .serdes = sm8750_ufsphy_serdes,
> >>>> + .serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes),
> >>>> + .tx = sm8750_ufsphy_tx,
> >>>> + .tx_num = ARRAY_SIZE(sm8750_ufsphy_tx),
> >>>> + .rx = sm8750_ufsphy_rx,
> >>>> + .rx_num = ARRAY_SIZE(sm8750_ufsphy_rx),
> >>>> + .pcs = sm8750_ufsphy_pcs,
> >>>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs),
> >>>> + },
> >>>> +
> >>>> + .tbls_hs_b = {
> >>>> + .pcs = sm8750_ufsphy_hs_b_pcs,
> >>>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs),
> >>>> + },
> >>>> +
> >>>> + .tbls_hs_overlay[0] = {
> >>>> + .pcs = sm8750_ufsphy_g4_pcs,
> >>>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs),
> >>>> + .max_gear = UFS_HS_G4,
> >>>> + },
> >>>> + .tbls_hs_overlay[1] = {
> >>>> + .pcs = sm8750_ufsphy_g5_pcs,
> >>>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g5_pcs),
> >>>> + .max_gear = UFS_HS_G5,
> >>>> + },
> >>>> +
> >>>> + .vreg_list = qmp_phy_vreg_l,
> >>>> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> >>>> + .regs = ufsphy_v6_regs_layout,
> >>>> +
> >>>> +};
> >>>> +
> >>>> static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
> >>>> {
> >>>> void __iomem *serdes = qmp->serdes;
> >>>> @@ -1593,8 +1759,10 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg
> >>>> qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
> >>>> }
> >>>>
> >>>> - if (qmp->mode == PHY_MODE_UFS_HS_B)
> >>>> + if (qmp->mode == PHY_MODE_UFS_HS_B) {
> >>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
> >>>> + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_b);
> >>>
> >>> Extract the serdes+lanes+pcs helper, use it in this function.
> >>
> >> Lane init is already a different helper and is already being called from
> >> function (qmp_ufs_init_register). Here we just adding few extra PCS
> >> registers needed to support Rate B.
> >
> > Please extract the helper that calls qmp_ufs_serdes_init() +
> > qmp_ufs_lanes_init() + qmp_ufs_pcs_init() over a particular table.
>
> Hi Dmitry,
>
> Do you mean to move qmp_ufs_serdes_init , qmp_ufs_lanes_init and
> qmp_ufs_pcs_init into a different wrapper function and call this wrapper
> from qmp_ufs_init_registers for each table.
Yes.
>
> But for tbls_hs_b, we just need qmp_ufs_serdes_init and
> qmp_ufs_pcs_init. qmp_ufs_lanes_init is not required for tbls_hs_b.
> So wrapper API won't be of much help.
It still is, it removes a need to care about the particular table.
Historically tbls_hs_b had only qserdes. Now you've added pcs. I don't
think we should wait for somebody to add tx/rx on top of that.
>
> Regards,
> Nitin
>
>
> >
> >>
> >>>
> >>>> + }
> >>>> }
> >>>>
> >>>> static int qmp_ufs_com_init(struct qmp_ufs *qmp)
> >>>> @@ -2061,7 +2229,11 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
> >>>> }, {
> >>>> .compatible = "qcom,sm8650-qmp-ufs-phy",
> >>>> .data = &sm8650_ufsphy_cfg,
> >>>> + }, {
> >>>> + .compatible = "qcom,sm8750-qmp-ufs-phy",
> >>>> + .data = &sm8750_ufsphy_cfg,
> >>>> },
> >>>> +
> >>>> { },
> >>>> };
> >>>> MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);
> >>>>
> >>>> --
> >>>> 2.46.1
> >>>>
> >>>
> >> Thanks,
> >> Nitin
> >>
> >
> >
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 2/5] phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
2025-02-05 14:28 ` Dmitry Baryshkov
@ 2025-02-07 9:14 ` Nitin Rawat
0 siblings, 0 replies; 37+ messages in thread
From: Nitin Rawat @ 2025-02-07 9:14 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Manish Pandey
On 2/5/2025 7:58 PM, Dmitry Baryshkov wrote:
> On Wed, 5 Feb 2025 at 15:57, Nitin Rawat <quic_nitirawa@quicinc.com> wrote:
>>
>>
>>
>> On 2/5/2025 5:14 PM, Dmitry Baryshkov wrote:
>>> On Wed, 5 Feb 2025 at 13:34, Nitin Rawat <quic_nitirawa@quicinc.com> wrote:
>>>>
>>>>
>>>>
>>>> On 1/14/2025 4:19 PM, Dmitry Baryshkov wrote:
>>>>> On Mon, Jan 13, 2025 at 01:46:25PM -0800, Melody Olvera wrote:
>>>>>> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>>>>>>
>>>>>> Add SM8750 specific register layout and table configs. The serdes
>>>>>> TX RX register offset has changed for SM8750 and hence keep UFS
>>>>>> specific serdes offsets in a dedicated header file.
>>>>>>
>>>>>> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
>>>>>> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
>>>>>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>>>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>>>> ---
>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 12 ++
>>>>>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h | 68 ++++++++
>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 174 ++++++++++++++++++++-
>>>>>> 3 files changed, 253 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>> index 328c6c0b0b09ae4ff5bf14e846772e6d0f31ce5a..aa2278f9377408b3c602f6fa0de5021804f21f52 100644
>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>> @@ -86,4 +86,16 @@
>>>>>> #define QSERDES_V6_COM_CMN_STATUS 0x1d0
>>>>>> #define QSERDES_V6_COM_C_READY_STATUS 0x1f8
>>>>>>
>>>>>> +#define QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG 0x268
>>>>>> +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0 0x26c
>>>>>> +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x270
>>>>>> +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x274
>>>>>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58
>>>>>> +
>>>>>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c
>>>>>> +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1 0x278
>>>>>> +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x27c
>>>>>> +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x280
>>>>>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
>>>>>> +#define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54
>>>>>> #endif
>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
>>>>>> new file mode 100644
>>>>>> index 0000000000000000000000000000000000000000..73b3857e0277ce6cdbe658066772172a94f25d6e
>>>>>> --- /dev/null
>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h
>>>>>> @@ -0,0 +1,68 @@
>>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>>>>> +/*
>>>>>> + * Copyright (c) 2024, Linaro Limited
>>>>>> + */
>>>>>> +
>>>>>> +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
>>>>>> +#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
>>>>>> +
>>>>>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_TX 0x28
>>>>>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_RX 0x2c
>>>>>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX 0x30
>>>>>> +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX 0x34
>>>>>> +#define QSERDES_UFS_V7_TX_LANE_MODE_1 0x7c
>>>>>> +#define QSERDES_UFS_V7_TX_FR_DCC_CTRL 0x108
>>>>>> +
>>>>>> +#define QSERDES_UFS_V7_RX_UCDR_SO_SATURATION 0x28
>>>>>> +#define QSERDES_UFS_V7_RX_UCDR_PI_CTRL1 0x58
>>>>>> +#define QSERDES_UFS_V7_RX_TERM_BW_CTRL0 0xC4
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0 0x218
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1 0x21C
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2 0x220
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3 0x224
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4 0x228
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6 0x230
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7 0x234
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B3 0x248
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B6 0x254
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE2_B7 0x258
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B0 0x260
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B1 0x264
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B2 0x268
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B3 0x26C
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B4 0x270
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B5 0x274
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B7 0x27C
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE3_B8 0x280
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0 0x284
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1 0x288
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2 0x28C
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3 0x290
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4 0x294
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5 0x298
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6 0x29C
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7 0x2A0
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0 0x2A8
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1 0x2AC
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2 0x2B0
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3 0x2B4
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4 0x2B8
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5 0x2BC
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6 0x2C0
>>>>>> +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7 0x2C4
>>>>>> +#define QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL 0x348
>>>>>> +#define QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM 0x380
>>>>>> +#define QSERDES_UFS_V7_RX_INTERFACE_MODE 0x1F0
>>>>>> +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2 0xD4
>>>>>> +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4 0xDC
>>>>>> +#define QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4 0xF0
>>>>>> +#define QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS 0xF4
>>>>>> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
>>>>>> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
>>>>>> +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
>>>>>> +#define QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1CC
>>>>>> +#define QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3 0x1D4
>>>>>> +#define QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4 0x1B4
>>>>>> +#define QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL 0x178
>>>>>
>>>>> - Lowercase hex
>>>>> - Sort RX by the register offset
>>>>
>>>> Sure Will take care in next patchset.
>>>
>>> Just to note, please sort QSERDES_V6_COM regs too.
>>>
>>>>
>>>>>
>>>>>
>>>>>> +
>>>>>> +#endif
>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>> index d964bdfe870029226482f264c78a27d0ec43bf2b..a1695b368fe7622bf8663343d0241b4d0d40ab59 100644
>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>> @@ -31,6 +31,7 @@
>>>>>> #include "phy-qcom-qmp-pcs-ufs-v6.h"
>>>>>>
>>>>>> #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
>>>>>> +#include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h"
>>>>>>
>>>>>> /* QPHY_PCS_READY_STATUS bit */
>>>>>> #define PCS_READY BIT(0)
>>>>>> @@ -949,6 +950,132 @@ static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = {
>>>>>> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
>>>>>> };
>>>>>>
>>>>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = {
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xD9),
>>>>>
>>>>> Lowercase hex
>>>>
>>>> Sure Will take care in next patchset.
>>>>>
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x60),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1F),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1F),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x07),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x20),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x40),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG, 0x06),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7F),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4C),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xBE),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
>>>>>> +};
>>>>>> +
>>>>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = {
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_LANE_MODE_1, 0x00),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x17),
>>>>>> +};
>>>>>> +
>>>>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = {
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0C),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0C),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0E),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1C),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0x8E),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0F),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xCE),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xCE),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1A),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0F),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9A),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xE2),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1B),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1B),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9B),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2A),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5F),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xE3),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x9B),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x9B),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0x60),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5F),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xFB),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1F),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xFA),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30),
>>>>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77),
>>>>>> +};
>>>>>> +
>>>>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = {
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40),
>>>>>
>>>>> Why does SM8650 have 0xc1 here?
>>>>
>>>> SM8750 phy is different from SM8650 and hence it is using different phy
>>>> calibration setting. This value is as per Hardware programming guide.'
>>>
>>> Ack.
>>>
>>>>
>>>>>
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0F),
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0E),
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12),
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15),
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19),
>>>>>> +};
>>>>>> +
>>>>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = {
>>>>>
>>>>> Missing QPHY_V6_PCS_UFS_PLL_CNTL, then it becomes sm8650_ufsphy_g4_pcs
>>>>
>>>> The value of QPHY_V6_PCS_UFS_PLL_CNTL is 0x33 for SM8750 as it is
>>>> operating on 80bit mode. Similiar change needs to be done for SM8650.
>>>
>>> Ack, please check if that allows the driver to use the same set of
>>> tables for SM8650 and SM8750.
>>>
>>>>>
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
>>>>>> +};
>>>>>> +
>>>>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_g5_pcs[] = {
>>>>>
>>>>> sm8650_ufsphy_g5_pcs?
>>>> Agree with you. Good Finding. I will replace sm8750_ufsphy_g5_pcs with
>>>> sm8650_ufsphy_g5_pcs.
>>>>
>>>>
>>>>>
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05),
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05),
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d),
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
>>>>>> +};
>>>>>> +
>>>>>> +static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = {
>>>>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x41),
>>>>>> +};
>>>>>> +
>>>>>> struct qmp_ufs_offsets {
>>>>>> u16 serdes;
>>>>>> u16 pcs;
>>>>>> @@ -1523,6 +1650,45 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
>>>>>> .regs = ufsphy_v6_regs_layout,
>>>>>> };
>>>>>>
>>>>>> +static const struct qmp_phy_cfg sm8750_ufsphy_cfg = {
>>>>>> + .lanes = 2,
>>>>>> +
>>>>>> + .offsets = &qmp_ufs_offsets_v6,
>>>>>> + .max_supported_gear = UFS_HS_G5,
>>>>>> +
>>>>>> + .tbls = {
>>>>>> + .serdes = sm8750_ufsphy_serdes,
>>>>>> + .serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes),
>>>>>> + .tx = sm8750_ufsphy_tx,
>>>>>> + .tx_num = ARRAY_SIZE(sm8750_ufsphy_tx),
>>>>>> + .rx = sm8750_ufsphy_rx,
>>>>>> + .rx_num = ARRAY_SIZE(sm8750_ufsphy_rx),
>>>>>> + .pcs = sm8750_ufsphy_pcs,
>>>>>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs),
>>>>>> + },
>>>>>> +
>>>>>> + .tbls_hs_b = {
>>>>>> + .pcs = sm8750_ufsphy_hs_b_pcs,
>>>>>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs),
>>>>>> + },
>>>>>> +
>>>>>> + .tbls_hs_overlay[0] = {
>>>>>> + .pcs = sm8750_ufsphy_g4_pcs,
>>>>>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs),
>>>>>> + .max_gear = UFS_HS_G4,
>>>>>> + },
>>>>>> + .tbls_hs_overlay[1] = {
>>>>>> + .pcs = sm8750_ufsphy_g5_pcs,
>>>>>> + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g5_pcs),
>>>>>> + .max_gear = UFS_HS_G5,
>>>>>> + },
>>>>>> +
>>>>>> + .vreg_list = qmp_phy_vreg_l,
>>>>>> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
>>>>>> + .regs = ufsphy_v6_regs_layout,
>>>>>> +
>>>>>> +};
>>>>>> +
>>>>>> static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
>>>>>> {
>>>>>> void __iomem *serdes = qmp->serdes;
>>>>>> @@ -1593,8 +1759,10 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg
>>>>>> qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
>>>>>> }
>>>>>>
>>>>>> - if (qmp->mode == PHY_MODE_UFS_HS_B)
>>>>>> + if (qmp->mode == PHY_MODE_UFS_HS_B) {
>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
>>>>>> + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_b);
>>>>>
>>>>> Extract the serdes+lanes+pcs helper, use it in this function.
>>>>
>>>> Lane init is already a different helper and is already being called from
>>>> function (qmp_ufs_init_register). Here we just adding few extra PCS
>>>> registers needed to support Rate B.
>>>
>>> Please extract the helper that calls qmp_ufs_serdes_init() +
>>> qmp_ufs_lanes_init() + qmp_ufs_pcs_init() over a particular table.
>>
>> Hi Dmitry,
>>
>> Do you mean to move qmp_ufs_serdes_init , qmp_ufs_lanes_init and
>> qmp_ufs_pcs_init into a different wrapper function and call this wrapper
>> from qmp_ufs_init_registers for each table.
>
> Yes.
>
>>
>> But for tbls_hs_b, we just need qmp_ufs_serdes_init and
>> qmp_ufs_pcs_init. qmp_ufs_lanes_init is not required for tbls_hs_b.
>> So wrapper API won't be of much help.
>
> It still is, it removes a need to care about the particular table.
> Historically tbls_hs_b had only qserdes. Now you've added pcs. I don't
> think we should wait for somebody to add tx/rx on top of that.
Sure. I'll take care of this as well in next patchset. Thanks.
>
>>
>> Regards,
>> Nitin
>>
>>
>>>
>>>>
>>>>>
>>>>>> + }
>>>>>> }
>>>>>>
>>>>>> static int qmp_ufs_com_init(struct qmp_ufs *qmp)
>>>>>> @@ -2061,7 +2229,11 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
>>>>>> }, {
>>>>>> .compatible = "qcom,sm8650-qmp-ufs-phy",
>>>>>> .data = &sm8650_ufsphy_cfg,
>>>>>> + }, {
>>>>>> + .compatible = "qcom,sm8750-qmp-ufs-phy",
>>>>>> + .data = &sm8750_ufsphy_cfg,
>>>>>> },
>>>>>> +
>>>>>> { },
>>>>>> };
>>>>>> MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);
>>>>>>
>>>>>> --
>>>>>> 2.46.1
>>>>>>
>>>>>
>>>> Thanks,
>>>> Nitin
>>>>
>>>
>>>
>>
>
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 0/5] Add UFS support for SM8750
2025-01-13 21:46 [PATCH 0/5] Add UFS support for SM8750 Melody Olvera
` (4 preceding siblings ...)
2025-01-13 21:46 ` [PATCH 5/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards Melody Olvera
@ 2025-02-07 22:47 ` Konrad Dybcio
2025-02-08 17:57 ` Nitin Rawat
2025-02-09 15:21 ` Manivannan Sadhasivam
5 siblings, 2 replies; 37+ messages in thread
From: Konrad Dybcio @ 2025-02-07 22:47 UTC (permalink / raw)
To: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
Nitin Rawat, Manish Pandey
On 13.01.2025 10:46 PM, Melody Olvera wrote:
> Add UFS support for SM8750 SoCs.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> Nitin Rawat (5):
> dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY
> phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
> dt-bindings: ufs: qcom: Document the SM8750 UFS Controller
> arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
> arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards
You still need the same workaround 8550/8650 have in the UFS driver
(UFSHCD_QUIRK_BROKEN_LSDBS_CAP) for it to work reliably, or at least
that was the case for me on a 8750 QRD.
Please check whether we can make that quirk apply based on ctrl
version or so, so that we don't have to keep growing the compatible
list in the driver.
Konrad
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
2025-01-13 21:46 ` [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC Melody Olvera
` (2 preceding siblings ...)
2025-01-27 10:23 ` Konrad Dybcio
@ 2025-02-08 1:43 ` Konrad Dybcio
3 siblings, 0 replies; 37+ messages in thread
From: Konrad Dybcio @ 2025-02-08 1:43 UTC (permalink / raw)
To: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
Nitin Rawat, Manish Pandey
On 13.01.2025 10:46 PM, Melody Olvera wrote:
> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>
> Add UFS host controller and PHY nodes for SM8750 SoC.
>
> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
Please also add this bit:
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 3bbd7d18598e..1f79f2adb0a5 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -532,9 +532,9 @@ gcc: clock-controller@100000 {
<0>,
<&sleep_clk>,
<0>,
- <0>,
- <0>,
- <0>,
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>,
<0>;
#clock-cells = <1>;
Konrad
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH 0/5] Add UFS support for SM8750
2025-02-07 22:47 ` [PATCH 0/5] Add UFS support for SM8750 Konrad Dybcio
@ 2025-02-08 17:57 ` Nitin Rawat
2025-02-09 15:21 ` Manivannan Sadhasivam
1 sibling, 0 replies; 37+ messages in thread
From: Nitin Rawat @ 2025-02-08 17:57 UTC (permalink / raw)
To: Konrad Dybcio, Melody Olvera, Vinod Koul, Kishon Vijay Abraham I,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Alim Akhtar, Avri Altman, Bart Van Assche,
Bjorn Andersson, Andy Gross, Konrad Dybcio,
Satya Durga Srinivasu Prabhala, Trilok Soni
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
Manish Pandey
On 2/8/2025 4:17 AM, Konrad Dybcio wrote:
> On 13.01.2025 10:46 PM, Melody Olvera wrote:
>> Add UFS support for SM8750 SoCs.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> Nitin Rawat (5):
>> dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY
>> phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
>> dt-bindings: ufs: qcom: Document the SM8750 UFS Controller
>> arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
>> arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards
>
> You still need the same workaround 8550/8650 have in the UFS driver
> (UFSHCD_QUIRK_BROKEN_LSDBS_CAP) for it to work reliably, or at least
> that was the case for me on a 8750 QRD.
Hi Konrad,
The LSDBS workaround is only applicable for SM8650 and SM8550.
SM8750 and onwards doesn't need this WA anymore as it is fixed in HW.
Thanks,
Nitin
>
> Please check whether we can make that quirk apply based on ctrl
> version or so, so that we don't have to keep growing the compatible
> list in the driver.
>
> Konrad
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
2025-01-14 10:52 ` Dmitry Baryshkov
@ 2025-02-08 19:17 ` Nitin Rawat
2025-02-08 22:06 ` Dmitry Baryshkov
0 siblings, 1 reply; 37+ messages in thread
From: Nitin Rawat @ 2025-02-08 19:17 UTC (permalink / raw)
To: Dmitry Baryshkov, Melody Olvera
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Manish Pandey
On 1/14/2025 4:22 PM, Dmitry Baryshkov wrote:
> On Mon, Jan 13, 2025 at 01:46:27PM -0800, Melody Olvera wrote:
>> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>>
>> Add UFS host controller and PHY nodes for SM8750 SoC.
>>
>> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
>> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sm8750.dtsi | 81 ++++++++++++++++++++++++++++++++++++
>> 1 file changed, 81 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..20690c102244b337847a6482dd83c37e19746de9 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> @@ -13,6 +13,7 @@
>> #include <dt-bindings/power/qcom,rpmhpd.h>
>> #include <dt-bindings/power/qcom-rpmpd.h>
>> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>> +#include <dt-bindings/gpio/gpio.h>
>>
>> / {
>> interrupt-parent = <&intc>;
>> @@ -1939,6 +1940,86 @@ mmss_noc: interconnect@1780000 {
>> #interconnect-cells = <2>;
>> };
>>
>> + ufs_mem_phy: phy@1d80000 {
>> + compatible = "qcom,sm8750-qmp-ufs-phy";
>> + reg = <0x0 0x01d80000 0x0 0x2000>;
>> +
>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>> + <&tcsrcc TCSR_UFS_CLKREF_EN>;
>> + clock-names = "ref",
>> + "ref_aux",
>> + "qref";
>> +
>> + resets = <&ufs_mem_hc 0>;
>> + reset-names = "ufsphy";
>> +
>> + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
>> +
>> + #clock-cells = <1>;
>> + #phy-cells = <0>;
>> +
>> + status = "disabled";
>> + };
>> +
>> + ufs_mem_hc: ufs@1d84000 {
>> + compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
>> + reg = <0x0 0x01d84000 0x0 0x3000>;
>> +
>> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
>> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
>> + <&gcc GCC_UFS_PHY_AHB_CLK>,
>> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
>> + <&rpmhcc RPMH_LN_BB_CLK3>,
>> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
>> + clock-names = "core_clk",
>> + "bus_aggr_clk",
>> + "iface_clk",
>> + "core_clk_unipro",
>> + "ref_clk",
>> + "tx_lane0_sync_clk",
>> + "rx_lane0_sync_clk",
>> + "rx_lane1_sync_clk";
>> + freq-table-hz = <100000000 403000000>,
>> + <0 0>,
>> + <0 0>,
>> + <100000000 403000000>,
>> + <100000000 403000000>,
>> + <0 0>,
>> + <0 0>,
>> + <0 0>;
>
> Use OPP table instead
Currently, OPP is not enabled in the device tree for any previous
targets. I plan to enable OPP in a separate patch at a later stage. This
is because there is an ongoing patch in the upstream that aims to enable
multiple-level clock scaling using OPP, which may introduce changes to
the device tree entries. To avoid extra efforts, I intend to enable OPP
once that patch is merged.
Please let me know if you have any concerns.
>
>> +
>> + resets = <&gcc GCC_UFS_PHY_BCR>;
>> + reset-names = "rst";
>> +
>> +
>> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>> + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
>
> Shouldn't cpu-ufs be ACTIVE_ONLY?
As per ufs driver implementation, Icc voting from ufs driver is removed
as part of low power mode (suspend or clock gating) and voted again in
resume/ungating path. Hence TAG_ALWAYS will have no power concern.
All previous targets have the same configuration.
Thanks,
Nitin
>
>> + interconnect-names = "ufs-ddr",
>> + "cpu-ufs";
>> +
>> + power-domains = <&gcc GCC_UFS_PHY_GDSC>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> +
>> + iommus = <&apps_smmu 0x60 0>;
>> + dma-coherent;
>> +
>> + lanes-per-direction = <2>;
>> +
>> + phys = <&ufs_mem_phy>;
>> + phy-names = "ufsphy";
>> +
>> + #reset-cells = <1>;
>> +
>> + status = "disabled";
>> + };
>> +
>> tcsr_mutex: hwlock@1f40000 {
>> compatible = "qcom,tcsr-mutex";
>> reg = <0x0 0x01f40000 0x0 0x20000>;
>>
>> --
>> 2.46.1
>>
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
2025-02-08 19:17 ` Nitin Rawat
@ 2025-02-08 22:06 ` Dmitry Baryshkov
2025-02-10 19:20 ` Konrad Dybcio
0 siblings, 1 reply; 37+ messages in thread
From: Dmitry Baryshkov @ 2025-02-08 22:06 UTC (permalink / raw)
To: Nitin Rawat
Cc: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Manish Pandey
On Sun, Feb 09, 2025 at 12:47:56AM +0530, Nitin Rawat wrote:
>
>
> On 1/14/2025 4:22 PM, Dmitry Baryshkov wrote:
> > On Mon, Jan 13, 2025 at 01:46:27PM -0800, Melody Olvera wrote:
> > > From: Nitin Rawat <quic_nitirawa@quicinc.com>
> > >
> > > Add UFS host controller and PHY nodes for SM8750 SoC.
> > >
> > > Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> > > Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> > > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> > > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> > > ---
> > > arch/arm64/boot/dts/qcom/sm8750.dtsi | 81 ++++++++++++++++++++++++++++++++++++
> > > 1 file changed, 81 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> > > index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..20690c102244b337847a6482dd83c37e19746de9 100644
> > > --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> > > @@ -13,6 +13,7 @@
> > > #include <dt-bindings/power/qcom,rpmhpd.h>
> > > #include <dt-bindings/power/qcom-rpmpd.h>
> > > #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> > > +#include <dt-bindings/gpio/gpio.h>
> > > / {
> > > interrupt-parent = <&intc>;
> > > @@ -1939,6 +1940,86 @@ mmss_noc: interconnect@1780000 {
> > > #interconnect-cells = <2>;
> > > };
> > > + ufs_mem_phy: phy@1d80000 {
> > > + compatible = "qcom,sm8750-qmp-ufs-phy";
> > > + reg = <0x0 0x01d80000 0x0 0x2000>;
> > > +
> > > + clocks = <&rpmhcc RPMH_CXO_CLK>,
> > > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> > > + <&tcsrcc TCSR_UFS_CLKREF_EN>;
> > > + clock-names = "ref",
> > > + "ref_aux",
> > > + "qref";
> > > +
> > > + resets = <&ufs_mem_hc 0>;
> > > + reset-names = "ufsphy";
> > > +
> > > + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
> > > +
> > > + #clock-cells = <1>;
> > > + #phy-cells = <0>;
> > > +
> > > + status = "disabled";
> > > + };
> > > +
> > > + ufs_mem_hc: ufs@1d84000 {
> > > + compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
> > > + reg = <0x0 0x01d84000 0x0 0x3000>;
> > > +
> > > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> > > +
> > > + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> > > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> > > + <&gcc GCC_UFS_PHY_AHB_CLK>,
> > > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> > > + <&rpmhcc RPMH_LN_BB_CLK3>,
> > > + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> > > + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> > > + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> > > + clock-names = "core_clk",
> > > + "bus_aggr_clk",
> > > + "iface_clk",
> > > + "core_clk_unipro",
> > > + "ref_clk",
> > > + "tx_lane0_sync_clk",
> > > + "rx_lane0_sync_clk",
> > > + "rx_lane1_sync_clk";
> > > + freq-table-hz = <100000000 403000000>,
> > > + <0 0>,
> > > + <0 0>,
> > > + <100000000 403000000>,
> > > + <100000000 403000000>,
> > > + <0 0>,
> > > + <0 0>,
> > > + <0 0>;
> >
> > Use OPP table instead
>
> Currently, OPP is not enabled in the device tree for any previous targets. I
Excuse me? ufs_opp_table is present on SM8250, SM8550 and SDM845 (and
QCS615). So this is not correct
> plan to enable OPP in a separate patch at a later stage. This is because
> there is an ongoing patch in the upstream that aims to enable multiple-level
> clock scaling using OPP, which may introduce changes to the device tree
> entries. To avoid extra efforts, I intend to enable OPP once that patch is
> merged.
Whatever changes are introduced, old DT must still continue to work.
There is no reason to use legacy freq-table-hz if you can use OPP table.
> Please let me know if you have any concerns.
>
>
> >
> > > +
> > > + resets = <&gcc GCC_UFS_PHY_BCR>;
> > > + reset-names = "rst";
> > > +
> > > +
> > > + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
> > > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> > > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> > > + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
> >
> > Shouldn't cpu-ufs be ACTIVE_ONLY?
>
> As per ufs driver implementation, Icc voting from ufs driver is removed as
> part of low power mode (suspend or clock gating) and voted again in
> resume/ungating path. Hence TAG_ALWAYS will have no power concern.
> All previous targets have the same configuration.
arch/arm64/boot/dts/qcom/qcs615.dtsi: &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
It might be a mistake for that target though. Your explanation sounds
fine to me.
>
> Thanks,
> Nitin
>
>
> >
> > > + interconnect-names = "ufs-ddr",
> > > + "cpu-ufs";
> > > +
> > > + power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> > > + required-opps = <&rpmhpd_opp_nom>;
> > > +
> > > + iommus = <&apps_smmu 0x60 0>;
> > > + dma-coherent;
> > > +
> > > + lanes-per-direction = <2>;
> > > +
> > > + phys = <&ufs_mem_phy>;
> > > + phy-names = "ufsphy";
> > > +
> > > + #reset-cells = <1>;
> > > +
> > > + status = "disabled";
> > > + };
> > > +
> > > tcsr_mutex: hwlock@1f40000 {
> > > compatible = "qcom,tcsr-mutex";
> > > reg = <0x0 0x01f40000 0x0 0x20000>;
> > >
> > > --
> > > 2.46.1
> > >
> >
>
>
> --
> linux-phy mailing list
> linux-phy@lists.infradead.org
> https://lists.infradead.org/mailman/listinfo/linux-phy
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 0/5] Add UFS support for SM8750
2025-02-07 22:47 ` [PATCH 0/5] Add UFS support for SM8750 Konrad Dybcio
2025-02-08 17:57 ` Nitin Rawat
@ 2025-02-09 15:21 ` Manivannan Sadhasivam
2025-02-10 9:39 ` neil.armstrong
1 sibling, 1 reply; 37+ messages in thread
From: Manivannan Sadhasivam @ 2025-02-09 15:21 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Alim Akhtar, Avri Altman,
Bart Van Assche, Bjorn Andersson, Andy Gross, Konrad Dybcio,
Satya Durga Srinivasu Prabhala, Trilok Soni, linux-arm-msm,
linux-phy, devicetree, linux-kernel, linux-scsi, Nitin Rawat,
Manish Pandey
On Fri, Feb 07, 2025 at 11:47:12PM +0100, Konrad Dybcio wrote:
> On 13.01.2025 10:46 PM, Melody Olvera wrote:
> > Add UFS support for SM8750 SoCs.
> >
> > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> > ---
> > Nitin Rawat (5):
> > dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY
> > phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
> > dt-bindings: ufs: qcom: Document the SM8750 UFS Controller
> > arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
> > arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards
>
> You still need the same workaround 8550/8650 have in the UFS driver
> (UFSHCD_QUIRK_BROKEN_LSDBS_CAP) for it to work reliably, or at least
> that was the case for me on a 8750 QRD.
>
> Please check whether we can make that quirk apply based on ctrl
> version or so, so that we don't have to keep growing the compatible
> list in the driver.
>
That would be a bizarre. When I added the quirk, I was told that it would affect
only SM8550 and SM8650 (this one I learned later). I'm not against applying the
quirk based on UFSHC version if the bug is carried forward, but that would be an
indication of bad design.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 0/5] Add UFS support for SM8750
2025-02-09 15:21 ` Manivannan Sadhasivam
@ 2025-02-10 9:39 ` neil.armstrong
2025-02-10 10:13 ` Manivannan Sadhasivam
2025-02-10 11:15 ` Nitin Rawat
0 siblings, 2 replies; 37+ messages in thread
From: neil.armstrong @ 2025-02-10 9:39 UTC (permalink / raw)
To: Manivannan Sadhasivam, Konrad Dybcio
Cc: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Alim Akhtar, Avri Altman,
Bart Van Assche, Bjorn Andersson, Andy Gross, Konrad Dybcio,
Satya Durga Srinivasu Prabhala, Trilok Soni, linux-arm-msm,
linux-phy, devicetree, linux-kernel, linux-scsi, Nitin Rawat,
Manish Pandey
On 09/02/2025 16:21, Manivannan Sadhasivam wrote:
> On Fri, Feb 07, 2025 at 11:47:12PM +0100, Konrad Dybcio wrote:
>> On 13.01.2025 10:46 PM, Melody Olvera wrote:
>>> Add UFS support for SM8750 SoCs.
>>>
>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>> ---
>>> Nitin Rawat (5):
>>> dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY
>>> phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
>>> dt-bindings: ufs: qcom: Document the SM8750 UFS Controller
>>> arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
>>> arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards
>>
>> You still need the same workaround 8550/8650 have in the UFS driver
>> (UFSHCD_QUIRK_BROKEN_LSDBS_CAP) for it to work reliably, or at least
>> that was the case for me on a 8750 QRD.
>>
>> Please check whether we can make that quirk apply based on ctrl
>> version or so, so that we don't have to keep growing the compatible
>> list in the driver.
>>
>
> That would be a bizarre. When I added the quirk, I was told that it would affect
> only SM8550 and SM8650 (this one I learned later). I'm not against applying the
> quirk based on UFSHC version if the bug is carried forward, but that would be an
> indication of bad design.
Isn't 8750 capable of using MCQ now ? because this is the whole issue behind
this UFSHCD_QUIRK_BROKEN_LSDBS_CAP, it's supposed to use MCQ by default... but
we don't.
Is there any news about that ? It's a clear regression against downstream, not
having MCQ makes the UFS driver struggle to reach high bandwidth when the system
is busy because we can't spread the load over all CPUs and we have only single
queue to submit requests.
Neil
>
> - Mani
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 0/5] Add UFS support for SM8750
2025-02-10 9:39 ` neil.armstrong
@ 2025-02-10 10:13 ` Manivannan Sadhasivam
2025-02-10 11:08 ` Nitin Rawat
2025-02-10 11:15 ` Nitin Rawat
1 sibling, 1 reply; 37+ messages in thread
From: Manivannan Sadhasivam @ 2025-02-10 10:13 UTC (permalink / raw)
To: neil.armstrong, quic_cang
Cc: Konrad Dybcio, Melody Olvera, Vinod Koul, Kishon Vijay Abraham I,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alim Akhtar,
Avri Altman, Bart Van Assche, Bjorn Andersson, Andy Gross,
Konrad Dybcio, Satya Durga Srinivasu Prabhala, Trilok Soni,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
Nitin Rawat, Manish Pandey
+ Can (for the MCQ query)
On Mon, Feb 10, 2025 at 10:39:04AM +0100, neil.armstrong@linaro.org wrote:
> On 09/02/2025 16:21, Manivannan Sadhasivam wrote:
> > On Fri, Feb 07, 2025 at 11:47:12PM +0100, Konrad Dybcio wrote:
> > > On 13.01.2025 10:46 PM, Melody Olvera wrote:
> > > > Add UFS support for SM8750 SoCs.
> > > >
> > > > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> > > > ---
> > > > Nitin Rawat (5):
> > > > dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY
> > > > phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
> > > > dt-bindings: ufs: qcom: Document the SM8750 UFS Controller
> > > > arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
> > > > arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards
> > >
> > > You still need the same workaround 8550/8650 have in the UFS driver
> > > (UFSHCD_QUIRK_BROKEN_LSDBS_CAP) for it to work reliably, or at least
> > > that was the case for me on a 8750 QRD.
> > >
> > > Please check whether we can make that quirk apply based on ctrl
> > > version or so, so that we don't have to keep growing the compatible
> > > list in the driver.
> > >
> >
> > That would be a bizarre. When I added the quirk, I was told that it would affect
> > only SM8550 and SM8650 (this one I learned later). I'm not against applying the
> > quirk based on UFSHC version if the bug is carried forward, but that would be an
> > indication of bad design.
>
> Isn't 8750 capable of using MCQ now ? because this is the whole issue behind
> this UFSHCD_QUIRK_BROKEN_LSDBS_CAP, it's supposed to use MCQ by default... but
> we don't.
>
> Is there any news about that ? It's a clear regression against downstream, not
> having MCQ makes the UFS driver struggle to reach high bandwidth when the system
> is busy because we can't spread the load over all CPUs and we have only single
> queue to submit requests.
>
There are hardware issues on SM8550 and SM8650(?) for the MCQ feature.
Apparently, Qcom carries the workaround in downstream, but I got tired of
pushing them to upstream the fix(es).
Maybe Can Guo can share what is the latest update on this.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 0/5] Add UFS support for SM8750
2025-02-10 10:13 ` Manivannan Sadhasivam
@ 2025-02-10 11:08 ` Nitin Rawat
2025-02-10 15:21 ` Konrad Dybcio
0 siblings, 1 reply; 37+ messages in thread
From: Nitin Rawat @ 2025-02-10 11:08 UTC (permalink / raw)
To: Manivannan Sadhasivam, neil.armstrong, quic_cang
Cc: Konrad Dybcio, Melody Olvera, Vinod Koul, Kishon Vijay Abraham I,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alim Akhtar,
Avri Altman, Bart Van Assche, Bjorn Andersson, Andy Gross,
Konrad Dybcio, Satya Durga Srinivasu Prabhala, Trilok Soni,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
Manish Pandey
On 2/10/2025 3:43 PM, Manivannan Sadhasivam wrote:
> + Can (for the MCQ query)
>
> On Mon, Feb 10, 2025 at 10:39:04AM +0100, neil.armstrong@linaro.org wrote:
>> On 09/02/2025 16:21, Manivannan Sadhasivam wrote:
>>> On Fri, Feb 07, 2025 at 11:47:12PM +0100, Konrad Dybcio wrote:
>>>> On 13.01.2025 10:46 PM, Melody Olvera wrote:
>>>>> Add UFS support for SM8750 SoCs.
>>>>>
>>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>>> ---
>>>>> Nitin Rawat (5):
>>>>> dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY
>>>>> phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
>>>>> dt-bindings: ufs: qcom: Document the SM8750 UFS Controller
>>>>> arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
>>>>> arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards
>>>>
>>>> You still need the same workaround 8550/8650 have in the UFS driver
>>>> (UFSHCD_QUIRK_BROKEN_LSDBS_CAP) for it to work reliably, or at least
>>>> that was the case for me on a 8750 QRD.
>>>>
>>>> Please check whether we can make that quirk apply based on ctrl
>>>> version or so, so that we don't have to keep growing the compatible
>>>> list in the driver.
>>>>
>>>
>>> That would be a bizarre. When I added the quirk, I was told that it would affect
>>> only SM8550 and SM8650 (this one I learned later). I'm not against applying the
>>> quirk based on UFSHC version if the bug is carried forward, but that would be an
>>> indication of bad design.
>>
>> Isn't 8750 capable of using MCQ now ? because this is the whole issue behind
>> this UFSHCD_QUIRK_BROKEN_LSDBS_CAP, it's supposed to use MCQ by default... but
>> we don't.
>>
>> Is there any news about that ? It's a clear regression against downstream, not
>> having MCQ makes the UFS driver struggle to reach high bandwidth when the system
>> is busy because we can't spread the load over all CPUs and we have only single
>> queue to submit requests.
>>
>
> There are hardware issues on SM8550 and SM8650(?) for the MCQ feature.
> Apparently, Qcom carries the workaround in downstream, but I got tired of
> pushing them to upstream the fix(es).
>
> Maybe Can Guo can share what is the latest update on this.
>
> - Mani
>
Hi Mani,
I have already replied to konrad mail earlier in this thread.
The LSDBS workaround is only applicable for SM8650 and SM8550.
SM8750 and onwards doesn't need this WA anymore as it is fixed in HW.
Regards,
Nitin
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 0/5] Add UFS support for SM8750
2025-02-10 9:39 ` neil.armstrong
2025-02-10 10:13 ` Manivannan Sadhasivam
@ 2025-02-10 11:15 ` Nitin Rawat
2025-02-10 15:33 ` neil.armstrong
1 sibling, 1 reply; 37+ messages in thread
From: Nitin Rawat @ 2025-02-10 11:15 UTC (permalink / raw)
To: neil.armstrong, Manivannan Sadhasivam, Konrad Dybcio
Cc: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Alim Akhtar, Avri Altman,
Bart Van Assche, Bjorn Andersson, Andy Gross, Konrad Dybcio,
Satya Durga Srinivasu Prabhala, Trilok Soni, linux-arm-msm,
linux-phy, devicetree, linux-kernel, linux-scsi, Manish Pandey
On 2/10/2025 3:09 PM, neil.armstrong@linaro.org wrote:
> On 09/02/2025 16:21, Manivannan Sadhasivam wrote:
>> On Fri, Feb 07, 2025 at 11:47:12PM +0100, Konrad Dybcio wrote:
>>> On 13.01.2025 10:46 PM, Melody Olvera wrote:
>>>> Add UFS support for SM8750 SoCs.
>>>>
>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>> ---
>>>> Nitin Rawat (5):
>>>> dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the
>>>> SM8750 QMP UFS PHY
>>>> phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
>>>> dt-bindings: ufs: qcom: Document the SM8750 UFS Controller
>>>> arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
>>>> arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and
>>>> MTP boards
>>>
>>> You still need the same workaround 8550/8650 have in the UFS driver
>>> (UFSHCD_QUIRK_BROKEN_LSDBS_CAP) for it to work reliably, or at least
>>> that was the case for me on a 8750 QRD.
>>>
>>> Please check whether we can make that quirk apply based on ctrl
>>> version or so, so that we don't have to keep growing the compatible
>>> list in the driver.
>>>
>>
>> That would be a bizarre. When I added the quirk, I was told that it
>> would affect
>> only SM8550 and SM8650 (this one I learned later). I'm not against
>> applying the
>> quirk based on UFSHC version if the bug is carried forward, but that
>> would be an
>> indication of bad design.
>
> Isn't 8750 capable of using MCQ now ? because this is the whole issue
> behind
> this UFSHCD_QUIRK_BROKEN_LSDBS_CAP, it's supposed to use MCQ by
> default... but
> we don't.
>
> Is there any news about that ? It's a clear regression against
> downstream, not
> having MCQ makes the UFS driver struggle to reach high bandwidth when
> the system
> is busy because we can't spread the load over all CPUs and we have only
> single
> queue to submit requests.
Hi Neil,
There is no relation b/w LSDBS_CAP Register and MCQ support.
That registers just indicate when MCQ support is present on any SOC,
whether Single queue mode is supported or not on that SOC.
In SM8650 and SM86550, just the pored value of that register was
incorrect which was fixed by WA but actually functionality was present
and working fine.
Pored value of that register has been fixed from SM8750 onwards.
Regards,
Nitin
>
> Neil
>
>>
>> - Mani
>>
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 0/5] Add UFS support for SM8750
2025-02-10 11:08 ` Nitin Rawat
@ 2025-02-10 15:21 ` Konrad Dybcio
0 siblings, 0 replies; 37+ messages in thread
From: Konrad Dybcio @ 2025-02-10 15:21 UTC (permalink / raw)
To: Nitin Rawat, Manivannan Sadhasivam, neil.armstrong, quic_cang
Cc: Konrad Dybcio, Melody Olvera, Vinod Koul, Kishon Vijay Abraham I,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alim Akhtar,
Avri Altman, Bart Van Assche, Bjorn Andersson, Andy Gross,
Konrad Dybcio, Satya Durga Srinivasu Prabhala, Trilok Soni,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
Manish Pandey
On 10.02.2025 12:08 PM, Nitin Rawat wrote:
>
>
> On 2/10/2025 3:43 PM, Manivannan Sadhasivam wrote:
>> + Can (for the MCQ query)
>>
>> On Mon, Feb 10, 2025 at 10:39:04AM +0100, neil.armstrong@linaro.org wrote:
>>> On 09/02/2025 16:21, Manivannan Sadhasivam wrote:
>>>> On Fri, Feb 07, 2025 at 11:47:12PM +0100, Konrad Dybcio wrote:
>>>>> On 13.01.2025 10:46 PM, Melody Olvera wrote:
>>>>>> Add UFS support for SM8750 SoCs.
>>>>>>
>>>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>>>> ---
>>>>>> Nitin Rawat (5):
>>>>>> dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY
>>>>>> phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
>>>>>> dt-bindings: ufs: qcom: Document the SM8750 UFS Controller
>>>>>> arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
>>>>>> arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards
>>>>>
>>>>> You still need the same workaround 8550/8650 have in the UFS driver
>>>>> (UFSHCD_QUIRK_BROKEN_LSDBS_CAP) for it to work reliably, or at least
>>>>> that was the case for me on a 8750 QRD.
>>>>>
>>>>> Please check whether we can make that quirk apply based on ctrl
>>>>> version or so, so that we don't have to keep growing the compatible
>>>>> list in the driver.
>>>>>
>>>>
>>>> That would be a bizarre. When I added the quirk, I was told that it would affect
>>>> only SM8550 and SM8650 (this one I learned later). I'm not against applying the
>>>> quirk based on UFSHC version if the bug is carried forward, but that would be an
>>>> indication of bad design.
>>>
>>> Isn't 8750 capable of using MCQ now ? because this is the whole issue behind
>>> this UFSHCD_QUIRK_BROKEN_LSDBS_CAP, it's supposed to use MCQ by default... but
>>> we don't.
>>>
>>> Is there any news about that ? It's a clear regression against downstream, not
>>> having MCQ makes the UFS driver struggle to reach high bandwidth when the system
>>> is busy because we can't spread the load over all CPUs and we have only single
>>> queue to submit requests.
>>>
>>
>> There are hardware issues on SM8550 and SM8650(?) for the MCQ feature.
>> Apparently, Qcom carries the workaround in downstream, but I got tired of
>> pushing them to upstream the fix(es).
>>
>> Maybe Can Guo can share what is the latest update on this.
>>
>> - Mani
>>
>
> Hi Mani,
>
> I have already replied to konrad mail earlier in this thread.
>
> The LSDBS workaround is only applicable for SM8650 and SM8550.
> SM8750 and onwards doesn't need this WA anymore as it is fixed in HW.
Nitin, you're right. I was hitting another issue and adding that quirk
only randomly changed some timings for it to not manifest
Sorry for the confusion.
Konrad
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 0/5] Add UFS support for SM8750
2025-02-10 11:15 ` Nitin Rawat
@ 2025-02-10 15:33 ` neil.armstrong
0 siblings, 0 replies; 37+ messages in thread
From: neil.armstrong @ 2025-02-10 15:33 UTC (permalink / raw)
To: Nitin Rawat, Manivannan Sadhasivam, Konrad Dybcio
Cc: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Alim Akhtar, Avri Altman,
Bart Van Assche, Bjorn Andersson, Andy Gross, Konrad Dybcio,
Satya Durga Srinivasu Prabhala, Trilok Soni, linux-arm-msm,
linux-phy, devicetree, linux-kernel, linux-scsi, Manish Pandey
Hi,
On 10/02/2025 12:15, Nitin Rawat wrote:
>
>
> On 2/10/2025 3:09 PM, neil.armstrong@linaro.org wrote:
>> On 09/02/2025 16:21, Manivannan Sadhasivam wrote:
>>> On Fri, Feb 07, 2025 at 11:47:12PM +0100, Konrad Dybcio wrote:
>>>> On 13.01.2025 10:46 PM, Melody Olvera wrote:
>>>>> Add UFS support for SM8750 SoCs.
>>>>>
>>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>>> ---
>>>>> Nitin Rawat (5):
>>>>> dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY
>>>>> phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
>>>>> dt-bindings: ufs: qcom: Document the SM8750 UFS Controller
>>>>> arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
>>>>> arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards
>>>>
>>>> You still need the same workaround 8550/8650 have in the UFS driver
>>>> (UFSHCD_QUIRK_BROKEN_LSDBS_CAP) for it to work reliably, or at least
>>>> that was the case for me on a 8750 QRD.
>>>>
>>>> Please check whether we can make that quirk apply based on ctrl
>>>> version or so, so that we don't have to keep growing the compatible
>>>> list in the driver.
>>>>
>>>
>>> That would be a bizarre. When I added the quirk, I was told that it would affect
>>> only SM8550 and SM8650 (this one I learned later). I'm not against applying the
>>> quirk based on UFSHC version if the bug is carried forward, but that would be an
>>> indication of bad design.
>>
>> Isn't 8750 capable of using MCQ now ? because this is the whole issue behind
>> this UFSHCD_QUIRK_BROKEN_LSDBS_CAP, it's supposed to use MCQ by default... but
>> we don't.
>>
>> Is there any news about that ? It's a clear regression against downstream, not
>> having MCQ makes the UFS driver struggle to reach high bandwidth when the system
>> is busy because we can't spread the load over all CPUs and we have only single
>> queue to submit requests.
>
> Hi Neil,
>
> There is no relation b/w LSDBS_CAP Register and MCQ support.
> That registers just indicate when MCQ support is present on any SOC,
> whether Single queue mode is supported or not on that SOC.
>
> In SM8650 and SM86550, just the pored value of that register was incorrect which was fixed by WA but actually functionality was present and working fine.
>
> Pored value of that register has been fixed from SM8750 onwards.
Thanks for the explanation, but this doesn't answer about the state of MCQ
for SM8550, SM8650 and SM8750. I would've expected to have MCQ for SM8750
in the first patchset.
Neil
>
> Regards,
> Nitin
>
>>
>> Neil
>>
>>>
>>> - Mani
>>>
>>
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
2025-02-08 22:06 ` Dmitry Baryshkov
@ 2025-02-10 19:20 ` Konrad Dybcio
2025-02-14 6:50 ` Manivannan Sadhasivam
0 siblings, 1 reply; 37+ messages in thread
From: Konrad Dybcio @ 2025-02-10 19:20 UTC (permalink / raw)
To: Dmitry Baryshkov, Nitin Rawat
Cc: Melody Olvera, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Bjorn Andersson,
Andy Gross, Konrad Dybcio, Satya Durga Srinivasu Prabhala,
Trilok Soni, linux-arm-msm, linux-phy, devicetree, linux-kernel,
linux-scsi, Manish Pandey
On 8.02.2025 11:06 PM, Dmitry Baryshkov wrote:
> On Sun, Feb 09, 2025 at 12:47:56AM +0530, Nitin Rawat wrote:
>>
>>
>> On 1/14/2025 4:22 PM, Dmitry Baryshkov wrote:
>>> On Mon, Jan 13, 2025 at 01:46:27PM -0800, Melody Olvera wrote:
>>>> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>>>>
>>>> Add UFS host controller and PHY nodes for SM8750 SoC.
>>>>
>>>> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
>>>> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
>>>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>> ---
[...]
>>> Use OPP table instead
>>
>> Currently, OPP is not enabled in the device tree for any previous targets. I
>
> Excuse me? ufs_opp_table is present on SM8250, SM8550 and SDM845 (and
> QCS615). So this is not correct
>
>> plan to enable OPP in a separate patch at a later stage. This is because
>> there is an ongoing patch in the upstream that aims to enable multiple-level
>> clock scaling using OPP, which may introduce changes to the device tree
>> entries. To avoid extra efforts, I intend to enable OPP once that patch is
>> merged.
>
> Whatever changes are introduced, old DT must still continue to work.
> There is no reason to use legacy freq-table-hz if you can use OPP table.
>
>> Please let me know if you have any concerns.
Go ahead with the OPP table. freq-table-hz is ancient and doesn't describe
e.g. the required RPMh levels for core clock frequencies.
You should then drop required-opps from the UFS node.
>>>> +
>>>> + resets = <&gcc GCC_UFS_PHY_BCR>;
>>>> + reset-names = "rst";
>>>> +
>>>> +
>>>> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
>>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>>>> + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
>>>
>>> Shouldn't cpu-ufs be ACTIVE_ONLY?
>>
>> As per ufs driver implementation, Icc voting from ufs driver is removed as
>> part of low power mode (suspend or clock gating) and voted again in
>> resume/ungating path. Hence TAG_ALWAYS will have no power concern.
>> All previous targets have the same configuration.
>
> arch/arm64/boot/dts/qcom/qcs615.dtsi: &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
>
> It might be a mistake for that target though. Your explanation sounds
> fine to me.
Let's use QCOM_ICC_TAG_ACTIVE_ONLY for the CPU path to clear up confusion.
Toggling it from the driver makes sense for UFS-idling-while-CPUs-are-online
cases and accidentally also does what RPMh does internally in the other case.
Konrad
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
2025-02-10 19:20 ` Konrad Dybcio
@ 2025-02-14 6:50 ` Manivannan Sadhasivam
2025-02-21 19:55 ` Konrad Dybcio
0 siblings, 1 reply; 37+ messages in thread
From: Manivannan Sadhasivam @ 2025-02-14 6:50 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Dmitry Baryshkov, Nitin Rawat, Melody Olvera, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alim Akhtar, Avri Altman, Bart Van Assche,
Bjorn Andersson, Andy Gross, Konrad Dybcio,
Satya Durga Srinivasu Prabhala, Trilok Soni, linux-arm-msm,
linux-phy, devicetree, linux-kernel, linux-scsi, Manish Pandey
On Mon, Feb 10, 2025 at 08:20:27PM +0100, Konrad Dybcio wrote:
> On 8.02.2025 11:06 PM, Dmitry Baryshkov wrote:
> > On Sun, Feb 09, 2025 at 12:47:56AM +0530, Nitin Rawat wrote:
> >>
> >>
> >> On 1/14/2025 4:22 PM, Dmitry Baryshkov wrote:
> >>> On Mon, Jan 13, 2025 at 01:46:27PM -0800, Melody Olvera wrote:
> >>>> From: Nitin Rawat <quic_nitirawa@quicinc.com>
> >>>>
> >>>> Add UFS host controller and PHY nodes for SM8750 SoC.
> >>>>
> >>>> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
> >>>> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> >>>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> >>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> >>>> ---
>
> [...]
>
> >>> Use OPP table instead
> >>
> >> Currently, OPP is not enabled in the device tree for any previous targets. I
> >
> > Excuse me? ufs_opp_table is present on SM8250, SM8550 and SDM845 (and
> > QCS615). So this is not correct
> >
> >> plan to enable OPP in a separate patch at a later stage. This is because
> >> there is an ongoing patch in the upstream that aims to enable multiple-level
> >> clock scaling using OPP, which may introduce changes to the device tree
> >> entries. To avoid extra efforts, I intend to enable OPP once that patch is
> >> merged.
> >
> > Whatever changes are introduced, old DT must still continue to work.
> > There is no reason to use legacy freq-table-hz if you can use OPP table.
> >
> >> Please let me know if you have any concerns.
>
> Go ahead with the OPP table. freq-table-hz is ancient and doesn't describe
> e.g. the required RPMh levels for core clock frequencies.
>
> You should then drop required-opps from the UFS node.
>
> >>>> +
> >>>> + resets = <&gcc GCC_UFS_PHY_BCR>;
> >>>> + reset-names = "rst";
> >>>> +
> >>>> +
> >>>> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
> >>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> >>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> >>>> + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
> >>>
> >>> Shouldn't cpu-ufs be ACTIVE_ONLY?
> >>
> >> As per ufs driver implementation, Icc voting from ufs driver is removed as
> >> part of low power mode (suspend or clock gating) and voted again in
> >> resume/ungating path. Hence TAG_ALWAYS will have no power concern.
> >> All previous targets have the same configuration.
> >
> > arch/arm64/boot/dts/qcom/qcs615.dtsi: &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
> >
> > It might be a mistake for that target though. Your explanation sounds
> > fine to me.
>
> Let's use QCOM_ICC_TAG_ACTIVE_ONLY for the CPU path to clear up confusion.
>
> Toggling it from the driver makes sense for UFS-idling-while-CPUs-are-online
> cases and accidentally also does what RPMh does internally in the other case.
>
Shouldn't it be applied to config path of all peripherals then? If
QCOM_ICC_TAG_ACTIVE_ONLY translates to 'resource getting voted only if the CPUSS
is active', then the same constraint should apply to all peripherals, isn't it?
I'm not sure who is accessing the config path other than the CPUs.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
2025-02-14 6:50 ` Manivannan Sadhasivam
@ 2025-02-21 19:55 ` Konrad Dybcio
0 siblings, 0 replies; 37+ messages in thread
From: Konrad Dybcio @ 2025-02-21 19:55 UTC (permalink / raw)
To: Manivannan Sadhasivam, Konrad Dybcio
Cc: Dmitry Baryshkov, Nitin Rawat, Melody Olvera, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alim Akhtar, Avri Altman, Bart Van Assche,
Bjorn Andersson, Andy Gross, Konrad Dybcio,
Satya Durga Srinivasu Prabhala, Trilok Soni, linux-arm-msm,
linux-phy, devicetree, linux-kernel, linux-scsi, Manish Pandey
On 14.02.2025 7:50 AM, Manivannan Sadhasivam wrote:
> On Mon, Feb 10, 2025 at 08:20:27PM +0100, Konrad Dybcio wrote:
>> On 8.02.2025 11:06 PM, Dmitry Baryshkov wrote:
>>> On Sun, Feb 09, 2025 at 12:47:56AM +0530, Nitin Rawat wrote:
>>>>
>>>>
>>>> On 1/14/2025 4:22 PM, Dmitry Baryshkov wrote:
>>>>> On Mon, Jan 13, 2025 at 01:46:27PM -0800, Melody Olvera wrote:
>>>>>> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>>>>>>
>>>>>> Add UFS host controller and PHY nodes for SM8750 SoC.
>>>>>>
>>>>>> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
>>>>>> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
>>>>>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>>>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>>>> ---
>>
>> [...]
>>
>>>>> Use OPP table instead
>>>>
>>>> Currently, OPP is not enabled in the device tree for any previous targets. I
>>>
>>> Excuse me? ufs_opp_table is present on SM8250, SM8550 and SDM845 (and
>>> QCS615). So this is not correct
>>>
>>>> plan to enable OPP in a separate patch at a later stage. This is because
>>>> there is an ongoing patch in the upstream that aims to enable multiple-level
>>>> clock scaling using OPP, which may introduce changes to the device tree
>>>> entries. To avoid extra efforts, I intend to enable OPP once that patch is
>>>> merged.
>>>
>>> Whatever changes are introduced, old DT must still continue to work.
>>> There is no reason to use legacy freq-table-hz if you can use OPP table.
>>>
>>>> Please let me know if you have any concerns.
>>
>> Go ahead with the OPP table. freq-table-hz is ancient and doesn't describe
>> e.g. the required RPMh levels for core clock frequencies.
>>
>> You should then drop required-opps from the UFS node.
>>
>>>>>> +
>>>>>> + resets = <&gcc GCC_UFS_PHY_BCR>;
>>>>>> + reset-names = "rst";
>>>>>> +
>>>>>> +
>>>>>> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
>>>>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>>>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>>>>>> + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
>>>>>
>>>>> Shouldn't cpu-ufs be ACTIVE_ONLY?
>>>>
>>>> As per ufs driver implementation, Icc voting from ufs driver is removed as
>>>> part of low power mode (suspend or clock gating) and voted again in
>>>> resume/ungating path. Hence TAG_ALWAYS will have no power concern.
>>>> All previous targets have the same configuration.
>>>
>>> arch/arm64/boot/dts/qcom/qcs615.dtsi: &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
>>>
>>> It might be a mistake for that target though. Your explanation sounds
>>> fine to me.
>>
>> Let's use QCOM_ICC_TAG_ACTIVE_ONLY for the CPU path to clear up confusion.
>>
>> Toggling it from the driver makes sense for UFS-idling-while-CPUs-are-online
>> cases and accidentally also does what RPMh does internally in the other case.
>>
>
> Shouldn't it be applied to config path of all peripherals then? If
> QCOM_ICC_TAG_ACTIVE_ONLY translates to 'resource getting voted only if the CPUSS
> is active', then the same constraint should apply to all peripherals, isn't it?
Yes and lately we've been trying to catch that in review
Konrad
> I'm not sure who is accessing the config path other than the CPUs.
>>hopefully<, no one
Konrad
^ permalink raw reply [flat|nested] 37+ messages in thread
end of thread, other threads:[~2025-02-21 19:55 UTC | newest]
Thread overview: 37+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-01-13 21:46 [PATCH 0/5] Add UFS support for SM8750 Melody Olvera
2025-01-13 21:46 ` [PATCH 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY Melody Olvera
2025-01-18 14:44 ` Krzysztof Kozlowski
2025-01-13 21:46 ` [PATCH 2/5] phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750 Melody Olvera
2025-01-14 9:00 ` neil.armstrong
2025-01-14 10:49 ` Dmitry Baryshkov
[not found] ` <6873e397-dbc0-4c30-8c08-a65ee7cd6e01@quicinc.com>
2025-02-04 1:36 ` Dmitry Baryshkov
2025-02-05 11:41 ` Nitin Rawat
2025-02-05 11:33 ` Nitin Rawat
2025-02-05 11:44 ` Dmitry Baryshkov
2025-02-05 13:57 ` Nitin Rawat
2025-02-05 14:28 ` Dmitry Baryshkov
2025-02-07 9:14 ` Nitin Rawat
2025-01-13 21:46 ` [PATCH 3/5] dt-bindings: ufs: qcom: Document the SM8750 UFS Controller Melody Olvera
2025-01-18 14:45 ` Krzysztof Kozlowski
2025-01-13 21:46 ` [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC Melody Olvera
2025-01-14 10:52 ` Dmitry Baryshkov
2025-02-08 19:17 ` Nitin Rawat
2025-02-08 22:06 ` Dmitry Baryshkov
2025-02-10 19:20 ` Konrad Dybcio
2025-02-14 6:50 ` Manivannan Sadhasivam
2025-02-21 19:55 ` Konrad Dybcio
2025-01-18 15:28 ` Krzysztof Kozlowski
2025-01-27 10:23 ` Konrad Dybcio
2025-02-08 1:43 ` Konrad Dybcio
2025-01-13 21:46 ` [PATCH 5/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards Melody Olvera
2025-01-18 15:26 ` Krzysztof Kozlowski
2025-01-27 10:20 ` Konrad Dybcio
2025-02-07 22:47 ` [PATCH 0/5] Add UFS support for SM8750 Konrad Dybcio
2025-02-08 17:57 ` Nitin Rawat
2025-02-09 15:21 ` Manivannan Sadhasivam
2025-02-10 9:39 ` neil.armstrong
2025-02-10 10:13 ` Manivannan Sadhasivam
2025-02-10 11:08 ` Nitin Rawat
2025-02-10 15:21 ` Konrad Dybcio
2025-02-10 11:15 ` Nitin Rawat
2025-02-10 15:33 ` neil.armstrong
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