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([2a01:e0a:982:cbb0:8235:1ea0:1a75:c4d5]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390db110dfsm188164975e9.36.2025.02.10.07.33.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Feb 2025 07:33:27 -0800 (PST) Message-ID: <2d1ab1fe-6d98-4b54-910c-f371f708039d@linaro.org> Date: Mon, 10 Feb 2025 16:33:18 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH 0/5] Add UFS support for SM8750 To: Nitin Rawat , Manivannan Sadhasivam , Konrad Dybcio Cc: Melody Olvera , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Avri Altman , Bart Van Assche , Bjorn Andersson , Andy Gross , Konrad Dybcio , Satya Durga Srinivasu Prabhala , Trilok Soni , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Manish Pandey References: <20250113-sm8750_ufs_master-v1-0-b3774120eb8c@quicinc.com> <20250209152140.cyry6g7ltccxcmyj@thinkpad> <92e77d82-7c76-4cc4-8e7d-7b72b57ab416@quicinc.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <92e77d82-7c76-4cc4-8e7d-7b72b57ab416@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi, On 10/02/2025 12:15, Nitin Rawat wrote: > > > On 2/10/2025 3:09 PM, neil.armstrong@linaro.org wrote: >> On 09/02/2025 16:21, Manivannan Sadhasivam wrote: >>> On Fri, Feb 07, 2025 at 11:47:12PM +0100, Konrad Dybcio wrote: >>>> On 13.01.2025 10:46 PM, Melody Olvera wrote: >>>>> Add UFS support for SM8750 SoCs. >>>>> >>>>> Signed-off-by: Melody Olvera >>>>> --- >>>>> Nitin Rawat (5): >>>>>        dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY >>>>>        phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750 >>>>>        dt-bindings: ufs: qcom: Document the SM8750 UFS Controller >>>>>        arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC >>>>>        arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards >>>> >>>> You still need the same workaround 8550/8650 have in the UFS driver >>>> (UFSHCD_QUIRK_BROKEN_LSDBS_CAP) for it to work reliably, or at least >>>> that was the case for me on a 8750 QRD. >>>> >>>> Please check whether we can make that quirk apply based on ctrl >>>> version or so, so that we don't have to keep growing the compatible >>>> list in the driver. >>>> >>> >>> That would be a bizarre. When I added the quirk, I was told that it would affect >>> only SM8550 and SM8650 (this one I learned later). I'm not against applying the >>> quirk based on UFSHC version if the bug is carried forward, but that would be an >>> indication of bad design. >> >> Isn't 8750 capable of using MCQ now ? because this is the whole issue behind >> this UFSHCD_QUIRK_BROKEN_LSDBS_CAP, it's supposed to use MCQ by default... but >> we don't. >> >> Is there any news about that ? It's a clear regression against downstream, not >> having MCQ makes the UFS driver struggle to reach high bandwidth when the system >> is busy because we can't spread the load over all CPUs and we have only single >> queue to submit requests. > > Hi Neil, > > There is no relation b/w LSDBS_CAP Register and MCQ support. > That registers just indicate when MCQ support is present on any SOC, > whether Single queue mode is supported or not on that SOC. > > In SM8650 and SM86550, just the pored value of that register was incorrect which was fixed by WA but actually functionality was present and working fine. > > Pored value of that register has been fixed from SM8750 onwards. Thanks for the explanation, but this doesn't answer about the state of MCQ for SM8550, SM8650 and SM8750. I would've expected to have MCQ for SM8750 in the first patchset. Neil > > Regards, > Nitin > >> >> Neil >> >>> >>> - Mani >>> >> >