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([2600:8804:5716:d800::b712]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-6c8f5cf48besm3802412eaf.4.2026.09.17.13.24.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Sep 2026 13:24:07 -0700 (PDT) Message-ID: <2d1b80f2-53f6-4ed6-81bf-e35c0a9efb26@gmail.com> Date: Thu, 17 Sep 2026 15:24:05 -0500 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/3] iio: adc: add mt6397 PMIC AUXADC support To: Andy Shevchenko Cc: Jonathan Cameron , David Lechner , =?UTF-8?Q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Lee Jones , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, mfd@lists.linux.dev, Roman Vivchar , Luca Leonardo Scorcia References: <20260915-rbrue-suez-upstreaming-mt6397-auxadc-v1-0-d35d2ac3d6f0@gmail.com> Content-Language: en-US From: Ryan Brue In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 9/16/26 4:50 AM, Andy Shevchenko wrote: > On Tue, Sep 15, 2026 at 11:15:25PM -0500, Ryan Brue wrote: >> The MediaTek mt6397 PMIC has a 10-bit AUXADC that nothing in-tree can >> reach. On boards built around it that ADC is the only path to the battery: >> the SoC's AUXADC is wired to board thermistors, and the charger ICs these >> boards use have no ADC at all, so without it there is no pack voltage and >> no state of charge. > This doesn't explain why a brand new driver? Perhaps we have existing code that > may be updated to support this device? I considered adding mt6397 support to either mt6323-auxadc or mt6359-auxadc, and both had problems. Both mt6323-auxadc and mt6359-auxadc select channels through a request register (1 bit per channel), while mt6397 uses a 4-bit numeric field CHSEL in CON1 (10:7), and then pulses a START bit (CON1 bit 0). That was the biggest reason I made the new driver. For mt6323-auxadc, which is the closest I could find to the mt6397 (CON0..CON27), it has 13 more registers than the mt6397 (CON0..CON14). It uses CON22 for its request register, and reads the result value from the same register as the ready bit. We don't do that - the mt6397 has a factory calibrated value for each channel at 0x16 higher than the raw value. mt6323 also has a 1800 mV / 15 bit scale / resolution while we have 1200 mV / 10 bits. We also have some per-channel preparation that we have to do before the burst, that the mt6323 doesn't have to do. For mt6359-auxadc, it has a more generic framework for describing the AUXADC, but it assumes requests are channel-per-bit, and so we would have to basically ignore req_idx, req_mask, rdy_idx, and rdy_mask. We also have our own software sampling, which the vendor does too (Amazon Fire OS based on Linux 3.18). We'd have to have our own sampling callback to do it. I drafted two other versions of these patches adding mt6397 support to both of those drivers, but the differences meant I had to add a lot of extra boilerplate to each driver and to me it didn't make sense. In v2 I will add the justification to the cover letter and commits for why I chose a new driver. If you'd like me to instead send the exploratory patches I made adapting mt6323-auxadc or mt6359-auxadc, let me know. I'm fine if it ends up seeming like we should adapt one of the existing drivers, but I think the mechanism for controlling this AUXADC is unique and merits its own driver. Thanks again for the review, I am going through each one, and sorry for the delay. I'm rather new to kernel development. Best regards, Ryan