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Tue, 18 Nov 2025 16:31:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IE9aTyhe3QihjQoXig54L488EL6koYTGGg77scgmXT7/fKmTmUcFZujSMAGlA9C7R+urkHskw== X-Received: by 2002:a05:7022:20c:b0:11b:38b6:a95a with SMTP id a92af1059eb24-11b40fc416bmr9550096c88.11.1763512268863; Tue, 18 Nov 2025 16:31:08 -0800 (PST) Received: from [192.168.1.57] ([98.148.145.183]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11b0608861asm44526917c88.9.2025.11.18.16.31.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Nov 2025 16:31:08 -0800 (PST) Message-ID: <2d94f235-0ce2-427f-a73f-05603faa37c1@oss.qualcomm.com> Date: Tue, 18 Nov 2025 16:31:07 -0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 5/5] media: qcom: camss: vfe: Add support for VFE 1080 To: Bryan O'Donoghue , Hangxiang Ma , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, Jingyi Wang , Atiya Kailany References: <20251113-add-support-for-camss-on-kaanapali-v6-0-1e6038785a8e@oss.qualcomm.com> <20251113-add-support-for-camss-on-kaanapali-v6-5-1e6038785a8e@oss.qualcomm.com> Content-Language: en-US From: Vijay Kumar Tumati In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=a6Q9NESF c=1 sm=1 tr=0 ts=691d0fce cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=BiHMn5M11h/vNwziJwzFrg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=EszM8AH1TrcyCSHxVMoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: myGPMF5VhWGnhhZoqp2vn-YRyeSPHZw1 X-Proofpoint-ORIG-GUID: myGPMF5VhWGnhhZoqp2vn-YRyeSPHZw1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE5MDAwMiBTYWx0ZWRfX5X3bv6WN7CrT rPOQ+GWjTci3nij29f+2dox5oB1JU/D4FpJEInlziXW03q2fQrUz8mgrOj4Li3p6YuLfuNaUfq9 OsbEgVa6mmV1DjQEa/kmEV6Z38wTp9jazQo3D8FgQ4LxtHNj7lK3v5/HUXmajS3dYv07DBqIigp ztMjgwAU/Ijot81cFJ7S/0xAClhhUh8X62TxMa1rQZX5kYsdyOIBtdXKZQg7YIG+gd7Vfv6+YsM ix8WF8gDfBfYvl4NobmOus02wYWd75rNwU6WLToljySrIpv7At4E8AQKtmVd4sFvLG6VVPS5E65 4fr/4+a4fjq1YAOmumraRQtGqEq0ReENkaBQYrhOFmw1brVKR7bK5TuL1whGLtHxW/92Y9Vm1Gf K5vpU4iS9d9JrOFAERh+jHn/AHbmDg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-18_04,2025-11-18_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 adultscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511190002 On 11/18/2025 1:58 AM, Bryan O'Donoghue wrote: > On 14/11/2025 03:29, Hangxiang Ma wrote: >> Add Video Front End (VFE) version 1080 as found on the Kaanapali SoC. >> >> The FULL front end modules in Kaanapali camera subsystem are called TFEs >> (Thin Front End), however, retaining the name VFE at places to maintain >> consistency and avoid unnecessary code changes. >> >> This change limits the VFE output lines to 3 for now as constrained by >> the CAMSS driver framework. >> >> Kaanapali architecture requires for the REG_UPDATE and AUP_UPDATE to be >> issued after all of the CSID configuration has been done. Additionally, >> the number of AUP_UPDATEs should match the number of buffers enqueued to >> the write master while it's being enabled. >> >> Although the real time data from TFE goes through the RT_CAMNOC, we are >> required to enable both the camnoc_rt_axi and camnoc_nrt_axi clocks for >> the PDX_NOC, that follows both the RT and NRT NOCs in this architecture, >> to ensure that both of the latter are idle after reset. >> >> Co-developed-by: Atiya Kailany >> Signed-off-by: Atiya Kailany >> Signed-off-by: Hangxiang Ma >> --- >>   drivers/media/platform/qcom/camss/Makefile         |   1 + >>   drivers/media/platform/qcom/camss/camss-vfe-1080.c | 197 >> +++++++++++++++++++++ >>   drivers/media/platform/qcom/camss/camss-vfe.c      |  10 +- >>   drivers/media/platform/qcom/camss/camss-vfe.h      |   2 + >>   drivers/media/platform/qcom/camss/camss.c          | 143 >> +++++++++++++++ >>   5 files changed, 351 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/media/platform/qcom/camss/Makefile >> b/drivers/media/platform/qcom/camss/Makefile >> index 3a7ed4f5a004..dc41b0d6dc21 100644 >> --- a/drivers/media/platform/qcom/camss/Makefile >> +++ b/drivers/media/platform/qcom/camss/Makefile >> @@ -22,6 +22,7 @@ qcom-camss-objs += \ >>           camss-vfe-340.o \ >>           camss-vfe-480.o \ >>           camss-vfe-680.o \ >> +        camss-vfe-1080.o \ >>           camss-vfe-gen3.o \ >>           camss-vfe-gen1.o \ >>           camss-vfe.o \ >> diff --git a/drivers/media/platform/qcom/camss/camss-vfe-1080.c >> b/drivers/media/platform/qcom/camss/camss-vfe-1080.c >> new file mode 100644 >> index 000000000000..03938759c57b >> --- /dev/null >> +++ b/drivers/media/platform/qcom/camss/camss-vfe-1080.c >> @@ -0,0 +1,197 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * camss-vfe-1080.c >> + * >> + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v1080 >> + * >> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. >> + */ >> +#include >> +#include >> +#include >> + >> +#include "camss.h" >> +#include "camss-vfe.h" >> + >> +/* VFE-1080 Bus Register Base Addresses */ >> +#define BUS_REG_BASE                (vfe_is_lite(vfe) ? 0x800 : 0x1000) >> + >> +#define VFE_BUS_WM_CGC_OVERRIDE            (BUS_REG_BASE + 0x08) >> +#define        WM_CGC_OVERRIDE_ALL            (0x7FFFFFF) >> + >> +#define VFE_BUS_WM_TEST_BUS_CTRL        (BUS_REG_BASE + 0x128) >> + >> +#define VFE_BUS_WM_CFG(n)            (BUS_REG_BASE + 0x500 + (n) * >> 0x100) >> +#define        WM_CFG_EN                BIT(0) >> +#define        WM_VIR_FRM_EN                BIT(1) >> +#define        WM_CFG_MODE                BIT(16) >> +#define VFE_BUS_WM_IMAGE_ADDR(n)        (BUS_REG_BASE + 0x504 + (n) >> * 0x100) >> +#define VFE_BUS_WM_FRAME_INCR(n)        (BUS_REG_BASE + 0x508 + (n) >> * 0x100) >> +#define VFE_BUS_WM_IMAGE_CFG_0(n)        (BUS_REG_BASE + 0x50c + (n) >> * 0x100) >> +#define        WM_IMAGE_CFG_0_DEFAULT_WIDTH        (0xFFFF) >> +#define VFE_BUS_WM_IMAGE_CFG_2(n)        (BUS_REG_BASE + 0x514 + (n) >> * 0x100) >> +#define        WM_IMAGE_CFG_2_DEFAULT_STRIDE        (0xFFFF) >> +#define VFE_BUS_WM_PACKER_CFG(n)        (BUS_REG_BASE + 0x518 + (n) >> * 0x100) >> + >> +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n)    (BUS_REG_BASE + 0x530 >> + (n) * 0x100) >> +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n)    (BUS_REG_BASE + 0x534 >> + (n) * 0x100) >> + >> +/* VFE lite has no such registers */ >> +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n)        (BUS_REG_BASE + 0x538 >> + (n) * 0x100) >> +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n)        (BUS_REG_BASE + 0x53c >> + (n) * 0x100) >> + >> +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n)        (BUS_REG_BASE + 0x560 >> + (n) * 0x100) >> +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n)    (BUS_REG_BASE + >> 0x564 + (n) * 0x100) >> + >> +/* >> + * IFE write master client IDs >> + * >> + * VIDEO_FULL            0 >> + * VIDEO_DC4_Y            1 >> + * VIDEO_DC4_C            2 >> + * VIDEO_DC16_Y            3 >> + * VIDEO_DC16_C            4 >> + * DISPLAY_DS2_Y        5 >> + * DISPLAY_DS2_C        6 >> + * FD_Y                7 >> + * FD_C                8 >> + * PIXEL_RAW            9 >> + * STATS_AEC_BG            10 >> + * STATS_AEC_BHIST        11 >> + * STATS_TINTLESS_BG        12 >> + * STATS_AWB_BG            13 >> + * STATS_AWB_BFW        14 >> + * STATS_AF_BHIST        15 >> + * STATS_ALSC_BG        16 >> + * STATS_FLICKER_BAYERRS    17 >> + * STATS_TMC_BHIST        18 >> + * PDAF_0            19 >> + * PDAF_1            20 >> + * PDAF_2            21 >> + * PDAF_3            22 >> + * RDI0                23 >> + * RDI1                24 >> + * RDI2                25 >> + * RDI3                26 >> + * RDI4                27 >> + * >> + * IFE Lite write master client IDs >> + * >> + * RDI0            0 >> + * RDI1            1 >> + * RDI2            2 >> + * RDI3            3 >> + * GAMMA        4 >> + * STATES_BE        5 >> + */ >> +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n)) >> + >> +static void vfe_wm_start_1080(struct vfe_device *vfe, u8 wm, struct >> vfe_line *line) >> +{ >> +    struct v4l2_pix_format_mplane *pix = >> +        &line->video_out.active_fmt.fmt.pix_mp; >> + >> +    wm = RDI_WM(wm); >> + >> +    /* no clock gating at bus input */ >> +    writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); >> + >> +    writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); >> + >> +    writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> >> 8, >> +           vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); >> +    writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF), >> +           vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); >> +    writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE, >> +           vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); >> +    writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); >> + >> +    /* no dropped frames, one irq per frame */ >> +    if (!vfe_is_lite(vfe)) { >> +        writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); >> +        writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); >> +    } >> + >> +    writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); >> +    writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); >> + >> +    writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm)); >> +    writel(0xFFFFFFFF, vfe->base + >> VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm)); >> + >> +    writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm)); >> +} >> + >> +static void vfe_wm_stop_1080(struct vfe_device *vfe, u8 wm) >> +{ >> +    wm = RDI_WM(wm); >> +    writel(0, vfe->base + VFE_BUS_WM_CFG(wm)); >> +} >> + >> +static void vfe_wm_update_1080(struct vfe_device *vfe, u8 wm, u32 addr, >> +                   struct vfe_line *line) >> +{ >> +    wm = RDI_WM(wm); >> +    writel((addr >> 8) & 0xFFFFFFFF, vfe->base + >> VFE_BUS_WM_IMAGE_ADDR(wm)); > > What is the & 0xFFFFFFFF for ? > > u32 addr = 0x80008000; > > addr = addr >> 8; > > addr == 0x8000080; > > addr &= 0xFFFFFFFF; > > addr == 0x8000080; > Agreed. Redundant. >> + >> +    dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr); >> +} >> + >> +static void vfe_reg_update_1080(struct vfe_device *vfe, enum >> vfe_line_id line_id) >> +{ >> +    int port_id = line_id; >> + >> +    camss_reg_update(vfe->camss, vfe->id, port_id, false); >> +} >> + >> +static inline void vfe_reg_update_clear_1080(struct vfe_device *vfe, >> +                         enum vfe_line_id line_id) >> +{ >> +    int port_id = line_id; >> + >> +    camss_reg_update(vfe->camss, vfe->id, port_id, true); >> +} >> + >> +static const struct camss_video_ops vfe_video_ops_1080 = { >> +    .queue_buffer = vfe_queue_buffer_v2, >> +    .flush_buffers = vfe_flush_buffers, >> +}; >> + >> +static void vfe_subdev_init_1080(struct device *dev, struct >> vfe_device *vfe) >> +{ >> +    vfe->video_ops = vfe_video_ops_1080; >> +} >> + >> +static void vfe_global_reset_1080(struct vfe_device *vfe) >> +{ >> +    vfe_isr_reset_ack(vfe); >> +} >> + >> +static irqreturn_t vfe_isr_1080(int irq, void *dev) >> +{ >> +    /* nop */ >> +    return IRQ_HANDLED; >> +} >> + >> +static int vfe_halt_1080(struct vfe_device *vfe) >> +{ >> +    /* rely on vfe_disable_output() to stop the VFE */ >> +    return 0; >> +} >> + >> +const struct vfe_hw_ops vfe_ops_1080 = { >> +    .global_reset = vfe_global_reset_1080, >> +    .hw_version = vfe_hw_version, >> +    .isr = vfe_isr_1080, >> +    .pm_domain_off = vfe_pm_domain_off, >> +    .pm_domain_on = vfe_pm_domain_on, >> +    .reg_update = vfe_reg_update_1080, >> +    .reg_update_clear = vfe_reg_update_clear_1080, >> +    .subdev_init = vfe_subdev_init_1080, >> +    .vfe_disable = vfe_disable, >> +    .vfe_enable = vfe_enable_v2, >> +    .vfe_halt = vfe_halt_1080, >> +    .vfe_wm_start = vfe_wm_start_1080, >> +    .vfe_wm_stop = vfe_wm_stop_1080, >> +    .vfe_buf_done = vfe_buf_done, >> +    .vfe_wm_update = vfe_wm_update_1080, >> +}; >> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c >> b/drivers/media/platform/qcom/camss/camss-vfe.c >> index 2753c2bb6c04..0084a1a1e71d 100644 >> --- a/drivers/media/platform/qcom/camss/camss-vfe.c >> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c >> @@ -349,6 +349,7 @@ static u32 vfe_src_pad_code(struct vfe_line >> *line, u32 sink_code, >>       case CAMSS_845: >>       case CAMSS_8550: >>       case CAMSS_8775P: >> +    case CAMSS_KAANAPALI: >>       case CAMSS_X1E80100: >>           switch (sink_code) { >>           case MEDIA_BUS_FMT_YUYV8_1X16: >> @@ -521,7 +522,8 @@ int vfe_enable_output_v2(struct vfe_line *line) >>         spin_lock_irqsave(&vfe->output_lock, flags); >>   -    ops->reg_update_clear(vfe, line->id); >> +    if (ops->reg_update_clear) >> +        ops->reg_update_clear(vfe, line->id); >>         if (output->state > VFE_OUTPUT_RESERVED) { >>           dev_err(vfe->camss->dev, >> @@ -548,7 +550,10 @@ int vfe_enable_output_v2(struct vfe_line *line) >>           output->gen2.active_num++; >>           ops->vfe_wm_update(vfe, output->wm_idx[0], >>                      output->buf[i]->addr[0], line); >> -        ops->reg_update(vfe, line->id); >> + >> +        /* Deferring the reg update until after CSID config */ >> +        if (!vfe->camss->res->vfe_res[vfe->id].vfe.is_deferred) >> +            ops->reg_update(vfe, line->id); > > if (vfe->camss->res->vfe_res[vfe->id].vfe.is_deferred) >     continue; > > Instead of calling this "is_deferred" it should name the thing that is > deferred reg_update_is_deferred > > Is it really deferred or is it done elsewhere ? Deferred implies > something happens later and then you'd expect this flag to be cleared. > > But it's not cleared, this is a permenant logical change, not a deferral. > > Please come up with a better more precise name for this and make your > change the corner case not the default, logically. > Yes, we can change the name but fundamentally, this is the default expectation on KNP every time the stream is enabled. Probably, "reg_update_after_csid_config'. >>       } >>         spin_unlock_irqrestore(&vfe->output_lock, flags); >> @@ -1998,6 +2003,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) >>       case CAMSS_845: >>       case CAMSS_8550: >>       case CAMSS_8775P: >> +    case CAMSS_KAANAPALI: >>       case CAMSS_X1E80100: >>           ret = 16; >>           break; >> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h >> b/drivers/media/platform/qcom/camss/camss-vfe.h >> index 0300efdb1c46..47851362edd4 100644 >> --- a/drivers/media/platform/qcom/camss/camss-vfe.h >> +++ b/drivers/media/platform/qcom/camss/camss-vfe.h >> @@ -133,6 +133,7 @@ struct vfe_isr_ops { >>     struct vfe_subdev_resources { >>       bool is_lite; >> +    bool is_deferred; >>       u8 line_num; >>       bool has_pd; >>       char *pd_name; >> @@ -245,6 +246,7 @@ extern const struct vfe_hw_ops vfe_ops_170; >>   extern const struct vfe_hw_ops vfe_ops_340; >>   extern const struct vfe_hw_ops vfe_ops_480; >>   extern const struct vfe_hw_ops vfe_ops_680; >> +extern const struct vfe_hw_ops vfe_ops_1080; >>   extern const struct vfe_hw_ops vfe_ops_gen3; >>     int vfe_get(struct vfe_device *vfe); >> diff --git a/drivers/media/platform/qcom/camss/camss.c >> b/drivers/media/platform/qcom/camss/camss.c >> index 30e58aeea310..9b5350b9ff4e 100644 >> --- a/drivers/media/platform/qcom/camss/camss.c >> +++ b/drivers/media/platform/qcom/camss/camss.c >> @@ -217,6 +217,147 @@ static const struct camss_subdev_resources >> csid_res_kaanapali[] = { >>       } >>   }; >>   +/* In Kaanapali, CAMNOC requires all CAMNOC_RT_TFEX clocks >> + * to operate on any TFE Full. >> + */ >> +static const struct camss_subdev_resources vfe_res_kaanapali[] = { >> +    /* VFE0 - TFE Full */ >> +    { >> +        .regulators = {}, >> +        .clock = { "gcc_hf_axi", "vfe0_fast_ahb", "vfe0", >> +               "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2", >> +               "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, >> +        .clock_rate = { { 0 }, >> +                { 0 }, >> +                { 360280000, 480000000, 630000000, 716000000, >> +                  833000000 }, >> +                { 0 }, >> +                { 0 }, >> +                { 0 }, >> +                { 200000000, 300000000, 400000000, 480000000 }, >> +                { 0 }, >> +                { 0 } }, >> +        .reg = { "vfe0" }, >> +        .interrupt = { "vfe0" }, >> +        .vfe = { >> +            .line_num = 3, >> +            .is_lite = false, >> +            .is_deferred = true, >> +            .has_pd = true, >> +            .pd_name = "vfe0", >> +            .hw_ops = &vfe_ops_1080, >> +            .formats_rdi = &vfe_formats_rdi_845, >> +            .formats_pix = &vfe_formats_pix_845 >> +        } >> +    }, >> +    /* VFE1 - TFE Full */ >> +    { >> +        .regulators = {}, >> +        .clock = { "gcc_hf_axi", "vfe1_fast_ahb", "vfe1", >> +               "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2", >> +               "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, >> +        .clock_rate = { { 0 }, >> +                { 0 }, >> +                { 360280000, 480000000, 630000000, 716000000, >> +                  833000000 }, >> +                { 0 }, >> +                { 0 }, >> +                { 0 }, >> +                { 200000000, 300000000, 400000000, 480000000 }, >> +                { 0 }, >> +                { 0 } }, >> +        .reg = { "vfe1" }, >> +        .interrupt = { "vfe1" }, >> +        .vfe = { >> +            .line_num = 3, >> +            .is_lite = false, >> +            .is_deferred = true, >> +            .has_pd = true, >> +            .pd_name = "vfe1", >> +            .hw_ops = &vfe_ops_1080, >> +            .formats_rdi = &vfe_formats_rdi_845, >> +            .formats_pix = &vfe_formats_pix_845 >> +        } >> +    }, >> +    /* VFE2 - TFE Full */ >> +    { >> +        .regulators = {}, >> +        .clock = { "gcc_hf_axi", "vfe2_fast_ahb", "vfe2", >> +               "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2", >> +               "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, >> +        .clock_rate = { { 0 }, >> +                { 0 }, >> +                { 360280000, 480000000, 630000000, 716000000, >> +                  833000000 }, >> +                { 0 }, >> +                { 0 }, >> +                { 0 }, >> +                { 200000000, 300000000, 400000000, 480000000 }, >> +                { 0 }, >> +                { 0 } }, >> +        .reg = { "vfe2" }, >> +        .interrupt = { "vfe2" }, >> +        .vfe = { >> +            .line_num = 3, >> +            .is_lite = false, >> +            .is_deferred = true, >> +            .has_pd = true, >> +            .pd_name = "vfe2", >> +            .hw_ops = &vfe_ops_1080, >> +            .formats_rdi = &vfe_formats_rdi_845, >> +            .formats_pix = &vfe_formats_pix_845 >> +        } >> +    }, >> +    /* VFE3 - IFE Lite */ >> +    { >> +        .regulators = {}, >> +        .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite", >> +               "camnoc_rt_vfe_lite", "camnoc_rt_axi", >> +               "camnoc_nrt_axi", "qdss_debug_xo" }, >> +        .clock_rate = { { 0 }, >> +                { 0 }, >> +                { 266666667, 400000000, 480000000 }, >> +                { 0 }, >> +                { 200000000, 300000000, 400000000, 480000000 }, >> +                { 0 }, >> +                { 0 } }, >> +        .reg = { "vfe_lite0" }, >> +        .interrupt = { "vfe_lite0" }, >> +        .vfe = { >> +            .line_num = 4, >> +            .is_lite = true, >> +            .is_deferred = true, >> +            .hw_ops = &vfe_ops_1080, >> +            .formats_rdi = &vfe_formats_rdi_845, >> +            .formats_pix = &vfe_formats_pix_845 >> +        } >> +    }, >> +    /* VFE4 - IFE Lite */ >> +    { >> +        .regulators = {}, >> +        .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite", >> +               "camnoc_rt_vfe_lite", "camnoc_rt_axi", >> +               "camnoc_nrt_axi", "qdss_debug_xo" }, >> +        .clock_rate = { { 0 }, >> +                { 0 }, >> +                { 266666667, 400000000, 480000000 }, >> +                { 0 }, >> +                { 200000000, 300000000, 400000000, 480000000 }, >> +                { 0 }, >> +                { 0 } }, >> +        .reg = { "vfe_lite1" }, >> +        .interrupt = { "vfe_lite1" }, >> +        .vfe = { >> +            .line_num = 4, >> +            .is_lite = true, >> +            .is_deferred = true, >> +            .hw_ops = &vfe_ops_1080, >> +            .formats_rdi = &vfe_formats_rdi_845, >> +            .formats_pix = &vfe_formats_pix_845 >> +        } >> +    }, >> +}; >> + >>   static const struct resources_icc icc_res_kaanapali[] = { >>       { >>           .name = "ahb", >> @@ -4493,10 +4634,12 @@ static const struct camss_resources >> kaanapali_resources = { >>       .pd_name = "top", >>       .csiphy_res = csiphy_res_kaanapali, >>       .csid_res = csid_res_kaanapali, >> +    .vfe_res = vfe_res_kaanapali, >>       .icc_res = icc_res_kaanapali, >>       .icc_path_num = ARRAY_SIZE(icc_res_kaanapali), >>       .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali), >>       .csid_num = ARRAY_SIZE(csid_res_kaanapali), >> +    .vfe_num = ARRAY_SIZE(vfe_res_kaanapali), >>   }; >>     static const struct camss_resources msm8916_resources = { >> > Thanks, Vijay.