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([2a01:e0a:982:cbb0:7555:8187:c6f1:9c02]) by smtp.gmail.com with ESMTPSA id oq25-20020a170906cc9900b00a3cd41b3c19sm541532ejb.199.2024.02.15.05.33.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Feb 2024 05:33:08 -0800 (PST) Message-ID: <2df69499-4ffa-46a9-8e7f-041e87ad3034@linaro.org> Date: Thu, 15 Feb 2024 14:33:06 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH v2 2/6] dt-bindings: arm-smmu: Document SM8650 GPU SMMU Content-Language: en-US, fr To: Dmitry Baryshkov Cc: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev References: <20240215-topic-sm8650-gpu-v2-0-6be0b4bf2e09@linaro.org> <20240215-topic-sm8650-gpu-v2-2-6be0b4bf2e09@linaro.org> Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro Developer Services In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 15/02/2024 10:32, Dmitry Baryshkov wrote: > On Thu, 15 Feb 2024 at 11:29, Neil Armstrong wrote: >> >> On 15/02/2024 10:25, Dmitry Baryshkov wrote: >>> On Thu, 15 Feb 2024 at 11:20, Neil Armstrong wrote: >>>> >>>> Document the GPU SMMU found on the SM8650 platform. >>>> >>>> Signed-off-by: Neil Armstrong >>>> --- >>>> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 7 +++++-- >>>> 1 file changed, 5 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >>>> index a4042ae24770..3ad5c850f3bf 100644 >>>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >>>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >>>> @@ -93,6 +93,7 @@ properties: >>>> - qcom,sm8350-smmu-500 >>>> - qcom,sm8450-smmu-500 >>>> - qcom,sm8550-smmu-500 >>>> + - qcom,sm8650-smmu-500 >>>> - const: qcom,adreno-smmu >>>> - const: qcom,smmu-500 >>>> - const: arm,mmu-500 >>>> @@ -508,7 +509,10 @@ allOf: >>>> - if: >>>> properties: >>>> compatible: >>>> - const: qcom,sm8550-smmu-500 >>>> + contains: >>>> + enum: >>>> + - qcom,sm8550-smmu-500 >>>> + - qcom,sm8650-smmu-500 >>> >>> Doesn't this cause warnings for non-GPU SMMU on this platform? >> >> No because it doesn't add those to required, it simply allows clock the properties. > > Can we further constrain this branch so that it is applicable only to > the Adreno SMMUs (and enforce requirement)? And maybe constrain the > second if-branch so that it doesn't apply to the Adreno SMMUs? Indeed, it's done like that for the a6 gpu, I'll send a fix for that Neil > >> >>> >>>> then: >>>> properties: >>>> clock-names: >>>> @@ -544,7 +548,6 @@ allOf: >>>> - qcom,sdx65-smmu-500 >>>> - qcom,sm6350-smmu-500 >>>> - qcom,sm6375-smmu-500 >>>> - - qcom,sm8650-smmu-500 >>>> - qcom,x1e80100-smmu-500 >>>> then: >>>> properties: >>>> >>>> -- >>>> 2.34.1 >>>> >>> >>> >> > >