* [PATCH 1/4] dt-bindings: media: Add bindings for qcom,x1p42100-camss
2026-04-10 4:25 [PATCH 0/4] media: camss: add support for purwa platform Wenmeng Liu
@ 2026-04-10 4:25 ` Wenmeng Liu
2026-04-10 7:59 ` Bryan O'Donoghue
` (2 more replies)
2026-04-10 4:25 ` [PATCH 2/4] media: qcom: camss: add support for X1P42100 camss Wenmeng Liu
` (2 subsequent siblings)
3 siblings, 3 replies; 11+ messages in thread
From: Wenmeng Liu @ 2026-04-10 4:25 UTC (permalink / raw)
To: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, Wenmeng Liu
Add bindings for the Camera Subsystem for X1P42100.
The X1P42100 platform provides:
- 2 x CSIPHY
- 3 x TPG
- 3 x CSID
- 2 x CSID Lite
- 1 x IFE
- 2 x IFE Lite
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
.../bindings/media/qcom,x1p42100-camss.yaml | 424 +++++++++++++++++++++
1 file changed, 424 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..8bfa7e616c3b6b91adc8e21ebfbbe6fb579484f6
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml
@@ -0,0 +1,424 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,x1p42100-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm X1P42100 Camera Subsystem (CAMSS)
+
+maintainers:
+ - Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,x1p42100-camss
+
+ reg:
+ maxItems: 14
+
+ reg-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csid_wrapper
+ - const: csiphy0
+ - const: csiphy4
+ - const: csitpg0
+ - const: csitpg1
+ - const: csitpg2
+ - const: vfe0
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ '#address-cells':
+ const: 2
+
+ '#size-cells':
+ const: 2
+
+ ranges: true
+
+ clocks:
+ maxItems: 22
+
+ clock-names:
+ items:
+ - const: camnoc_nrt_axi
+ - const: camnoc_rt_axi
+ - const: core_ahb
+ - const: cpas_ahb
+ - const: cpas_fast_ahb
+ - const: cpas_vfe0
+ - const: cpas_vfe_lite
+ - const: cphy_rx_clk_src
+ - const: csid
+ - const: csid_csiphy_rx
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy4
+ - const: csiphy4_timer
+ - const: gcc_axi_hf
+ - const: gcc_axi_sf
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+
+ interrupts:
+ maxItems: 10
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy4
+ - const: vfe0
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ interconnects:
+ maxItems: 4
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_mnoc
+ - const: sf_mnoc
+ - const: sf_icp_mnoc
+
+ iommus:
+ oneOf:
+ - items:
+ - description: S1 HLOS IFE and IFE_LITE non-protected read
+ - description: S1 HLOS IFE and IFE_LITE non-protected write
+ - description: S1 HLOS SFE non-protected read
+ - description: S1 HLOS SFE non-protected write
+ - description: S1 HLOS CDM IFE non-protected
+ - description: Legacy slot 0 - do not use
+ - description: Legacy slot 1 - do not use
+ - description: Legacy slot 2 - do not use
+ - items:
+ - description: S1 HLOS IFE and IFE_LITE non-protected read
+ - description: S1 HLOS IFE and IFE_LITE non-protected write
+ - description: S1 HLOS SFE non-protected read
+ - description: S1 HLOS SFE non-protected write
+ - description: S1 HLOS CDM IFE non-protected
+
+ power-domains:
+ items:
+ - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: top
+
+ vdd-csiphy-0p8-supply:
+ description:
+ 0.8V supply to a PHY.
+
+ vdd-csiphy-1p2-supply:
+ description:
+ 1.2V supply to a PHY.
+
+ phys:
+ maxItems: 2
+
+ phy-names:
+ items:
+ - const: csiphy0
+ - const: csiphy4
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports. Supports either standard single sensor mode or
+ Qualcomm's combo mode with one sensor in 2x1 + 1x1 data-lane, clock-lane mode.
+
+ patternProperties:
+ "^port@[0-3]$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+
+ description:
+ Input port for receiving CSI data.
+
+ properties:
+ endpoint@0:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ description:
+ Endpoint for receiving a single sensor input (or first leg of combo).
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4 # Base max allows 4 (for D-PHY)
+
+ clock-lanes:
+ maxItems: 1
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ endpoint@1:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ description:
+ Endpoint for receiving the second leg of a combo sensor input.
+
+ properties:
+ data-lanes:
+ maxItems: 1
+
+ clock-lanes:
+ maxItems: 1
+
+ bus-type:
+ const: 4 # Combo is D-PHY specific
+
+ required:
+ - data-lanes
+
+ allOf:
+ # Case 1: Combo Mode (endpoint@1 is present)
+ # If endpoint@1 exists, we restrict endpoint@0 to 2 lanes (D-PHY split)
+ - if:
+ required:
+ - endpoint@1
+ then:
+ properties:
+ endpoint@0:
+ properties:
+ data-lanes:
+ minItems: 2
+ maxItems: 2
+ bus-type:
+ const: 4
+ endpoint@1:
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 1
+ bus-type:
+ const: 4
+
+ # Case 2: Single Mode (endpoint@1 is missing)
+ # We explicitly allow up to 4 lanes here to cover the D-PHY use case.
+ - if:
+ not:
+ required:
+ - endpoint@1
+ then:
+ properties:
+ endpoint@0:
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+patternProperties:
+ "^phy@[0-9a-f]+$":
+ $ref: /schemas/phy/qcom,x1e80100-csi2-phy.yaml
+ unevaluatedProperties: false
+
+ "^opp-table(-.*)?$":
+ type: object
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
+ #include <dt-bindings/clock/qcom,x1e80100-camcc.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ camss: isp@acb7000 {
+ compatible = "qcom,x1p42100-camss";
+
+ reg = <0 0x0acb7000 0 0x2000>,
+ <0 0x0acb9000 0 0x2000>,
+ <0 0x0acbb000 0 0x2000>,
+ <0 0x0acc6000 0 0x1000>,
+ <0 0x0acca000 0 0x1000>,
+ <0 0x0acb6000 0 0x1000>,
+ <0 0x0ace4000 0 0x1000>,
+ <0 0x0acec000 0 0x4000>,
+ <0 0x0acf6000 0 0x1000>,
+ <0 0x0acf7000 0 0x1000>,
+ <0 0x0acf8000 0 0x1000>,
+ <0 0x0ac62000 0 0x4000>,
+ <0 0x0acc7000 0 0x2000>,
+ <0 0x0accb000 0 0x2000>;
+
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csid_wrapper",
+ "csiphy0",
+ "csiphy4",
+ "csitpg0",
+ "csitpg1",
+ "csitpg2",
+ "vfe0",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
+ <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+
+ clock-names = "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "core_ahb",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe_lite",
+ "cphy_rx_clk_src",
+ "csid",
+ "csid_csiphy_rx",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy4",
+ "vfe0",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ interconnect-names = "ahb",
+ "hf_mnoc",
+ "sf_mnoc",
+ "sf_icp_mnoc";
+
+ iommus = <&apps_smmu 0x800 0x60>,
+ <&apps_smmu 0x820 0x60>,
+ <&apps_smmu 0x840 0x60>,
+ <&apps_smmu 0x860 0x60>,
+ <&apps_smmu 0x18a0 0x0>;
+
+ power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ power-domain-names = "ife0",
+ "top";
+
+ vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>;
+ vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ csiphy_ep0: endpoint {
+ data-lanes = <0 1>;
+ remote-endpoint = <&sensor_ep>;
+ };
+ };
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 1/4] dt-bindings: media: Add bindings for qcom,x1p42100-camss
2026-04-10 4:25 ` [PATCH 1/4] dt-bindings: media: Add bindings for qcom,x1p42100-camss Wenmeng Liu
@ 2026-04-10 7:59 ` Bryan O'Donoghue
2026-04-10 8:06 ` Bryan O'Donoghue
2026-04-10 11:36 ` Krzysztof Kozlowski
2 siblings, 0 replies; 11+ messages in thread
From: Bryan O'Donoghue @ 2026-04-10 7:59 UTC (permalink / raw)
To: Wenmeng Liu, Robert Foss, Todor Tomov, Vladimir Zapolskiy,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel
On 10/04/2026 05:25, Wenmeng Liu wrote:
> Add bindings for the Camera Subsystem for X1P42100.
>
> The X1P42100 platform provides:
> - 2 x CSIPHY
> - 3 x TPG
> - 3 x CSID
> - 2 x CSID Lite
> - 1 x IFE
> - 2 x IFE Lite
>
> Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
> ---
> .../bindings/media/qcom,x1p42100-camss.yaml | 424 +++++++++++++++++++++
> 1 file changed, 424 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..8bfa7e616c3b6b91adc8e21ebfbbe6fb579484f6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml
> @@ -0,0 +1,424 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,x1p42100-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm X1P42100 Camera Subsystem (CAMSS)
> +
> +maintainers:
> + - Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
> +
> +description:
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,x1p42100-camss
> +
> + reg:
> + maxItems: 14
> +
> + reg-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csid_wrapper
> + - const: csiphy0
> + - const: csiphy4
> + - const: csitpg0
> + - const: csitpg1
> + - const: csitpg2
> + - const: vfe0
> + - const: vfe_lite0
> + - const: vfe_lite1
> +
> + '#address-cells':
> + const: 2
> +
> + '#size-cells':
> + const: 2
> +
> + ranges: true
> +
> + clocks:
> + maxItems: 22
> +
> + clock-names:
> + items:
> + - const: camnoc_nrt_axi
> + - const: camnoc_rt_axi
> + - const: core_ahb
> + - const: cpas_ahb
> + - const: cpas_fast_ahb
> + - const: cpas_vfe0
> + - const: cpas_vfe_lite
> + - const: cphy_rx_clk_src
> + - const: csid
> + - const: csid_csiphy_rx
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy4
> + - const: csiphy4_timer
> + - const: gcc_axi_hf
> + - const: gcc_axi_sf
> + - const: vfe0
> + - const: vfe0_fast_ahb
> + - const: vfe_lite
> + - const: vfe_lite_ahb
> + - const: vfe_lite_cphy_rx
> + - const: vfe_lite_csid
> +
> + interrupts:
> + maxItems: 10
> +
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csiphy0
> + - const: csiphy4
> + - const: vfe0
> + - const: vfe_lite0
> + - const: vfe_lite1
> +
> + interconnects:
> + maxItems: 4
> +
> + interconnect-names:
> + items:
> + - const: ahb
> + - const: hf_mnoc
> + - const: sf_mnoc
> + - const: sf_icp_mnoc
> +
> + iommus:
> + oneOf:
> + - items:
> + - description: S1 HLOS IFE and IFE_LITE non-protected read
> + - description: S1 HLOS IFE and IFE_LITE non-protected write
> + - description: S1 HLOS SFE non-protected read
> + - description: S1 HLOS SFE non-protected write
> + - description: S1 HLOS CDM IFE non-protected
> + - description: Legacy slot 0 - do not use
> + - description: Legacy slot 1 - do not use
> + - description: Legacy slot 2 - do not use
> + - items:
> + - description: S1 HLOS IFE and IFE_LITE non-protected read
> + - description: S1 HLOS IFE and IFE_LITE non-protected write
> + - description: S1 HLOS SFE non-protected read
> + - description: S1 HLOS SFE non-protected write
> + - description: S1 HLOS CDM IFE non-protected
> +
> + power-domains:
> + items:
> + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
> +
> + power-domain-names:
> + items:
> + - const: ife0
> + - const: top
> +
> + vdd-csiphy-0p8-supply:
> + description:
> + 0.8V supply to a PHY.
> +
> + vdd-csiphy-1p2-supply:
> + description:
> + 1.2V supply to a PHY.
> +
> + phys:
> + maxItems: 2
> +
> + phy-names:
> + items:
> + - const: csiphy0
> + - const: csiphy4
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports. Supports either standard single sensor mode or
> + Qualcomm's combo mode with one sensor in 2x1 + 1x1 data-lane, clock-lane mode.
> +
> + patternProperties:
> + "^port@[0-3]$":
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> +
> + description:
> + Input port for receiving CSI data.
> +
> + properties:
> + endpoint@0:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + description:
> + Endpoint for receiving a single sensor input (or first leg of combo).
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4 # Base max allows 4 (for D-PHY)
> +
> + clock-lanes:
> + maxItems: 1
> +
> + bus-type:
> + enum:
> + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
> + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
> +
> + endpoint@1:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + description:
> + Endpoint for receiving the second leg of a combo sensor input.
> +
> + properties:
> + data-lanes:
> + maxItems: 1
> +
> + clock-lanes:
> + maxItems: 1
> +
> + bus-type:
> + const: 4 # Combo is D-PHY specific
> +
> + required:
> + - data-lanes
> +
> + allOf:
> + # Case 1: Combo Mode (endpoint@1 is present)
> + # If endpoint@1 exists, we restrict endpoint@0 to 2 lanes (D-PHY split)
> + - if:
> + required:
> + - endpoint@1
> + then:
> + properties:
> + endpoint@0:
> + properties:
> + data-lanes:
> + minItems: 2
> + maxItems: 2
> + bus-type:
> + const: 4
> + endpoint@1:
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 1
> + bus-type:
> + const: 4
> +
> + # Case 2: Single Mode (endpoint@1 is missing)
> + # We explicitly allow up to 4 lanes here to cover the D-PHY use case.
> + - if:
> + not:
> + required:
> + - endpoint@1
> + then:
> + properties:
> + endpoint@0:
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> +patternProperties:
> + "^phy@[0-9a-f]+$":
> + $ref: /schemas/phy/qcom,x1e80100-csi2-phy.yaml
> + unevaluatedProperties: false
> +
> + "^opp-table(-.*)?$":
> + type: object
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - interrupts
> + - interrupt-names
> + - interconnects
> + - interconnect-names
> + - iommus
> + - power-domains
> + - power-domain-names
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
> + #include <dt-bindings/clock/qcom,x1e80100-camcc.h>
> + #include <dt-bindings/interconnect/qcom,icc.h>
> + #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
> + #include <dt-bindings/phy/phy.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + camss: isp@acb7000 {
> + compatible = "qcom,x1p42100-camss";
> +
> + reg = <0 0x0acb7000 0 0x2000>,
> + <0 0x0acb9000 0 0x2000>,
> + <0 0x0acbb000 0 0x2000>,
> + <0 0x0acc6000 0 0x1000>,
> + <0 0x0acca000 0 0x1000>,
> + <0 0x0acb6000 0 0x1000>,
> + <0 0x0ace4000 0 0x1000>,
> + <0 0x0acec000 0 0x4000>,
> + <0 0x0acf6000 0 0x1000>,
> + <0 0x0acf7000 0 0x1000>,
> + <0 0x0acf8000 0 0x1000>,
> + <0 0x0ac62000 0 0x4000>,
Is this the full extent of the VFE ? It looks like not to me.
For each register block please make sure you cover the _entire_ range of
the block not just the RDI part of it.
> + <0 0x0acc7000 0 0x2000>,
> + <0 0x0accb000 0 0x2000>;
> +
> + reg-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csid_wrapper",
> + "csiphy0",
> + "csiphy4",
> + "csitpg0",
> + "csitpg1",
> + "csitpg2",
> + "vfe0",
> + "vfe_lite0",
> + "vfe_lite1";
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
> + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
> + <&camcc CAM_CC_CORE_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_0_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
> + <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
_SRC clocks are generally not necessary, is this one ?
> + <&camcc CAM_CC_CSID_CLK>,
> + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY4_CLK>,
> + <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&gcc GCC_CAMERA_SF_AXI_CLK>,
> + <&camcc CAM_CC_IFE_0_CLK>,
> + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CLK>,
> + <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
> +
> + clock-names = "camnoc_nrt_axi",
> + "camnoc_rt_axi",
> + "core_ahb",
> + "cpas_ahb",
> + "cpas_fast_ahb",
> + "cpas_vfe0",
> + "cpas_vfe_lite",
> + "cphy_rx_clk_src",
> + "csid",
> + "csid_csiphy_rx",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy4",
> + "csiphy4_timer",
> + "gcc_axi_hf",
> + "gcc_axi_sf",
> + "vfe0",
> + "vfe0_fast_ahb",
> + "vfe_lite",
> + "vfe_lite_ahb",
> + "vfe_lite_cphy_rx",
> + "vfe_lite_csid";
> +
> + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
> +
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy4",
> + "vfe0",
> + "vfe_lite0",
> + "vfe_lite1";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> +
> + interconnect-names = "ahb",
> + "hf_mnoc",
> + "sf_mnoc",
> + "sf_icp_mnoc";
> +
> + iommus = <&apps_smmu 0x800 0x60>,
> + <&apps_smmu 0x820 0x60>,
> + <&apps_smmu 0x840 0x60>,
> + <&apps_smmu 0x860 0x60>,
> + <&apps_smmu 0x18a0 0x0>;
Please define which IOMMUs these are - I'd like to make sure the top
level node maps the IFE IOMMUs and not the ICP IOMMUs - as ICP should be
its own sub/separate node.
> +
> + power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
> + <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + power-domain-names = "ife0",
> + "top";
> +
> + vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>;
> + vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + csiphy_ep0: endpoint {
> + data-lanes = <0 1>;
> + remote-endpoint = <&sensor_ep>;
> + };
> + };
> + };
> + };
> + };
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 1/4] dt-bindings: media: Add bindings for qcom,x1p42100-camss
2026-04-10 4:25 ` [PATCH 1/4] dt-bindings: media: Add bindings for qcom,x1p42100-camss Wenmeng Liu
2026-04-10 7:59 ` Bryan O'Donoghue
@ 2026-04-10 8:06 ` Bryan O'Donoghue
2026-04-10 11:36 ` Krzysztof Kozlowski
2 siblings, 0 replies; 11+ messages in thread
From: Bryan O'Donoghue @ 2026-04-10 8:06 UTC (permalink / raw)
To: Wenmeng Liu, Robert Foss, Todor Tomov, Vladimir Zapolskiy,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel
On 10/04/2026 05:25, Wenmeng Liu wrote:
> + vdd-csiphy-0p8-supply:
> + description:
> + 0.8V supply to a PHY.
> +
> + vdd-csiphy-1p2-supply:
> + description:
> + 1.2V supply to a PHY.
> +
> + phys:
> + maxItems: 2
> +
> + phy-names:
> + items:
> + - const: csiphy0
> + - const: csiphy4
> +
So if we still can't agree to get phys = in in the next kernel cycle,
then this scheme is acceptable but with the huge caveat that one
power-rail for each PHY is known to be wrong.
And I absolutely hate to continue to knowingly do the wrong thing...
---
bod
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/4] dt-bindings: media: Add bindings for qcom,x1p42100-camss
2026-04-10 4:25 ` [PATCH 1/4] dt-bindings: media: Add bindings for qcom,x1p42100-camss Wenmeng Liu
2026-04-10 7:59 ` Bryan O'Donoghue
2026-04-10 8:06 ` Bryan O'Donoghue
@ 2026-04-10 11:36 ` Krzysztof Kozlowski
2 siblings, 0 replies; 11+ messages in thread
From: Krzysztof Kozlowski @ 2026-04-10 11:36 UTC (permalink / raw)
To: Wenmeng Liu
Cc: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
linux-media, linux-arm-msm, devicetree, linux-kernel
On Fri, Apr 10, 2026 at 12:25:31PM +0800, Wenmeng Liu wrote:
> Add bindings for the Camera Subsystem for X1P42100.
>
A nit, subject: drop second/last, redundant "bindings for". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.17-rc3/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
Please use subject prefixes matching the subsystem. You can get them for
example with 'git log --oneline -- DIRECTORY_OR_FILE' on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
> The X1P42100 platform provides:
> - 2 x CSIPHY
> - 3 x TPG
> - 3 x CSID
> - 2 x CSID Lite
> - 1 x IFE
> - 2 x IFE Lite
>
> Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
> ---
> .../bindings/media/qcom,x1p42100-camss.yaml | 424 +++++++++++++++++++++
> 1 file changed, 424 insertions(+)
>
You have ~20 prerequisities and some are even DTS patches, so either you
organized this wrong or patches are wrong. They cannot depend on DTS.
Probably this does not affect the binding, but it is not really
maintainers task to figure that out. You really should make it obvious
and easy for the community to review.
> diff --git a/Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..8bfa7e616c3b6b91adc8e21ebfbbe6fb579484f6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml
> @@ -0,0 +1,424 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,x1p42100-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm X1P42100 Camera Subsystem (CAMSS)
> +
> +maintainers:
> + - Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
> +
> +description:
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,x1p42100-camss
> +
> + reg:
> + maxItems: 14
> +
> + reg-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csid_wrapper
> + - const: csiphy0
> + - const: csiphy4
> + - const: csitpg0
> + - const: csitpg1
> + - const: csitpg2
> + - const: vfe0
> + - const: vfe_lite0
> + - const: vfe_lite1
> +
> + '#address-cells':
> + const: 2
> +
> + '#size-cells':
> + const: 2
> +
> + ranges: true
> +
> + clocks:
> + maxItems: 22
> +
> + clock-names:
> + items:
> + - const: camnoc_nrt_axi
> + - const: camnoc_rt_axi
> + - const: core_ahb
> + - const: cpas_ahb
> + - const: cpas_fast_ahb
> + - const: cpas_vfe0
> + - const: cpas_vfe_lite
> + - const: cphy_rx_clk_src
> + - const: csid
> + - const: csid_csiphy_rx
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy4
> + - const: csiphy4_timer
> + - const: gcc_axi_hf
> + - const: gcc_axi_sf
> + - const: vfe0
> + - const: vfe0_fast_ahb
> + - const: vfe_lite
> + - const: vfe_lite_ahb
> + - const: vfe_lite_cphy_rx
> + - const: vfe_lite_csid
> +
> + interrupts:
> + maxItems: 10
> +
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csiphy0
> + - const: csiphy4
> + - const: vfe0
> + - const: vfe_lite0
> + - const: vfe_lite1
> +
> + interconnects:
> + maxItems: 4
> +
> + interconnect-names:
> + items:
> + - const: ahb
> + - const: hf_mnoc
> + - const: sf_mnoc
> + - const: sf_icp_mnoc
> +
> + iommus:
> + oneOf:
> + - items:
> + - description: S1 HLOS IFE and IFE_LITE non-protected read
> + - description: S1 HLOS IFE and IFE_LITE non-protected write
> + - description: S1 HLOS SFE non-protected read
> + - description: S1 HLOS SFE non-protected write
> + - description: S1 HLOS CDM IFE non-protected
> + - description: Legacy slot 0 - do not use
> + - description: Legacy slot 1 - do not use
> + - description: Legacy slot 2 - do not use
> + - items:
> + - description: S1 HLOS IFE and IFE_LITE non-protected read
> + - description: S1 HLOS IFE and IFE_LITE non-protected write
> + - description: S1 HLOS SFE non-protected read
> + - description: S1 HLOS SFE non-protected write
> + - description: S1 HLOS CDM IFE non-protected
> +
> + power-domains:
> + items:
> + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
> +
> + power-domain-names:
> + items:
> + - const: ife0
> + - const: top
> +
> + vdd-csiphy-0p8-supply:
> + description:
> + 0.8V supply to a PHY.
> +
> + vdd-csiphy-1p2-supply:
> + description:
> + 1.2V supply to a PHY.
Properties of phys.
> +
> + phys:
> + maxItems: 2
> +
> + phy-names:
> + items:
> + - const: csiphy0
> + - const: csiphy4
If phys are listed here, why they are also child nodes? Drop above phys,
unless you want to say that phys should not be children of camss?
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports. Supports either standard single sensor mode or
> + Qualcomm's combo mode with one sensor in 2x1 + 1x1 data-lane, clock-lane mode.
> +
> + patternProperties:
> + "^port@[0-3]$":
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> +
> + description:
> + Input port for receiving CSI data.
> +
> + properties:
> + endpoint@0:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + description:
> + Endpoint for receiving a single sensor input (or first leg of combo).
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4 # Base max allows 4 (for D-PHY)
> +
> + clock-lanes:
> + maxItems: 1
> +
> + bus-type:
> + enum:
> + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
> + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
> +
> + endpoint@1:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + description:
> + Endpoint for receiving the second leg of a combo sensor input.
> +
> + properties:
> + data-lanes:
> + maxItems: 1
> +
> + clock-lanes:
> + maxItems: 1
> +
> + bus-type:
> + const: 4 # Combo is D-PHY specific
> +
> + required:
> + - data-lanes
> +
> + allOf:
> + # Case 1: Combo Mode (endpoint@1 is present)
> + # If endpoint@1 exists, we restrict endpoint@0 to 2 lanes (D-PHY split)
> + - if:
> + required:
> + - endpoint@1
> + then:
> + properties:
> + endpoint@0:
> + properties:
> + data-lanes:
> + minItems: 2
> + maxItems: 2
> + bus-type:
> + const: 4
> + endpoint@1:
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 1
> + bus-type:
> + const: 4
> +
> + # Case 2: Single Mode (endpoint@1 is missing)
> + # We explicitly allow up to 4 lanes here to cover the D-PHY use case.
> + - if:
> + not:
> + required:
> + - endpoint@1
> + then:
> + properties:
> + endpoint@0:
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> +patternProperties:
> + "^phy@[0-9a-f]+$":
> + $ref: /schemas/phy/qcom,x1e80100-csi2-phy.yaml
> + unevaluatedProperties: false
> +
> + "^opp-table(-.*)?$":
Why multiple opp-tables?
> + type: object
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - interrupts
> + - interrupt-names
> + - interconnects
> + - interconnect-names
> + - iommus
> + - power-domains
> + - power-domain-names
> + - ports
> +
...
> + power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
> + <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + power-domain-names = "ife0",
> + "top";
> +
> + vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>;
> + vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + csiphy_ep0: endpoint {
> + data-lanes = <0 1>;
> + remote-endpoint = <&sensor_ep>;
> + };
> + };
> + };
Incomplete, please add children.
> + };
> + };
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/4] media: qcom: camss: add support for X1P42100 camss
2026-04-10 4:25 [PATCH 0/4] media: camss: add support for purwa platform Wenmeng Liu
2026-04-10 4:25 ` [PATCH 1/4] dt-bindings: media: Add bindings for qcom,x1p42100-camss Wenmeng Liu
@ 2026-04-10 4:25 ` Wenmeng Liu
2026-04-10 4:25 ` [PATCH 3/4] arm64: dts: qcom: purwa: Add camss node Wenmeng Liu
2026-04-10 4:25 ` [PATCH 4/4] arm64: dts: qcom: purwa-iot-evk: " Wenmeng Liu
3 siblings, 0 replies; 11+ messages in thread
From: Wenmeng Liu @ 2026-04-10 4:25 UTC (permalink / raw)
To: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, Wenmeng Liu
The Purwa camera subsystem is a cut-down variant of the Hamoa CAMSS.
Compared to Hamoa, Purwa provides only two CSIPHY instances and does
not include the VFE1.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 2 +
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
drivers/media/platform/qcom/camss/camss.c | 109 +++++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
4 files changed, 114 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index 4154832745525972a663809c947a9e9aeca9f944..d37f71de0f42c394b0918a22de2a18836cbfec75 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -1020,6 +1020,7 @@ static bool csiphy_is_gen2(u32 version)
case CAMSS_8650:
case CAMSS_8775P:
case CAMSS_X1E80100:
+ case CAMSS_X1P42100:
ret = true;
break;
}
@@ -1115,6 +1116,7 @@ static int csiphy_init(struct csiphy_device *csiphy)
regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
break;
case CAMSS_X1E80100:
+ case CAMSS_X1P42100:
regs->lane_regs = &lane_regs_x1e80100[0];
regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
regs->offset = 0x1000;
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 5baf0e3d4bc461df28d8dcf97a98dec04fa17ceb..b48dfad5a8a73f81254086e5fc8f5bbc3a45aef3 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -353,6 +353,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_8650:
case CAMSS_8775P:
case CAMSS_X1E80100:
+ case CAMSS_X1P42100:
switch (sink_code) {
case MEDIA_BUS_FMT_YUYV8_1X16:
{
@@ -2012,6 +2013,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
case CAMSS_8650:
case CAMSS_8775P:
case CAMSS_X1E80100:
+ case CAMSS_X1P42100:
ret = 16;
break;
default:
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 3b092560b5df54513a5d0253dded1527769fcfbe..d2221f968251fc2c1ab7996ff54b087667a8108c 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -4158,6 +4158,98 @@ static const struct resources_wrapper csid_wrapper_res_x1e80100 = {
.reg = "csid_wrapper",
};
+static const struct camss_subdev_resources csiphy_res_x1p42100[] = {
+ /* CSIPHY0 */
+ {
+ .csiphy = {
+ .id = 0,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ },
+ },
+ /* CSIPHY4 */
+ {
+ .csiphy = {
+ .id = 4,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ },
+ },
+};
+
+static const struct camss_subdev_resources vfe_res_x1p42100[] = {
+ /* IFE0 */
+ {
+ .regulators = {},
+ .clock = {"camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb",
+ "cpas_fast_ahb", "cpas_vfe0", "vfe0_fast_ahb",
+ "vfe0" },
+ .clock_rate = { { 400000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 345600000, 432000000, 594000000, 675000000,
+ 727000000 }, },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 4,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_680,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ },
+ },
+ /* IFE_LITE_0 */
+ {
+ .regulators = {},
+ .clock = { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb",
+ "vfe_lite_ahb", "cpas_vfe_lite", "vfe_lite",
+ "vfe_lite_csid" },
+ .clock_rate = { { 400000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 266666667, 400000000, 480000000 }, },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .is_lite = true,
+ .line_num = 4,
+ .hw_ops = &vfe_ops_680,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ },
+ },
+ /* IFE_LITE_1 */
+ {
+ .regulators = {},
+ .clock = { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb",
+ "vfe_lite_ahb", "cpas_vfe_lite", "vfe_lite",
+ "vfe_lite_csid" },
+ .clock_rate = { { 400000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 266666667, 400000000, 480000000 }, },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .is_lite = true,
+ .line_num = 4,
+ .hw_ops = &vfe_ops_680,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ },
+ },
+};
+
/*
* camss_add_clock_margin - Add margin to clock frequency rate
* @rate: Clock frequency rate
@@ -5340,6 +5432,22 @@ static const struct camss_resources x1e80100_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_x1e80100),
};
+static const struct camss_resources x1p42100_resources = {
+ .version = CAMSS_X1P42100,
+ .pd_name = "top",
+ .csiphy_res = csiphy_res_x1p42100,
+ .tpg_res = tpg_res_x1e80100,
+ .csid_res = csid_res_x1e80100,
+ .vfe_res = vfe_res_x1p42100,
+ .csid_wrapper_res = &csid_wrapper_res_x1e80100,
+ .icc_res = icc_res_x1e80100,
+ .icc_path_num = ARRAY_SIZE(icc_res_x1e80100),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_x1p42100),
+ .tpg_num = ARRAY_SIZE(tpg_res_x1e80100),
+ .csid_num = ARRAY_SIZE(csid_res_x1e80100),
+ .vfe_num = ARRAY_SIZE(vfe_res_x1p42100),
+};
+
static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
{ .compatible = "qcom,msm8939-camss", .data = &msm8939_resources },
@@ -5358,6 +5466,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
{ .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
+ { .compatible = "qcom,x1p42100-camss", .data = &x1p42100_resources },
{ }
};
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 24ec3ad7990e7c582b06a2c112361128b2358630..c1374033f0b2036458ae6fe31034f183d3041a09 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -94,6 +94,7 @@ enum camss_version {
CAMSS_8650,
CAMSS_8775P,
CAMSS_X1E80100,
+ CAMSS_X1P42100,
};
enum icc_count {
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 3/4] arm64: dts: qcom: purwa: Add camss node
2026-04-10 4:25 [PATCH 0/4] media: camss: add support for purwa platform Wenmeng Liu
2026-04-10 4:25 ` [PATCH 1/4] dt-bindings: media: Add bindings for qcom,x1p42100-camss Wenmeng Liu
2026-04-10 4:25 ` [PATCH 2/4] media: qcom: camss: add support for X1P42100 camss Wenmeng Liu
@ 2026-04-10 4:25 ` Wenmeng Liu
2026-04-10 4:25 ` [PATCH 4/4] arm64: dts: qcom: purwa-iot-evk: " Wenmeng Liu
3 siblings, 0 replies; 11+ messages in thread
From: Wenmeng Liu @ 2026-04-10 4:25 UTC (permalink / raw)
To: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, Wenmeng Liu
Add node for the X1P42100 camera subsystem.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/purwa.dtsi | 158 ++++++++++++++++++++++++++++++++++++
1 file changed, 158 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi
index ea65b8448836ead83f837e973ed536e8ea0ed8ef..ff7b0dd781e9fdea2cec5a918772e4b2ff6f53a7 100644
--- a/arch/arm64/boot/dts/qcom/purwa.dtsi
+++ b/arch/arm64/boot/dts/qcom/purwa.dtsi
@@ -19,6 +19,8 @@
/delete-node/ &cpu_pd9;
/delete-node/ &cpu_pd10;
/delete-node/ &cpu_pd11;
+/delete-node/ &csiphy1;
+/delete-node/ &csiphy2;
/delete-node/ &gpu_opp_table;
/delete-node/ &gpu_speed_bin;
/delete-node/ &pcie3_phy;
@@ -38,6 +40,162 @@
/delete-node/ &thermal_gpuss_6;
/delete-node/ &thermal_gpuss_7;
+&camss {
+ compatible = "qcom,x1p42100-camss";
+
+ reg = <0 0x0acb7000 0 0x2000>,
+ <0 0x0acb9000 0 0x2000>,
+ <0 0x0acbb000 0 0x2000>,
+ <0 0x0acc6000 0 0x1000>,
+ <0 0x0acca000 0 0x1000>,
+ <0 0x0acb6000 0 0x1000>,
+ <0 0x0ace4000 0 0x1000>,
+ <0 0x0acec000 0 0x4000>,
+ <0 0x0acf6000 0 0x1000>,
+ <0 0x0acf7000 0 0x1000>,
+ <0 0x0acf8000 0 0x1000>,
+ <0 0x0ac62000 0 0x4000>,
+ <0 0x0acc7000 0 0x2000>,
+ <0 0x0accb000 0 0x2000>;
+
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csid_wrapper",
+ "csiphy0",
+ "csiphy4",
+ "csitpg0",
+ "csitpg1",
+ "csitpg2",
+ "vfe0",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy4",
+ "vfe0",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
+ <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+
+ clock-names = "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "core_ahb",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe_lite",
+ "cphy_rx_clk_src",
+ "csid",
+ "csid_csiphy_rx",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc",
+ "sf_mnoc",
+ "sf_icp_mnoc";
+
+ iommus = <&apps_smmu 0x800 0x60>,
+ <&apps_smmu 0x860 0x60>,
+ <&apps_smmu 0x1860 0x60>,
+ <&apps_smmu 0x18e0 0x00>,
+ <&apps_smmu 0x19a0 0x20>;
+
+ power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "top";
+
+ phys = <&csiphy0 PHY_TYPE_DPHY>,
+ <&csiphy4 PHY_TYPE_DPHY>;
+ phy-names = "csiphy0",
+ "csiphy4";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ camss_csiphy0_inep0: endpoint@0 {
+ reg = <0>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ camss_csiphy4_inep0: endpoint@0 {
+ reg = <0>;
+ };
+ };
+ };
+};
+
&camcc {
compatible = "qcom,x1p42100-camcc";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 4/4] arm64: dts: qcom: purwa-iot-evk: Add camss node
2026-04-10 4:25 [PATCH 0/4] media: camss: add support for purwa platform Wenmeng Liu
` (2 preceding siblings ...)
2026-04-10 4:25 ` [PATCH 3/4] arm64: dts: qcom: purwa: Add camss node Wenmeng Liu
@ 2026-04-10 4:25 ` Wenmeng Liu
2026-04-10 8:16 ` Bryan O'Donoghue
3 siblings, 1 reply; 11+ messages in thread
From: Wenmeng Liu @ 2026-04-10 4:25 UTC (permalink / raw)
To: Robert Foss, Todor Tomov, Bryan O'Donoghue,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, Wenmeng Liu
nable camss node for purwa iot evk board camss tpg support.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/purwa-iot-evk.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts
index ad503beec1d3d8c671d3564942a74c484de762d0..eef03f1eb2a950c06294159be3f97169fb487265 100644
--- a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts
+++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts
@@ -734,6 +734,10 @@ retimer_ss2_con_sbu_out: endpoint {
};
};
+&camss {
+ status = "okay";
+};
+
&i2c3 {
clock-frequency = <400000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 4/4] arm64: dts: qcom: purwa-iot-evk: Add camss node
2026-04-10 4:25 ` [PATCH 4/4] arm64: dts: qcom: purwa-iot-evk: " Wenmeng Liu
@ 2026-04-10 8:16 ` Bryan O'Donoghue
2026-04-10 8:38 ` Wenmeng Liu
0 siblings, 1 reply; 11+ messages in thread
From: Bryan O'Donoghue @ 2026-04-10 8:16 UTC (permalink / raw)
To: Wenmeng Liu, Robert Foss, Todor Tomov, Vladimir Zapolskiy,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel
On 10/04/2026 05:25, Wenmeng Liu wrote:
> nable camss node for purwa iot evk board camss tpg support.
>
> Signed-off-by: Wenmeng Liu<wenmeng.liu@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/purwa-iot-evk.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts
> index ad503beec1d3d8c671d3564942a74c484de762d0..eef03f1eb2a950c06294159be3f97169fb487265 100644
> --- a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts
> +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts
> @@ -734,6 +734,10 @@ retimer_ss2_con_sbu_out: endpoint {
> };
> };
>
> +&camss {
> + status = "okay";
> +};
Hmm.
I don't agree with this. Enabling the CAMSS node with just the TPG is of
very low value to an end-user and doesn't "prove out" the CSIPHY, TPG
and RDI path - which is the minimum entry point in upstream right now.
I don't support less than a sensor at minimum.
You guys must have a sensor you've used with this board ?
---
bod
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 4/4] arm64: dts: qcom: purwa-iot-evk: Add camss node
2026-04-10 8:16 ` Bryan O'Donoghue
@ 2026-04-10 8:38 ` Wenmeng Liu
2026-04-10 13:43 ` Krzysztof Kozlowski
0 siblings, 1 reply; 11+ messages in thread
From: Wenmeng Liu @ 2026-04-10 8:38 UTC (permalink / raw)
To: Bryan O'Donoghue, Robert Foss, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel
Hi Bryan,
On 4/10/2026 4:16 PM, Bryan O'Donoghue wrote:
> On 10/04/2026 05:25, Wenmeng Liu wrote:
>> nable camss node for purwa iot evk board camss tpg support.
>>
>> Signed-off-by: Wenmeng Liu<wenmeng.liu@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/purwa-iot-evk.dts | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/
>> boot/dts/qcom/purwa-iot-evk.dts
>> index
>> ad503beec1d3d8c671d3564942a74c484de762d0..eef03f1eb2a950c06294159be3f97169fb487265 100644
>> --- a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts
>> +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts
>> @@ -734,6 +734,10 @@ retimer_ss2_con_sbu_out: endpoint {
>> };
>> };
>> +&camss {
>> + status = "okay";
>> +};
>
> Hmm.
>
> I don't agree with this. Enabling the CAMSS node with just the TPG is of
> very low value to an end-user and doesn't "prove out" the CSIPHY, TPG
> and RDI path - which is the minimum entry point in upstream right now.
>
> I don't support less than a sensor at minimum.
>
> You guys must have a sensor you've used with this board ?
>
Yes we have, but both not upstreamed sensor, we currently have no plans
for sensor upstream, perhaps this work will be carried out later.
And ack comments on the previous patch.
Thanks,
Wenmeng
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 4/4] arm64: dts: qcom: purwa-iot-evk: Add camss node
2026-04-10 8:38 ` Wenmeng Liu
@ 2026-04-10 13:43 ` Krzysztof Kozlowski
0 siblings, 0 replies; 11+ messages in thread
From: Krzysztof Kozlowski @ 2026-04-10 13:43 UTC (permalink / raw)
To: Wenmeng Liu, Bryan O'Donoghue, Robert Foss, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel
On 10/04/2026 10:38, Wenmeng Liu wrote:
>>> +&camss {
>>> + status = "okay";
>>> +};
>>
>> Hmm.
>>
>> I don't agree with this. Enabling the CAMSS node with just the TPG is of
>> very low value to an end-user and doesn't "prove out" the CSIPHY, TPG
>> and RDI path - which is the minimum entry point in upstream right now.
>>
>> I don't support less than a sensor at minimum.
>>
>> You guys must have a sensor you've used with this board ?
>>
>
> Yes we have, but both not upstreamed sensor, we currently have no plans
> for sensor upstream, perhaps this work will be carried out later.
>
Then, as Bryan said, this patch should not be sent. It brings no value
to the user of this DTS, because users-with-out-of-tree-patches can have
this as well out of tree.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 11+ messages in thread