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[94.29.10.250]) by smtp.googlemail.com with ESMTPSA id b4sm4260809ljp.84.2019.10.28.16.48.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Oct 2019 16:48:32 -0700 (PDT) Subject: Re: [PATCH v1 01/17] clk: tegra: Add custom CCLK implementation To: Peter De Schrijver , Stephen Boyd Cc: Thierry Reding , Jonathan Hunter , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Michael Turquette , Peter Geis , Nicolas Chauvet , Marcel Ziswiler , linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20191015211618.20758-1-digetx@gmail.com> <20191015211618.20758-2-digetx@gmail.com> <20191028145706.GF27141@pdeschrijver-desktop.Nvidia.com> From: Dmitry Osipenko Message-ID: <2e35c210-8d76-c096-69b6-91b6ed577605@gmail.com> Date: Tue, 29 Oct 2019 02:48:31 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <20191028145706.GF27141@pdeschrijver-desktop.Nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 28.10.2019 17:57, Peter De Schrijver пишет: > On Wed, Oct 16, 2019 at 12:16:02AM +0300, Dmitry Osipenko wrote: >> CCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supports >> multiple parents and it has internal clock divider which uses clock >> skipping technique, meaning that CPU's voltage should correspond to the >> parent clock rate and not CCLK. PLLX is the main CCLK parent that provides >> clock rates above 1GHz and it has special property such that the CCLK's >> internal divider is set into bypass mode when PLLX is set as a parent for >> CCLK. >> >> This patch forks generic Super Clock into CCLK implementation which takes >> into account all CCLK specifics. The proper CCLK implementation is needed >> by the upcoming Tegra20 CPUFreq driver update that will allow to utilize >> the generic cpufreq-dt driver by moving intermediate clock handling into >> the clock driver. Note that technically this all could be squashed into >> clk-super, but result will be messier. >> >> Note that currently all CCLKLP bits are left in the clk-super.c and only >> CCLKG is supported by clk-tegra-super-cclk. It shouldn't be difficult >> to move the CCLKLP bits, but CCLKLP is not used by anything in kernel >> and thus better not to touch it for now. > > .. > >> + super->reg = reg; >> + super->lock = lock; >> + super->width = 4; >> + super->flags = clk_super_flags; >> + super->frac_div.reg = reg + 4; >> + super->frac_div.shift = 16; >> + super->frac_div.width = 8; >> + super->frac_div.frac_width = 1; >> + super->frac_div.lock = lock; >> + super->frac_div.flags = TEGRA_DIVIDER_SUPER; >> + super->div_ops = &tegra_clk_frac_div_ops; >> + > > This is not right. The super clock divider is not a divider, it's a > pulse skipper. For the reference: on #tegra Peter explained to me in a more details what was meant here. Turned out that T30+ has a real CCLK divider and we won't use the pulse skipper for T20 nor for T30+, I'll update clk patches accordingly in the next revision.