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Mon, 6 Oct 2025 00:39:24 -0700 (PDT) Message-ID: <2e6ce092996f2717bc274e1c82873c42b2ab18ce.camel@icenowy.me> Subject: Re: [PATCH v2 2/2] riscv: dts: starfive: add DT for Orange Pi RV From: Icenowy Zheng To: E Shattow , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Emil Renner Berthing , Michael Zhu , Drew Fustini , Yao Zi Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Date: Mon, 06 Oct 2025 15:39:16 +0800 In-Reply-To: References: <20250930100318.2131968-1-uwu@icenowy.me> <20250930100318.2131968-2-uwu@icenowy.me> <579dad6b4ab0c981b8d51383af2db3a9f4394609.camel@icenowy.me> Organization: Anthon Open-Source Community Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.4 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External =E5=9C=A8 2025-10-05=E6=98=9F=E6=9C=9F=E6=97=A5=E7=9A=84 11:47 -0700=EF=BC= =8CE Shattow=E5=86=99=E9=81=93=EF=BC=9A > Hi Icenowy, >=20 > On 9/30/25 08:51, Icenowy Zheng wrote: > > =E5=9C=A8 2025-09-30=E6=98=9F=E6=9C=9F=E4=BA=8C=E7=9A=84 18:03 +0800=EF= =BC=8CIcenowy Zheng=E5=86=99=E9=81=93=EF=BC=9A > > > Orange Pi RV is a newly released SBC with JH7110 SoC, single GbE > > > port > > > (connected to JH7110 GMAC0 via a YT8531 PHY), 4 USB ports (via a > > > VL805 > > > PCIe USB controller connected to JH7110 PCIE0), a M.2 M-key slot > > > (connected to JH7110 PCIE1), a HDMI video output, a 3.5mm audio > > > output > > > and a microSD slot. > > >=20 > > > Other Onboard peripherals contain a SPI NOR (which contains the > > > U- > > > Boot > > > firmware), a 24c02 EEPROM storing some StarFive-specific > > > information > > > (factory programmed and read only by default) and an Ampak AP6256 > > > SDIO > > > Wi-Fi module. > > >=20 > > > Signed-off-by: Icenowy Zheng > > > --- > > > Changes in v2: > > > - Property order change mentioned in the review of v1. > > > - Added Wi-Fi (along with the always on VCC3V3_PCIE regulator, > > > which > > > is > > > =C2=A0 used to power up WIFI_3V3). The OOB IRQ is still not possible > > > to > > > use > > > =C2=A0 because of some incompatibility between StarFive pinctrl drive= r > > > and > > > =C2=A0 brcmfmac. > > > - Removed the LED because it's in common DTSI. > > >=20 > > > =C2=A0arch/riscv/boot/dts/starfive/Makefile=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 1 + > > > =C2=A0.../boot/dts/starfive/jh7110-orangepi-rv.dts=C2=A0 | 87 > > > +++++++++++++++++++ > > > =C2=A02 files changed, 88 insertions(+) > > > =C2=A0create mode 100644 arch/riscv/boot/dts/starfive/jh7110-orangepi= - > > > rv.dts > > >=20 > > > diff --git a/arch/riscv/boot/dts/starfive/Makefile > > > b/arch/riscv/boot/dts/starfive/Makefile > > > index b3bb12f78e7d5..24f1a44828350 100644 > > > --- a/arch/riscv/boot/dts/starfive/Makefile > > > +++ b/arch/riscv/boot/dts/starfive/Makefile > > > @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7100-starfive- > > > visionfive-v1.dtb > > > =C2=A0 > > > =C2=A0dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-deepcomputing-fml13v01.= dtb > > > =C2=A0dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-milkv-mars.dtb > > > +dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-orangepi-rv.dtb > > > =C2=A0dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-pine64-star64.dtb > > > =C2=A0dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-starfive-visionfive-2- > > > v1.2a.dtb > > > =C2=A0dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-starfive-visionfive-2- > > > v1.3b.dtb > > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-orangepi-rv.dts > > > b/arch/riscv/boot/dts/starfive/jh7110-orangepi-rv.dts > > > new file mode 100644 > > > index 0000000000000..5a917b7db6f78 > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/starfive/jh7110-orangepi-rv.dts > > > @@ -0,0 +1,87 @@ > > > +// SPDX-License-Identifier: GPL-2.0 OR MIT > > > +/* > > > + * Copyright (C) 2025 Icenowy Zheng > > > + */ > > > + > > > +/dts-v1/; > > > +#include "jh7110-common.dtsi" > > > + > > > +/ { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0model =3D "Xunlong Orange = Pi RV"; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0compatible =3D "xunlong,or= angepi-rv", "starfive,jh7110"; > > > + > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* This regulator is alway= s on by hardware */ > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0reg_vcc3v3_pcie: regulator= -vcc3v3-pcie { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0compatible =3D "regulator-fixed"; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0regulator-name =3D "vcc3v3-pcie"; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0regulator-min-microvolt =3D <3300000>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0regulator-max-microvolt =3D <3300000>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0regulator-always-on; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0}; > > > + > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0wifi_pwrseq: wifi-pwrseq { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0compatible =3D "mmc-pwrseq-simple"; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0reset-gpios =3D <&sysgpio 62 GPIO_ACTIVE_LOW>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0}; > > > +}; > > > + > > > +&gmac0 { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0assigned-clocks =3D <&aonc= rg JH7110_AONCLK_GMAC0_TX>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0assigned-clock-parents =3D= <&aoncrg > > > JH7110_AONCLK_GMAC0_RMII_RTX>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0starfive,tx-use-rgmii-clk; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0status =3D "okay"; > > > +}; > > > + > > > +&mmc0 { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0#address-cells =3D <1>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0#size-cells =3D <0>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0cap-sd-highspeed; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0mmc-pwrseq =3D <&wifi_pwrs= eq>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0vmmc-supply =3D <®_vcc3= v3_pcie>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0vqmmc-supply =3D <&vcc_3v3= >; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0status =3D "okay"; > > > + > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0ap6256: wifi@1 { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0compatible =3D "brcm,bcm43456-fmac", "brcm,bcm4329- > > > fmac"; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0reg =3D <1>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0/* TODO: out-of-band IRQ on GPIO21 */ > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0}; > > > +}; > > > + >=20 > > > +&mmc0_pins { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * As the MMC0 bus is used= to connect a SDIO Wi-Fi card > > > instead of > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * an eMMC card, and the e= MMC RST is repurposed to be an > > > enablement > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * pin of the SDIO Wi-Fi, = remove it from the pinctrl node > > > and > > > manage > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * it as a GPIO instead. > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 */ > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/delete-node/ rst-pins; > > > +}; > > > + >=20 > Listed on the schematic [1] as: > Default function SDIO0 RSTn GPIO62 for eMMC:J9 > Highlighted (non-default?) function GPIO62 D17 << WIFI_EN_H_GPIO62 > WIFI_EN_H_GPIO62 >> WIFI_PWREN (pin 12 WL_REG_ON of module AP6256) >=20 > I've sent a patch [2] to portion out mmc0 reset pins from jh7110- > common.dtsi >=20 > > > +&mmc1 { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/delete-property/ cd-gpios= ; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0broken-cd; > >=20 > > Well it's found that the card detect is working, although with > > different polarity with other boards. > >=20 > > Here should be: > > ``` > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0cd-gpios =3D <&sysgpio = 41 GPIO_ACTIVE_HIGH>; > > ``` > >=20 > > Will be fixed in the next revision. >=20 > Yes, listed on the schematic [1] as: > SD SDIO0 CD GPIO41 for MicroSD:J10 >=20 > There is not a mention of active high or active low on the schematic > label, however there is listed a 10Kohm pull-up to +Vdd1.833 for the > circuit diagram of the Micro SD Card. The card holder is referenced > to > ground and could reasonably be N/O or N/C switch operation depending > on > the exact part selected for manufacture. >=20 > >=20 > > > +}; > > > + > > > +&pcie0 { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0status =3D "okay"; > > > +}; > > > + > > > +&pcie1 { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0status =3D "okay"; > > > +}; > > > + >=20 > > > +&phy0 { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0rx-internal-delay-ps =3D <= 1500>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0tx-internal-delay-ps =3D <= 1500>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0motorcomm,tx-clk-adj-enabl= ed; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0motorcomm,tx-clk-10-invert= ed; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0motorcomm,tx-clk-100-inver= ted; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0motorcomm,tx-clk-1000-inve= rted; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0motorcomm,rx-clk-drv-micro= amp =3D <3970>; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0motorcomm,rx-data-drv-micr= oamp =3D <2910>; > > > +}; >=20 > 'motorcomm,rx' before 'motorcomm,tx' in `LANG=3DC sort` of vendor- > specific > properties. >=20 > > > + > > > +&pwmdac { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0status =3D "okay"; > > > +}; > >=20 > Additional non-default GPIO as listed in the Orange Pi design: > GPIO21 WIFI_WAKE_HOST_H /* default vf2 function PCIE_PWREN_H_GPIO21 > */ > GPIO22 >> BT_UART_RXD /* default vf2 function MIPI_PWR_EN */ > GPIO23 << BT_UART_TXD /* default vf2 function LCD RESET */ > GPIO24 << BT_UART_CTS /* default vf2 function MIPI_LCD_BL */ > GPIO25 << BT_UART_RTS /* default vf2 function TP_DET_GPIO25 */ > GPIO30 << BT_EN_H_GPIO30 /* default vf2 function TP_INT_L */ > GPIO31 << BT_WAKE_GPIO31 /* default vf2 function TP_RST_L */ >=20 > Of all the above, GPIO21 is defined in jh7110-common.dtsi > &pcie1_pins/wake-pins and may need consideration. >=20 > There is a note about "PMIC_PWRON as Key" and so does this have the > meaning of it is used as an input device? >=20 > Also noted is that the USB over-current circuit appears to be > implemented, different than being absent in other VF2 designs. >=20 > 1: > http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/service= -and-support/Orange-Pi-RV.html > 2: > https://lore.kernel.org/lkml/20251005174450.1949110-1-e@freeshell.de/ >=20 > With the card detect describing hardware corrected, and clean up the > vendor property sort, then please confirm if you think GPIO21 is > described correctly. Well yes, GPIO21 should be splitted from PCIe pinctrl and assigned to be the out-of-band IRQ of the Wi-Fi module. My DT omits this because the jh7110 pinctrl driver is currently not compatible with brcmfmac out-of-band IRQ code. Should I add /delete-node/ for it? >=20 > Acked-by: E Shattow >=20