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([2a02:810d:15c0:828:77d1:16a1:abe1:84fc]) by smtp.gmail.com with ESMTPSA id u24-20020a056402111800b0050bc4eb9846sm8354012edv.1.2023.05.16.09.43.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 May 2023 09:43:17 -0700 (PDT) Message-ID: <2e6f282c-33d9-7f96-0338-c4fd457d04fa@linaro.org> Date: Tue, 16 May 2023 18:43:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 1/2] arm64: dts: qcom: sm8550-qrd: add PCIe0 Content-Language: en-US To: Dmitry Baryshkov Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230516133011.108093-1-krzysztof.kozlowski@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 16/05/2023 18:39, Dmitry Baryshkov wrote: > On Tue, 16 May 2023 at 16:30, Krzysztof Kozlowski > wrote: >> >> Add PCIe0 nodes used with WCN7851 device. The PCIe1 is not connected, >> thus skip pcie_1_phy_aux_clk input clock to GCC. >> >> Signed-off-by: Krzysztof Kozlowski >> --- >> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 32 +++++++++++++++++++++++++ >> 1 file changed, 32 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts >> index ccc58e6b45bd..e7a2bc5d788b 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts >> +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts >> @@ -385,6 +385,38 @@ vreg_l3g_1p2: ldo3 { >> }; >> }; >> >> +&gcc { >> + clocks = <&bi_tcxo_div2>, <&sleep_clk>, >> + <&pcie0_phy>, >> + <&pcie1_phy>, >> + <0>, >> + <&ufs_mem_phy 0>, >> + <&ufs_mem_phy 1>, >> + <&ufs_mem_phy 2>, >> + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; >> +}; > > Is there any reason to disable the PCIe1 PHY AUX clock here? I mean, > the PCIe1 is still enabled in the hardware. I was thinking about this. The AUX clock seems to be an external clock, although I could not find it in schematics. I assume that on QRD8550 it could be missing, if it is really external. OTOH, downstream DTS did not seem to care... Best regards, Krzysztof