From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christo Radev Subject: Re: [PATCH 1/1] ARM: dts: sunxi: Add a olinuxino-lime2-emmc Date: Wed, 4 May 2016 07:31:11 -0700 (PDT) Message-ID: <2e745ef7-ddc0-40fc-b867-414543690276@googlegroups.com> References: <1461827998-12192-1-git-send-email-oliver@schinagl.nl> <57285162.2000704@schinagl.nl> <5729F07C.3080308@schinagl.nl> <948be370-4401-43cb-862e-d4376755a75d@googlegroups.com> <5729F6D6.8030100@schinagl.nl> <4704fa35-9a2a-4e6e-8fd4-f4778405c598@googlegroups.com> <572A0052.9060202@schinagl.nl> Reply-To: christo.radev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_4453_1131217155.1462372271639" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <572A0052.9060202-dxLnbx3+1qmEVqv0pETR8A@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: linux-sunxi Cc: christo.radev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, radoslav.kolev-1W28NRE8jL9DPfheJLI6IQ@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, tsvetan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, dev-3kdeTeqwOZ9EV1b7eY7vFQ@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, oliver-dxLnbx3+1qmEVqv0pETR8A@public.gmane.org List-Id: devicetree@vger.kernel.org ------=_Part_4453_1131217155.1462372271639 Content-Type: multipart/alternative; boundary="----=_Part_4454_621519749.1462372271640" ------=_Part_4454_621519749.1462372271640 Content-Type: text/plain; charset=UTF-8 Tanks Oliver, It could be the problem to get 8-bit access working. Unfortunately, I do not see where to make this changes because original dts files are used in Armbian build. I also see '*SUNXI_PINCTRL_PIN*' and '*SUNXI_FUNCTION*' may require some patches in addition. I am ready to make 8-bit eMMC access tests again so could you help me with the needed staff it has to be used. Best regards Chris On Wednesday, May 4, 2016 at 4:59:52 PM UTC+3, Olliver Schinagl wrote: > > Hey Christo, > > On 04-05-16 15:32, Christo Radev wrote: > > Hi Oliver, > > I do: that > http://forum.armbian.com/index.php/topic/853-armbian-customization/page-2#entry7359 > The syntax error seen there was fixed and the result is: > http://forum.armbian.com/index.php/topic/853-armbian-customization/page-2#entry7361 > > Nope, you are still forgetting and seeing an 'unsupported function' error > because of it. > > You forgot to add: > > >>>* SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), > *>>>* SUNXI_FUNCTION(0x0, "gpio_in"), > *>>>* SUNXI_FUNCTION(0x1, "gpio_out"), > *>>>* - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ > *>>>* + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ > *>>>* + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ > *>>>* SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), > *>>>* SUNXI_FUNCTION(0x0, "gpio_in"), > *>>>* SUNXI_FUNCTION(0x1, "gpio_out"), > *>>>* - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ > *>>>* + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ > *>>>* + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ > *>>>* SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), > *>>>* SUNXI_FUNCTION(0x0, "gpio_in"), > *>>>* SUNXI_FUNCTION(0x1, "gpio_out"), > *>>>* - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ > *>>>* + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ > *>>>* + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ > *>>>* SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), > *>>>* SUNXI_FUNCTION(0x0, "gpio_in"), > *>>>* SUNXI_FUNCTION(0x1, "gpio_out"), > *>>>* - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ > *>>>* + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ > *>>>* + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */* > > > to actually get the pin functions. > > > The same tests was done on legacy kernel 3.4.111 modifying fex file and > the result is the same: > http://forum.armbian.com/index.php/topic/853-armbian-customization/page-2#entry7265 > > > Best regards > Chris > > > On Wednesday, May 4, 2016 at 4:19:20 PM UTC+3, Olliver Schinagl wrote: >> >> Hey Christo, >> >> On 04-05-16 15:07, Christo Radev wrote: >> >> Hi Olliver, >> >> I have already test it a few weeks ago and definitely can say that 8-bit >> bus did not work on A20-Olinuxino-Lime2-eMMC with mainline kernel. >> See may post here >> >> . >> >> I saw, but you forgot to define the pins for 4.x :) >> >> See my patch from earlier: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-September/368887.html >> >> Olliver >> >> >> Best regards >> >> Chris >> >> On Wednesday, May 4, 2016 at 3:52:17 PM UTC+3, Olliver Schinagl wrote: >>> >>> Hey Radoslav, >>> >>> On 04-05-16 14:30, Radoslav Kolev wrote: >>> > 2016-05-03 10:25 GMT+03:00 Chen-Yu Tsai : >>> >> On Tue, May 3, 2016 at 3:21 PM, Olliver Schinagl >>> wrote: >>> >>>>> + bus-width = <4>; >>> >>>> Only 4 bits? We normally see eMMC with 8 bits. 4 bits are some kind >>> of >>> >>>> embedded SD card. >>> >>> On A20 as well? Our investigations so far have concluded that the >>> A10 and >>> >>> A20 have those pins not mapped out to pads. The IP does support it >>> however >>> >>> we assume. >>> >> You're right. My bad. First time A10/A20 sees eMMC support. >>> > I can't say anything about A10/A20, but I have a board with A13 and >>> > the same eMMC chip and it works fine in 8 bit mode. >>> Yep, sun5i actually brings them all out to pads, the A20 however does >>> not :( We first thought that the A20 would also be an 8bitter, because >>> the mmc IP appears to be the same as sun5i, but initial tests show it is >>> not. As for A10, it has older IP and it might not even support 8 bit >>> mode, let alone bring out the pins. >>> >>> But with A20's + eMMC being available via the lime2, others may repeat >>> my experiments! The lime2 is 8 bit connected. >>> >>> Olliver >>> > >>> > Regards, >>> > Radoslav >>> >>> >> > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. ------=_Part_4454_621519749.1462372271640 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Tanks Oliver,

It could be the problem to get 8-bit = access working.

Unfortunately, I do not see where to make this chang= es because original dts files are used in Armbian build.
I als= o see 'SUNXI_PINCTRL_PIN' and 'SUNXI_FUNCTION'= ; may require some patches in addition.

I am ready to make 8-bit eMM= C access tests again so could you help me with the needed staff it has to b= e used.

Best regards
Chris

On Wednesday, May 4, 2016 at 4:= 59:52 PM UTC+3, Olliver Schinagl wrote:
=20 =20 =20
Hey Christo,

On 04-05-16 15:32, Christo Radev wrote:
Nope, you are still forgetting and seeing an 'unsupported function&= #39; error because of it.

You forgot to add:

>>>          SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
>>>                    SUNXI_FUNCTION(0x0, "gpio_in&qu=
ot;),
>>>                    SUNXI_FUNCTION(0x1, "gpio_out&q=
uot;),
>>> -                 SUNXI_FUNCTION(0x2, "nand0"=
)),        /* NDQ4 */
>>> +                 SUNXI_FUNCTION(0x2, "nand0"=
),         /* NDQ4 */
>>> +                 SUNXI_FUNCTION(0x3, "mmc2")=
),         /* D4 */
>>>          SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
>>>                    SUNXI_FUNCTION(0x0, "gpio_in&qu=
ot;),
>>>                    SUNXI_FUNCTION(0x1, "gpio_out&q=
uot;),
>>> -                 SUNXI_FUNCTION(0x2, "nand0"=
)),        /* NDQ5 */
>>> +                 SUNXI_FUNCTION(0x2, "nand0"=
),         /* NDQ5 */
>>> +                 SUNXI_FUNCTION(0x3, "mmc2")=
),         /* D5 */
>>>          SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
>>>                    SUNXI_FUNCTION(0x0, "gpio_in&qu=
ot;),
>>>                    SUNXI_FUNCTION(0x1, "gpio_out&q=
uot;),
>>> -                 SUNXI_FUNCTION(0x2, "nand0"=
)),        /* NDQ6 */
>>> +                 SUNXI_FUNCTION(0x2, "nand0"=
),         /* NDQ6 */
>>> +                 SUNXI_FUNCTION(0x3, "mmc2")=
),         /* D6 */
>>>          SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
>>>                    SUNXI_FUNCTION(0x0, "gpio_in&qu=
ot;),
>>>                    SUNXI_FUNCTION(0x1, "gpio_out&q=
uot;),
>>> -                 SUNXI_FUNCTION(0x2, "nand0"=
)),        /* NDQ7 */
>>> +                 SUNXI_FUNCTION(0x2, "nand0"=
),         /* NDQ7 */
>>> +                 SUNXI_FUNCTION(0x3, "mmc2")=
),         /* D7 */

to actually get the pin functions.

The same tests was done on legacy kernel 3.4.111 modifying fex file and the result is the same: http://forum.armbian.com/index.php/topic/= 853-armbian-customization/page-2#entry7265


Best regards
Chris


On Wednesday, May 4, 2016 at 4:19:20 PM UTC+3, Olliver Schinagl wrote:
Hey Christo,

On 04-05-16 15:07, Christo Radev wrote:
Hi Olliver,

I have already test it a few weeks ago and definitely can say that 8-bit bus did not work on A20-Olinuxino-Lime2-eMMC with mainline kernel.
See may post here.
I saw, but you forgot to define the pins for 4.x :)

See my patch from earlier: http://lists.infradead.org/pipermail/linux= -arm-kernel/2015-September/368887.html

Olliver


Best regards

Chris

On Wednesday, May 4, 2016 at 3:52:17 PM UTC+3, Olliver Schinagl wrote:
Hey Radoslav,

On 04-05-16 14:30, Radoslav Kolev wrote:
> 2016-05-03 10:25 GMT+03:00 Chen-Yu Tsai <<= a>we...-jdAy2FN1RRM@public.gmane.org>:
>> On Tue, May 3, 2016 at 3:21 PM, Olliver Schinagl <oli...-dxLnbx3+1qmEVqv0pETR8A@public.gmane.org> wrote:
>>>>> + =C2=A0 =C2=A0 =C2=A0 bus-width =3D= <4>;
>>>> Only 4 bits? We normally see eMMC with 8 bits. 4 bits are some kind of
>>>> embedded SD card.
>>> On A20 as well? Our investigations so far have concluded that the A10 and
>>> A20 have those pins not mapped out to pads. The IP does support it however
>>> we assume.
>> You're right. My bad. First time A10/A20 see= s eMMC support.
> I can't say anything about A10/A20, but I have a board with A13 and
> the same eMMC chip and it works fine in 8 bit mode.
Yep, sun5i actually brings them all out to pads, the A20 however does
not :( We first thought that the A20 would also be an 8bitter, because
the mmc IP appears to be the same as sun5i, but initial tests show it is
not. As for A10, it has older IP and it might not even support 8 bit
mode, let alone bring out the pins.

But with A20's + eMMC being available via the lime2, others may repeat
my experiments! The lime2 is 8 bit connected.

Olliver
>
> Regards,
> Radoslav



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