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[71.163.245.5]) by smtp.gmail.com with ESMTPSA id d4sm9153573qty.15.2021.08.11.04.27.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Aug 2021 04:27:20 -0700 (PDT) Subject: Re: [Patch v5 3/6] cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support To: Viresh Kumar Cc: agross@kernel.org, bjorn.andersson@linaro.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org, steev@kali.org, tdas@codeaurora.org, mka@chromium.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20210809191605.3742979-1-thara.gopinath@linaro.org> <20210809191605.3742979-4-thara.gopinath@linaro.org> <20210810024723.qne6ntjtv5zxf576@vireshk-i7> From: Thara Gopinath Message-ID: <2ea49a1c-5336-5a52-43ff-2000a7b0d25e@linaro.org> Date: Wed, 11 Aug 2021 07:27:19 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210810024723.qne6ntjtv5zxf576@vireshk-i7> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 8/9/21 10:47 PM, Viresh Kumar wrote: > On 09-08-21, 15:16, Thara Gopinath wrote: >> Add interrupt support to notify the kernel of h/w initiated frequency >> throttling by LMh. Convey this to scheduler via thermal presssure >> interface. >> >> Signed-off-by: Thara Gopinath >> --- >> >> v4->v5: >> - Changed throttle_lock from a spinlock to mutex to take potential >> race between LMh de-init sequence and reenabling of >> interrupts/polling after a thermal throttle event. >> - Other cosmetic fixes as pointed out by Viresh. > > How do you expect this to get merged ? I pick up this patch alone ? Hi. Yes, you can pick up this patch alone. This patch is standalone and has no dependencies. Once you do that, I will drop it from my series. > -- Warm Regards Thara (She/Her/Hers)