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Thu, 30 Apr 2026 01:40:20 -0700 (PDT) X-Received: by 2002:a17:902:c949:b0:2b0:5520:f497 with SMTP id d9443c01a7336-2b9a231ad36mr19136485ad.9.1777538419530; Thu, 30 Apr 2026 01:40:19 -0700 (PDT) Received: from [10.218.5.114] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b98893f132sm46236635ad.49.2026.04.30.01.40.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Apr 2026 01:40:19 -0700 (PDT) Message-ID: <2efc6a84-cbae-4460-a0f9-3712da8c33a7@oss.qualcomm.com> Date: Thu, 30 Apr 2026 14:10:13 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/5] arm64: defconfig: Enable Qualcomm Shikra SoC Global clock controller To: Krzysztof Kozlowski , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org References: <20260429-shikra-gcc-rpmcc-clks-v1-0-c3cd77558b7a@oss.qualcomm.com> <20260429-shikra-gcc-rpmcc-clks-v1-5-c3cd77558b7a@oss.qualcomm.com> <6f76dd8a-2007-4012-980f-268076fff5ad@kernel.org> Content-Language: en-US From: Imran Shaik In-Reply-To: <6f76dd8a-2007-4012-980f-268076fff5ad@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDMwMDA4NCBTYWx0ZWRfX+clLGDFRc8/p c0ey0nP9uQlFtq7akY2+FNg5SH9KQNeFCqlw/8BGxou7XaB1U8jABczA6Q/vHiZHc4poW90XAYO kr1rsVCNpBgrHxrHGDvkcCsf7A8lGGVSQ7iCiVYB2w2VIcTsgzPwMOy49Z1pECy847dGqj8HPyv t3WQ3bX3NqnRn63iZHTdoYT6WmQQD19Xe8OqD+R0weVBYLIOQlVx7AytBIC61tpxi5BC3x179BQ BlhgDHYZ2bgGT7vVJzX3nNfXQKTNuHi1wc2WX5HWy/GSooQJysJHRrHSQpR4vYf/44IKIj4pmwg IwJkBR1Xd1ygsSJV1OtCoasiEnS5W5I6G3FzvMWZgYiGFOipKniMOr6FNngJQnLJR/tgsHcQGfc Vl0cG2F/FxqtLg8h47s5CLBoTqWrXOwjDdORmCE1hW+6p/yAn0qAjTOEcTSfaLAqHWfmWL+2FaY YHvuwM0MCitXJ48zXgw== X-Proofpoint-ORIG-GUID: CV1j8urQazoColl5JEWWaU25MhHYTiXC X-Authority-Analysis: v=2.4 cv=O5oJeh9W c=1 sm=1 tr=0 ts=69f31574 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=FE2aYY5kXyuWuzusOicA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: CV1j8urQazoColl5JEWWaU25MhHYTiXC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-30_02,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 adultscore=0 phishscore=0 suspectscore=0 impostorscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604300084 On 29-04-2026 08:02 pm, Krzysztof Kozlowski wrote: > On 29/04/2026 12:51, Imran Shaik wrote: >> Enable the Global clock controller driver on Qualcomm Shikra EVK board. >> >> Signed-off-by: Imran Shaik >> --- >> arch/arm64/configs/defconfig | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig >> index dd1ac01ee29bf631d517c38486f6896ffd82dcc9..13e04080b37160129ccd47b0148a64277b8e0e4c 100644 >> --- a/arch/arm64/configs/defconfig >> +++ b/arch/arm64/configs/defconfig >> @@ -1461,6 +1461,7 @@ CONFIG_CLK_IMX8QXP=y >> CONFIG_CLK_IMX8ULP=y >> CONFIG_CLK_IMX93=y >> CONFIG_CLK_IMX95_BLK_CTL=y >> +CONFIG_CLK_SHIKRA_GCC=y > > Beside some really odd order, this patch should not be needed. > Sure, will drop this change, and update Kconfig accordingly. Thanks, Imran