From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69C49C7619A for ; Wed, 12 Apr 2023 02:36:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229553AbjDLCgD (ORCPT ); Tue, 11 Apr 2023 22:36:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229503AbjDLCgC (ORCPT ); Tue, 11 Apr 2023 22:36:02 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08B14172B; Tue, 11 Apr 2023 19:36:01 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id F112324E201; Wed, 12 Apr 2023 10:35:53 +0800 (CST) Received: from EXMBX067.cuchost.com (172.16.6.67) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 12 Apr 2023 10:35:53 +0800 Received: from [192.168.125.89] (113.72.145.176) by EXMBX067.cuchost.com (172.16.6.67) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 12 Apr 2023 10:35:53 +0800 Message-ID: <2f5b4e94-0476-83df-0b18-a6b2ba1ea896@starfivetech.com> Date: Wed, 12 Apr 2023 10:35:52 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v1 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Content-Language: en-US To: Conor Dooley CC: "Rafael J. Wysocki" , Viresh Kumar , Emil Renner Berthing , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Shengyu Qu , , , , References: <20230411083257.16155-1-mason.huo@starfivetech.com> <20230411083257.16155-4-mason.huo@starfivetech.com> <20230411-darling-chump-faaf8dec29ef@wendy> From: Mason Huo In-Reply-To: <20230411-darling-chump-faaf8dec29ef@wendy> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX067.cuchost.com (172.16.6.67) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 2023/4/11 17:06, Conor Dooley wrote: > Hey Mason, > > On Tue, Apr 11, 2023 at 04:32:57PM +0800, Mason Huo wrote: >> Add the operating-points-v2 to support cpu scaling >> on StarFive JH7110 SoC. > > (btw, there's no need to wrap commit messages at 52 columns, you have > 72 to work with) > Hi Conor, Thanks for your review. Will place it in the same line. >> It supports up to 4 cpu frequency loads. >> >> Signed-off-by: Mason Huo >> --- >> .../jh7110-starfive-visionfive-2.dtsi | 25 +++++++++++++++++++ >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 25 +++++++++++++++++++ >> 2 files changed, 50 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> index df582bddae4b..ae446b268e78 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> @@ -228,3 +228,28 @@ &uart0 { >> pinctrl-0 = <&uart0_pins>; >> status = "okay"; >> }; >> + >> +&U74_1 { >> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; >> + clock-names = "cpu"; >> + cpu-supply = <®_dcdc2>; >> +}; >> + >> +&U74_2 { >> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; >> + clock-names = "cpu"; >> + cpu-supply = <®_dcdc2>; >> +}; >> + >> +&U74_3 { >> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; >> + clock-names = "cpu"; >> + cpu-supply = <®_dcdc2>; >> +}; >> + >> +&U74_4 { >> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; > ^^ > There's a double space in each of these. > >> + clock-names = "cpu"; >> + cpu-supply = <®_dcdc2>; >> +}; > > How come these two clock properties are being added in .dtsi? > Should they not be in .dtsi? >> Thanks, > Conor. Yes, will move them to .dtsi Thanks Mason