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Fri, 18 Jul 2025 10:37:30 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGS+WhE3jQDC0YVjY/4E/XNzovaX5vUwzvI27UOQtAKYgfzXmsNsUeiIAZoMDUSIbvOYGM/sQ== X-Received: by 2002:a05:6a20:430c:b0:224:46a0:25ef with SMTP id adf61e73a8af0-2390c7f698cmr13397740637.16.1752860249913; Fri, 18 Jul 2025 10:37:29 -0700 (PDT) Received: from [192.168.0.195] ([49.204.28.43]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-759c84e2b48sm1581307b3a.19.2025.07.18.10.37.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Jul 2025 10:37:29 -0700 (PDT) Message-ID: <2f5b5e6e-5041-453e-b3f7-b10b40bc6f57@oss.qualcomm.com> Date: Fri, 18 Jul 2025 23:07:23 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 7/7] clk: qcom: gcc: Add support for Global Clock Controller To: Krzysztof Kozlowski , Abel Vesa , Pankaj Patil Cc: sboyd@kernel.org, mturquette@baylibre.com, andersson@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_rjendra@quicinc.com, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250716152017.4070029-1-pankaj.patil@oss.qualcomm.com> <20250716152017.4070029-8-pankaj.patil@oss.qualcomm.com> <40534488-24f6-4958-b032-d45a177dfd80@kernel.org> Content-Language: en-US From: Taniya Das In-Reply-To: <40534488-24f6-4958-b032-d45a177dfd80@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE4MDEzOSBTYWx0ZWRfXx58htIlNeGSf s9i5orNq9O9L476sylvuTkrN68uQxKecMW7ZtQAa7xDZ2yjUZV9UY/R2wbnEqa9Nz7jdP3WrtUE OvKX2vB06I2EyQr+6ZAPyKPmgFaAcjE1vYe2mBvmNvbGmYpOw5KkIkJ9De5jKA8959wKI9crHAk QG8kW0G+QaH/5f0ZekzpR+T5g34MUkeaqfE1EoJw2qVyffBMecOZICwMYoGElA5tnebIfnlcyMK meTyaZ3NZBUmcuZdFrDRDgeQJVC9iPrbJE4mQG028YHRBchQCPZwUIAF3SYLFIzAtlueYjGg8MV bnL2QDaVJKpEkRPorDIzGydp1/K7I7lH5nQeQPyqMtrQ2eW0Y6LWXpA+1f013r4248Ofrt4tif4 pPMhFvgBsfeVDqM/umf/l/kuQEuQb6AYJ2W42L8jIxNCxXVjhQggn4Xg5DEHxRNnODZAA84A X-Proofpoint-GUID: 2ds3lHZeiI5nfU8FyPkVPgkoxgYjFgY8 X-Authority-Analysis: v=2.4 cv=SeX3duRu c=1 sm=1 tr=0 ts=687a865c cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=tMiizUMu9hGndvLFPAJAbA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=ZEZnheZsc53CzuolOOIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: 2ds3lHZeiI5nfU8FyPkVPgkoxgYjFgY8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-18_04,2025-07-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxscore=0 priorityscore=1501 bulkscore=0 phishscore=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 clxscore=1015 adultscore=0 suspectscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507180139 On 7/17/2025 3:38 PM, Krzysztof Kozlowski wrote: > On 17/07/2025 11:57, Abel Vesa wrote: >> On 25-07-16 20:50:17, Pankaj Patil wrote: >>> From: Taniya Das >>> >>> Add support for Global clock controller for Glymur platform. >>> >>> Signed-off-by: Taniya Das >>> Signed-off-by: Pankaj Patil >>> --- >>> drivers/clk/qcom/Kconfig | 10 + >>> drivers/clk/qcom/Makefile | 1 + >>> drivers/clk/qcom/gcc-glymur.c | 8623 +++++++++++++++++++++++++++++++++ >>> 3 files changed, 8634 insertions(+) >>> create mode 100644 drivers/clk/qcom/gcc-glymur.c >>> >>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig >>> index 051301007aa6..1d9e8c6aeaed 100644 >>> --- a/drivers/clk/qcom/Kconfig >>> +++ b/drivers/clk/qcom/Kconfig >>> @@ -645,6 +645,16 @@ config SAR_GPUCC_2130P >>> Say Y if you want to support graphics controller devices and >>> functionality such as 3D graphics. >>> >>> +config SC_GCC_GLYMUR >> >> Wait, are we going back to this now? >> >> X Elite had CLK_X1E80100_GCC, so maybe this should be CLK_GLYMUR_GCC >> then. > > > Yeah, the SC is meaningless here, unless you call it CLK_SC8480XP_GCC, > so the authors need to decide on one naming. Not mixtures.. > > Glymur follows the "SC" naming convention, and historically we've adhered to the format: "SC/SM/SDX/SA__". This structure has helped maintain consistency and clarity across platforms. The case of X1E80100 appears to be an exception—likely influenced by its unique naming convention at the time. That said, I’d prefer to stay aligned with the established convention used for earlier chipsets to preserve continuity. I’d appreciate hearing your thoughts on this as well. -- Thanks, Taniya Das