[RFC PATCH v3 02/37] dt-bindings: soc: kvx: Add binding for kalray,coolidge-pwr-ctrl

[RFC PATCH v3 02/37] dt-bindings: soc: kvx: Add binding for kalray,coolidge-pwr-ctrl

[ysionneau]

From: Yann Sionneau <ysionneau@kalrayinc.com>

Add binding for Kalray Coolidge SoC cluster power controller.

Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
---

Notes:

V2 -> V3: New patch
---
 .../soc/kvx/kalray,coolidge-pwr-ctrl.yaml     | 37 +++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.yaml

diff --git a/Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.yaml b/Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.yaml
new file mode 100644
index 0000000000000..e0363a080ac11
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/kalray/kalray,coolidge-pwr-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kalray Coolidge cluster Power Controller (pwr-ctrl)
+
+maintainers:
+  - Jonathan Borne <jborne@kalrayinc.com>
+  - Julian Vetter <jvetter@kalrayinc.com>
+  - Yann Sionneau <ysionneau@kalrayinc.com>
+
+description: |
+  The Power Controller (pwr-ctrl) control cores reset and wake-up procedure.
+
+properties:
+  compatible:
+    const: kalray,coolidge-pwr-ctrl
+
+  reg:
+    maxItems: 1
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    pwr_ctrl: pwr-ctrl@a40000 {
+        compatible = "kalray,coolidge-pwr-ctrl";
+        reg = <0x00 0xa40000 0x00 0x4158>;
+    };
+
+...
-- 
2.45.2

Re: [RFC PATCH v3 02/37] dt-bindings: soc: kvx: Add binding for kalray,coolidge-pwr-ctrl

[Krzysztof Kozlowski]

On 22/07/2024 11:41, ysionneau@kalrayinc.com wrote:
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add binding for Kalray Coolidge SoC cluster power controller.
> 
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3: New patch
> ---
>  .../soc/kvx/kalray,coolidge-pwr-ctrl.yaml     | 37 +++++++++++++++++++
>  1 file changed, 37 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.yaml b/Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.yaml
> new file mode 100644
> index 0000000000000..e0363a080ac11
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.yaml
> @@ -0,0 +1,37 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/kalray/kalray,coolidge-pwr-ctrl.yaml#

It does not look like you tested the bindings, at least after quick
look. Please run `make dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
Maybe you need to update your dtschema and yamllint.

Best regards,
Krzysztof

Re: [RFC PATCH v3 02/37] dt-bindings: soc: kvx: Add binding for kalray,coolidge-pwr-ctrl

[Yann Sionneau]

Hello Krzysztof,

On 22/07/2024 11:47, Krzysztof Kozlowski wrote:
> On 22/07/2024 11:41, ysionneau@kalrayinc.com wrote:
>> From: Yann Sionneau <ysionneau@kalrayinc.com>
>>
>> Add binding for Kalray Coolidge SoC cluster power controller.
>>
>> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
>> ---
>>
>> Notes:
>>
>> V2 -> V3: New patch
>> ---
>>  .../soc/kvx/kalray,coolidge-pwr-ctrl.yaml     | 37 +++++++++++++++++++
>>  1 file changed, 37 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.yaml b/Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.yaml
>> new file mode 100644
>> index 0000000000000..e0363a080ac11
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.yaml
>> @@ -0,0 +1,37 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/kalray/kalray,coolidge-pwr-ctrl.yaml#
> It does not look like you tested the bindings, at least after quick
> look. Please run `make dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
> Maybe you need to update your dtschema and yamllint.

You are entirely correct, I *did* test the bindings at some point, but then in my last rounds of modifications I only ran make dtbs and make dtbs_check and completely forgot to re-run the `make dt_binding_check`.

Sorry about that.

We'll work on those again.

Regards,

PS: my dtschema and yamllint are up to date though.

-- 

Yann

Re: [RFC PATCH v3 02/37] dt-bindings: soc: kvx: Add binding for kalray,coolidge-pwr-ctrl

[Rob Herring (Arm)]

On Mon, 22 Jul 2024 11:41:13 +0200, ysionneau@kalrayinc.com wrote:
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add binding for Kalray Coolidge SoC cluster power controller.
> 
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3: New patch
> ---
>  .../soc/kvx/kalray,coolidge-pwr-ctrl.yaml     | 37 +++++++++++++++++++
>  1 file changed, 37 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.yaml: $id: Cannot determine base path from $id, relative path/filename doesn't match actual path or filename
 	 $id: http://devicetree.org/schemas/kalray/kalray,coolidge-pwr-ctrl.yaml
 	file: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/kvx/kalray,coolidge-pwr-ctrl.example.dtb: pwr-ctrl@a40000: reg: [[0, 10747904], [0, 16728]] is too long
	from schema $id: http://devicetree.org/schemas/kalray/kalray,coolidge-pwr-ctrl.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240722094226.21602-3-ysionneau@kalrayinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

[RFC PATCH v3 03/37] dt-bindings: Add binding for kalray,kv3-1-intc

[ysionneau]

From: Yann Sionneau <ysionneau@kalrayinc.com>

Add binding for Kalray kv3-1 core interrupt controller.

Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
---

Notes:

V2 -> V3: Fixed bindings to adhere to dt schema
---
 .../kalray,kv3-1-intc.yaml                    | 54 +++++++++++++++++++
 1 file changed, 54 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml
new file mode 100644
index 0000000000000..9c8bb2c8c49dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/kalray,kv3-1-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kalray kv3-1 Core Interrupt Controller
+
+maintainers:
+  - Jonathan Borne <jborne@kalrayinc.com>
+  - Julian Vetter <jvetter@kalrayinc.com>
+  - Yann Sionneau <ysionneau@kalrayinc.com>
+
+description: |
+  The Kalray Core Interrupt Controller is tightly integrated in each kv3 core
+  present in the Coolidge SoC.
+
+  It provides the following features:
+  - 32 independent interrupt sources
+  - 2-bit configurable priority level
+  - 2-bit configurable ownership level
+
+properties:
+  compatible:
+    const: kalray,kv3-1-intc
+
+  "#interrupt-cells":
+    const: 1
+    description:
+      The IRQ number.
+
+  "#address-cells":
+    const: 0
+
+  interrupt-controller: true
+
+additionalProperties: false
+
+required:
+  - compatible
+  - "#interrupt-cells"
+  - "#address-cells"
+  - interrupt-controller
+
+examples:
+  - |
+    intc: interrupt-controller {
+        compatible = "kalray,kv3-1-intc";
+        #interrupt-cells = <1>;
+        #address-cells = <0>;
+        interrupt-controller;
+    };
+
+...
-- 
2.45.2

Re: [RFC PATCH v3 03/37] dt-bindings: Add binding for kalray,kv3-1-intc

[Krzysztof Kozlowski]

On 22/07/2024 11:41, ysionneau@kalrayinc.com wrote:
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add binding for Kalray kv3-1 core interrupt controller.
> 
> Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3: Fixed bindings to adhere to dt schema
> ---
>  .../kalray,kv3-1-intc.yaml                    | 54 +++++++++++++++++++
>  1 file changed, 54 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml
> new file mode 100644
> index 0000000000000..9c8bb2c8c49dd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml
> @@ -0,0 +1,54 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/kalray,kv3-1-intc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Kalray kv3-1 Core Interrupt Controller
> +
> +maintainers:
> +  - Jonathan Borne <jborne@kalrayinc.com>
> +  - Julian Vetter <jvetter@kalrayinc.com>
> +  - Yann Sionneau <ysionneau@kalrayinc.com>
> +
> +description: |
> +  The Kalray Core Interrupt Controller is tightly integrated in each kv3 core
> +  present in the Coolidge SoC.
> +
> +  It provides the following features:
> +  - 32 independent interrupt sources
> +  - 2-bit configurable priority level
> +  - 2-bit configurable ownership level
> +
> +properties:
> +  compatible:
> +    const: kalray,kv3-1-intc

What is the SoC name/model? You use "Kalray Core" and "Coolidge" and
"kv3-1".

> +
> +  "#interrupt-cells":
> +    const: 1
> +    description:
> +      The IRQ number.
> +
> +  "#address-cells":
> +    const: 0
> +
> +  interrupt-controller: true
> +
> +additionalProperties: false

Please put it after "required:" block. See example-schema. This applies
everywhere.

> +
> +required:
> +  - compatible
> +  - "#interrupt-cells"
> +  - "#address-cells"
> +  - interrupt-controller
> +
> +examples:
> +  - |
> +    intc: interrupt-controller {

No resources? How does it talk with the hardware?

> +        compatible = "kalray,kv3-1-intc";
> +        #interrupt-cells = <1>;
> +        #address-cells = <0>;
> +        interrupt-controller;
> +    };
> +
> +...

Best regards,
Krzysztof

Re: [RFC PATCH v3 03/37] dt-bindings: Add binding for kalray,kv3-1-intc

[Yann Sionneau]

Hello Krzysztof,

On 22/07/2024 11:51, Krzysztof Kozlowski wrote:
> On 22/07/2024 11:41, ysionneau@kalrayinc.com wrote:
>> From: Yann Sionneau <ysionneau@kalrayinc.com>
>>
>> Add binding for Kalray kv3-1 core interrupt controller.
>>
>> Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
>> Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
>> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
>> ---
>>
>> Notes:
>>
>> V2 -> V3: Fixed bindings to adhere to dt schema
>> ---
>>  .../kalray,kv3-1-intc.yaml                    | 54 +++++++++++++++++++
>>  1 file changed, 54 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml
>> new file mode 100644
>> index 0000000000000..9c8bb2c8c49dd
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml
>> @@ -0,0 +1,54 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/interrupt-controller/kalray,kv3-1-intc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Kalray kv3-1 Core Interrupt Controller
>> +
>> +maintainers:
>> +  - Jonathan Borne <jborne@kalrayinc.com>
>> +  - Julian Vetter <jvetter@kalrayinc.com>
>> +  - Yann Sionneau <ysionneau@kalrayinc.com>
>> +
>> +description: |
>> +  The Kalray Core Interrupt Controller is tightly integrated in each kv3 core
>> +  present in the Coolidge SoC.
>> +
>> +  It provides the following features:
>> +  - 32 independent interrupt sources
>> +  - 2-bit configurable priority level
>> +  - 2-bit configurable ownership level
>> +
>> +properties:
>> +  compatible:
>> +    const: kalray,kv3-1-intc
> What is the SoC name/model? You use "Kalray Core" and "Coolidge" and
> "kv3-1".

The SoC name is Coolidge , it contains "Kalray cores". Kalray being the name of the company.

The exact core name is kv3-1. The core is part of the kvx family: next core generation will most likely be called kv4 or kv4-1.

The question whether to use "coolidge" (soc name) or "kv3-1" (cpu core name) for our IPs compatible is indeed a good one, we talked about it internally at Kalray.

We ended up using "kv3-1" at the beginning of the compatible when the hw IP is very closed/tightly integrated into the CPU core.

We ended up using "coolidge" when the hw IP is just some general IP inside the SoC (like the IOMMU, the dma_noc).

The "intc" or "core intc", is very tightly integrated into the cpu core.

The "core intc" is configured directly using core registers named SFR (System Function Registers) using special SFR handling instructions. It is not memory mapped.

So we ended up using "kv3-1" in the compatible. Is this OK?

>
>> +
>> +  "#interrupt-cells":
>> +    const: 1
>> +    description:
>> +      The IRQ number.
>> +
>> +  "#address-cells":
>> +    const: 0
>> +
>> +  interrupt-controller: true
>> +
>> +additionalProperties: false
> Please put it after "required:" block. See example-schema. This applies
> everywhere.
Oops, ok, I will do this.
>
>> +
>> +required:
>> +  - compatible
>> +  - "#interrupt-cells"
>> +  - "#address-cells"
>> +  - interrupt-controller
>> +
>> +examples:
>> +  - |
>> +    intc: interrupt-controller {
> No resources? How does it talk with the hardware?
CPU configures the core intc using special instructions to access SFR (System Function Registers).
>
>> +        compatible = "kalray,kv3-1-intc";
>> +        #interrupt-cells = <1>;
>> +        #address-cells = <0>;
>> +        interrupt-controller;
>> +    };
>> +
>> +...

Regards,

-- 

Yann

Re: [RFC PATCH v3 03/37] dt-bindings: Add binding for kalray,kv3-1-intc

[Krzysztof Kozlowski]

On 31/07/2024 16:47, Yann Sionneau wrote:
>>> +description: |
>>> +  The Kalray Core Interrupt Controller is tightly integrated in each kv3 core
>>> +  present in the Coolidge SoC.
>>> +
>>> +  It provides the following features:
>>> +  - 32 independent interrupt sources
>>> +  - 2-bit configurable priority level
>>> +  - 2-bit configurable ownership level
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: kalray,kv3-1-intc
>> What is the SoC name/model? You use "Kalray Core" and "Coolidge" and
>> "kv3-1".
> 
> The SoC name is Coolidge , it contains "Kalray cores". Kalray being the name of the company.
> 
> The exact core name is kv3-1. The core is part of the kvx family: next core generation will most likely be called kv4 or kv4-1.
> 
> The question whether to use "coolidge" (soc name) or "kv3-1" (cpu core name) for our IPs compatible is indeed a good one, we talked about it internally at Kalray.
> 
> We ended up using "kv3-1" at the beginning of the compatible when the hw IP is very closed/tightly integrated into the CPU core.
> 
> We ended up using "coolidge" when the hw IP is just some general IP inside the SoC (like the IOMMU, the dma_noc).
> 
> The "intc" or "core intc", is very tightly integrated into the cpu core.
> 
> The "core intc" is configured directly using core registers named SFR (System Function Registers) using special SFR handling instructions. It is not memory mapped.
> 
> So we ended up using "kv3-1" in the compatible. Is this OK?

Comaptibles are supposed to be based on SoC model name, thus kv3-1 is
fine (based in your explanation). However unified naming in title or
description would be helpful, e.g. in title:
"Kalray Coolidge kv3-1 Core Interrupt Controller"

And all other compatibles and titles need fixing. For example in other
places you use "coolidge".

> 
>>
>>> +
>>> +  "#interrupt-cells":
>>> +    const: 1
>>> +    description:
>>> +      The IRQ number.
>>> +
>>> +  "#address-cells":
>>> +    const: 0
>>> +
>>> +  interrupt-controller: true
>>> +
>>> +additionalProperties: false
>> Please put it after "required:" block. See example-schema. This applies
>> everywhere.
> Oops, ok, I will do this.
>>
>>> +
>>> +required:
>>> +  - compatible
>>> +  - "#interrupt-cells"
>>> +  - "#address-cells"
>>> +  - interrupt-controller
>>> +
>>> +examples:
>>> +  - |
>>> +    intc: interrupt-controller {
>> No resources? How does it talk with the hardware?
> CPU configures the core intc using special instructions to access SFR (System Function Registers).

Ack.


Best regards,
Krzysztof

Re: [RFC PATCH v3 03/37] dt-bindings: Add binding for kalray,kv3-1-intc

[Rob Herring]

On Mon, Jul 22, 2024 at 11:41:14AM +0200, ysionneau@kalrayinc.com wrote:
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add binding for Kalray kv3-1 core interrupt controller.
> 
> Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3: Fixed bindings to adhere to dt schema
> ---
>  .../kalray,kv3-1-intc.yaml                    | 54 +++++++++++++++++++
>  1 file changed, 54 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml
> new file mode 100644
> index 0000000000000..9c8bb2c8c49dd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-intc.yaml
> @@ -0,0 +1,54 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/kalray,kv3-1-intc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Kalray kv3-1 Core Interrupt Controller
> +
> +maintainers:
> +  - Jonathan Borne <jborne@kalrayinc.com>
> +  - Julian Vetter <jvetter@kalrayinc.com>
> +  - Yann Sionneau <ysionneau@kalrayinc.com>
> +
> +description: |
> +  The Kalray Core Interrupt Controller is tightly integrated in each kv3 core
> +  present in the Coolidge SoC.
> +
> +  It provides the following features:
> +  - 32 independent interrupt sources
> +  - 2-bit configurable priority level
> +  - 2-bit configurable ownership level
> +
> +properties:
> +  compatible:
> +    const: kalray,kv3-1-intc

Why is this defined here and in the cpu schema? It is simple enough, I 
would just put it in the cpu schema.

Rob

[RFC PATCH v3 04/37] dt-bindings: Add binding for kalray,coolidge-apic-gic

[ysionneau]

From: Yann Sionneau <ysionneau@kalrayinc.com>

Add binding for Kalray Coolidge APIC GIC interrupt controller.

Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
---

Notes:

V2 -> V3: Fixed bindings to adhere to dt-schema
---
 .../kalray,coolidge-apic-gic.yaml             | 87 +++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-gic.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-gic.yaml
new file mode 100644
index 0000000000000..02e25256c1c1d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-gic.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/kalray,coolidge-apic-gic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kalray kv3-1 APIC-GIC
+
+maintainers:
+  - Jonathan Borne <jborne@kalrayinc.com>
+  - Julian Vetter <jvetter@kalrayinc.com>
+  - Yann Sionneau <ysionneau@kalrayinc.com>
+
+description: |
+  Each cluster in the Coolidge SoC includes an Advanced Programmable Interrupt
+  Controller (APIC) which is split in two part:
+    - a Generic Interrupt Controller (referred as APIC-GIC)
+    - a Mailbox Controller           (referred as APIC-Mailbox)
+  The APIC-GIC acts as an intermediary interrupt controller, muxing/routing
+  incoming interrupts to output interrupts connected to kvx cores interrupts lines.
+  The 139 possible input interrupt lines are organized as follow:
+     - 128 from the mailbox controller (one it per mailboxes)
+     - 1   from the NoC router
+     - 5   from IOMMUs
+     - 1   from L2 cache DMA job FIFO
+     - 1   from cluster watchdog
+     - 2   for SECC, DECC
+     - 1   from Data NoC
+  The 72 possible output interrupt lines:
+     -  68 : 4 interrupts per cores (17 cores)
+     -  1 for L2 cache controller
+     -  3 extra that are for padding
+
+properties:
+  compatible:
+    const: kalray,coolidge-apic-gic
+
+  reg:
+    maxItems: 1
+
+  "#interrupt-cells":
+    const: 1
+    description: The IRQ number.
+
+  interrupt-controller: true
+
+  interrupts-extended:
+    maxItems: 16
+    description: |
+     Specifies the interrupt line(s) in the interrupt-parent controller node;
+     valid values depend on the type of parent interrupt controller
+
+required:
+  - compatible
+  - reg
+  - "#interrupt-cells"
+  - interrupt-controller
+  - interrupts-extended
+
+additionalProperties: false
+
+examples:
+  - |
+    apic_gic: interrupt-controller@a20000 {
+        compatible = "kalray,coolidge-apic-gic";
+        reg = <0 0xa20000 0 0x12000>;
+        #interrupt-cells = <1>;
+        interrupt-controller;
+        interrupts-extended = <&core_intc0 0x4>,
+                              <&core_intc1 0x4>,
+                              <&core_intc2 0x4>,
+                              <&core_intc3 0x4>,
+                              <&core_intc4 0x4>,
+                              <&core_intc5 0x4>,
+                              <&core_intc6 0x4>,
+                              <&core_intc7 0x4>,
+                              <&core_intc8 0x4>,
+                              <&core_intc9 0x4>,
+                              <&core_intc10 0x4>,
+                              <&core_intc11 0x4>,
+                              <&core_intc12 0x4>,
+                              <&core_intc13 0x4>,
+                              <&core_intc14 0x4>,
+                              <&core_intc15 0x4>;
+    };
+
+...
-- 
2.45.2

Re: [RFC PATCH v3 04/37] dt-bindings: Add binding for kalray,coolidge-apic-gic

[Rob Herring (Arm)]

On Mon, 22 Jul 2024 11:41:15 +0200, ysionneau@kalrayinc.com wrote:
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add binding for Kalray Coolidge APIC GIC interrupt controller.
> 
> Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3: Fixed bindings to adhere to dt-schema
> ---
>  .../kalray,coolidge-apic-gic.yaml             | 87 +++++++++++++++++++
>  1 file changed, 87 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-gic.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-gic.example.dtb: interrupt-controller@a20000: reg: [[0, 10616832], [0, 73728]] is too long
	from schema $id: http://devicetree.org/schemas/interrupt-controller/kalray,coolidge-apic-gic.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240722094226.21602-5-ysionneau@kalrayinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

[RFC PATCH v3 05/37] dt-bindings: Add binding for kalray,coolidge-apic-mailbox

[ysionneau]

From: Yann Sionneau <ysionneau@kalrayinc.com>

Add binding for Kalray Coolidge APIC Mailbox interrupt-controller.

Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
---

Notes:

V2 -> V3: Fixed bindings to adhere to dt-schema
---
 .../kalray,coolidge-apic-mailbox.yaml         | 90 +++++++++++++++++++
 1 file changed, 90 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml
new file mode 100644
index 0000000000000..334b816b80583
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/kalray,coolidge-apic-mailbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kalray Coolidge APIC-Mailbox
+
+maintainers:
+  - Jonathan Borne <jborne@kalrayinc.com>
+  - Julian Vetter <jvetter@kalrayinc.com>
+  - Yann Sionneau <ysionneau@kalrayinc.com>
+
+description: |
+  Each cluster in the Coolidge SoC includes an Advanced Programmable Interrupt
+  Controller (APIC) which is split in two part:
+    - a Generic Interrupt Controller (referred as APIC-GIC)
+    - a Mailbox Controller           (referred as APIC-Mailbox)
+  The APIC-Mailbox contains 128 mailboxes of 8 bytes (size of a word),
+  this hardware block is basically a 1 KB of smart memory space.
+  Each mailbox can be independently configured with a trigger condition
+  and an input mode function.
+
+  Input mode are:
+   - write
+   - bitwise OR
+   - add
+
+  Interrupts are generated on a write when the mailbox content value
+  match the configured trigger condition.
+  Available conditions are:
+   - doorbell: always raise interruption on write
+   - match: when the mailbox's value equal the configured trigger value
+   - barrier: same as match but the mailbox's value is cleared on trigger
+   - threshold: when the mailbox's value is greater than, or equal to, the
+     configured trigger value
+
+  Since this hardware block generates IRQs based on writes to some memory
+  locations, it is both an interrupt controller and an MSI controller.
+
+properties:
+  compatible:
+    const: kalray,coolidge-apic-mailbox
+
+  reg:
+    maxItems: 1
+
+  "#interrupt-cells":
+    const: 0
+    description:
+      The IRQ number.
+
+  "#address-cells":
+    const: 0
+
+  interrupt-controller: true
+
+  interrupts:
+    maxItems: 128
+    minItems: 1
+    description: |
+     Specifies the interrupt line(s) in the interrupt-parent controller node;
+     valid values depend on the type of parent interrupt controller
+
+  msi-controller: true
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - "#interrupt-cells"
+  - "#address-cells"
+  - interrupt-controller
+  - interrupts
+  - msi-controller
+
+examples:
+  - |
+    apic_mailbox: interrupt-controller@a00000 {
+        compatible = "kalray,coolidge-apic-mailbox";
+        reg = <0 0xa00000 0 0x0f200>;
+        #interrupt-cells = <0>;
+        interrupt-controller;
+        interrupt-parent = <&apic_gic>;
+        interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>;
+        msi-controller;
+    };
+
+...
-- 
2.45.2

Re: [RFC PATCH v3 05/37] dt-bindings: Add binding for kalray,coolidge-apic-mailbox

[Rob Herring (Arm)]

On Mon, 22 Jul 2024 11:41:16 +0200, ysionneau@kalrayinc.com wrote:
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add binding for Kalray Coolidge APIC Mailbox interrupt-controller.
> 
> Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3: Fixed bindings to adhere to dt-schema
> ---
>  .../kalray,coolidge-apic-mailbox.yaml         | 90 +++++++++++++++++++
>  1 file changed, 90 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.example.dtb: interrupt-controller@a00000: reg: [[0, 10485760], [0, 61952]] is too long
	from schema $id: http://devicetree.org/schemas/interrupt-controller/kalray,coolidge-apic-mailbox.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.example.dtb: interrupt-controller@a00000: '#address-cells' is a required property
	from schema $id: http://devicetree.org/schemas/interrupt-controller/kalray,coolidge-apic-mailbox.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240722094226.21602-6-ysionneau@kalrayinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [RFC PATCH v3 05/37] dt-bindings: Add binding for kalray,coolidge-apic-mailbox

[Rob Herring]

On Mon, Jul 22, 2024 at 11:41:16AM +0200, ysionneau@kalrayinc.com wrote:
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add binding for Kalray Coolidge APIC Mailbox interrupt-controller.
> 
> Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3: Fixed bindings to adhere to dt-schema
> ---
>  .../kalray,coolidge-apic-mailbox.yaml         | 90 +++++++++++++++++++
>  1 file changed, 90 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml
> new file mode 100644
> index 0000000000000..334b816b80583
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/kalray,coolidge-apic-mailbox.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Kalray Coolidge APIC-Mailbox
> +
> +maintainers:
> +  - Jonathan Borne <jborne@kalrayinc.com>
> +  - Julian Vetter <jvetter@kalrayinc.com>
> +  - Yann Sionneau <ysionneau@kalrayinc.com>
> +
> +description: |
> +  Each cluster in the Coolidge SoC includes an Advanced Programmable Interrupt
> +  Controller (APIC) which is split in two part:
> +    - a Generic Interrupt Controller (referred as APIC-GIC)
> +    - a Mailbox Controller           (referred as APIC-Mailbox)
> +  The APIC-Mailbox contains 128 mailboxes of 8 bytes (size of a word),
> +  this hardware block is basically a 1 KB of smart memory space.
> +  Each mailbox can be independently configured with a trigger condition
> +  and an input mode function.
> +
> +  Input mode are:
> +   - write
> +   - bitwise OR
> +   - add
> +
> +  Interrupts are generated on a write when the mailbox content value
> +  match the configured trigger condition.
> +  Available conditions are:
> +   - doorbell: always raise interruption on write
> +   - match: when the mailbox's value equal the configured trigger value
> +   - barrier: same as match but the mailbox's value is cleared on trigger
> +   - threshold: when the mailbox's value is greater than, or equal to, the
> +     configured trigger value
> +
> +  Since this hardware block generates IRQs based on writes to some memory
> +  locations, it is both an interrupt controller and an MSI controller.
> +
> +properties:
> +  compatible:
> +    const: kalray,coolidge-apic-mailbox
> +
> +  reg:
> +    maxItems: 1
> +
> +  "#interrupt-cells":
> +    const: 0
> +    description:
> +      The IRQ number.
> +
> +  "#address-cells":
> +    const: 0
> +
> +  interrupt-controller: true
> +
> +  interrupts:
> +    maxItems: 128
> +    minItems: 1
> +    description: |
> +     Specifies the interrupt line(s) in the interrupt-parent controller node;
> +     valid values depend on the type of parent interrupt controller

Your description applies to all 'interrupts' properties and is therefore 
redundant. What you should explain is what are the 1-128 possible 
interrupts. Normally, you have to list each one out unless they are all 
instances of the same type of interrupt.

> +
> +  msi-controller: true

"#msi-cells" should be specified too.

> +
> +additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#interrupt-cells"
> +  - "#address-cells"
> +  - interrupt-controller
> +  - interrupts
> +  - msi-controller
> +
> +examples:
> +  - |
> +    apic_mailbox: interrupt-controller@a00000 {
> +        compatible = "kalray,coolidge-apic-mailbox";
> +        reg = <0 0xa00000 0 0x0f200>;
> +        #interrupt-cells = <0>;
> +        interrupt-controller;
> +        interrupt-parent = <&apic_gic>;
> +        interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>;
> +        msi-controller;
> +    };
> +
> +...
> -- 
> 2.45.2
> 
> 
> 
> 
> 

Re: [RFC PATCH v3 05/37] dt-bindings: Add binding for kalray,coolidge-apic-mailbox

[Yann Sionneau]

Hello Rob,

Le 7/22/24 à 22:47, Rob Herring a écrit :
> On Mon, Jul 22, 2024 at 11:41:16AM +0200, ysionneau@kalrayinc.com wrote:
>> From: Yann Sionneau <ysionneau@kalrayinc.com>
>>
>> Add binding for Kalray Coolidge APIC Mailbox interrupt-controller.
>>
>> Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
>> Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
>> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
>> ---
>>
>> Notes:
>>
>> V2 -> V3: Fixed bindings to adhere to dt-schema
>> ---
>>  .../kalray,coolidge-apic-mailbox.yaml         | 90 +++++++++++++++++++
>>  1 file changed, 90 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml
>> new file mode 100644
>> index 0000000000000..334b816b80583
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml
>> [...]
>> +
>> +  interrupts:
>> +    maxItems: 128
>> +    minItems: 1
>> +    description: |
>> +     Specifies the interrupt line(s) in the interrupt-parent controller node;
>> +     valid values depend on the type of parent interrupt controller
> Your description applies to all 'interrupts' properties and is therefore 
> redundant. What you should explain is what are the 1-128 possible 
> interrupts. Normally, you have to list each one out unless they are all 
> instances of the same type of interrupt.

Oops I understand what you mean, this description could work on any .yaml indeed.

I propose this instead:

Each of the 128 mailboxes generates an interrupt on the APIC-GIC.

The interrupt is triggered according to the mailbox input mode and

its trigger condition.

>> +
>> +  msi-controller: true
> "#msi-cells" should be specified too.
Ok.
>
>> +
>> +additionalProperties: false
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - "#interrupt-cells"
>> +  - "#address-cells"
>> +  - interrupt-controller
>> +  - interrupts
>> +  - msi-controller
>> +
>> +examples:
>> +  - |
>> +    apic_mailbox: interrupt-controller@a00000 {
>> +        compatible = "kalray,coolidge-apic-mailbox";
>> +        reg = <0 0xa00000 0 0x0f200>;
>> +        #interrupt-cells = <0>;
>> +        interrupt-controller;
>> +        interrupt-parent = <&apic_gic>;
>> +        interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>;
>> +        msi-controller;
>> +    };
>> +
>> +...
>> -- 
>> 2.45.2
>>
>>
>>
>>
>>
>

[RFC PATCH v3 06/37] dt-bindings: Add binding for kalray,coolidge-itgen

[ysionneau]

From: Yann Sionneau <ysionneau@kalrayinc.com>

Add binding for Kalray Coolidge Interrupt Generator.

Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
---

Notes:

V2 -> V3: Fixed bindings to adhere to dt-schema
---
 .../kalray,coolidge-itgen.yaml                | 55 +++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-itgen.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-itgen.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-itgen.yaml
new file mode 100644
index 0000000000000..222cacb5cbea4
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-itgen.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/kalray,coolidge-itgen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kalray Coolidge SoC Interrupt Generator (ITGEN)
+
+maintainers:
+  - Jonathan Borne <jborne@kalrayinc.com>
+  - Julian Vetter <jvetter@kalrayinc.com>
+  - Yann Sionneau <ysionneau@kalrayinc.com>
+
+description: |
+  The Interrupt Generator (ITGEN) is an interrupt controller block.
+  It's purpose is to convert IRQ lines coming from SoC peripherals into writes
+  on the AXI bus. The ITGEN intended purpose is to write into the APIC mailboxes.
+
+properties:
+  compatible:
+    const: kalray,coolidge-itgen
+
+  reg:
+    maxItems: 1
+
+  "#interrupt-cells":
+    const: 2
+    description: |
+      - 1st cell is for the IRQ number
+      - 2nd cell is for the trigger type as defined dt-bindings/interrupt-controller/irq.h
+
+  interrupt-controller: true
+
+  msi-parent: true
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - "#interrupt-cells"
+  - interrupt-controller
+  - msi-parent
+
+examples:
+  - |
+    itgen: interrupt-controller@27000000 {
+        compatible = "kalray,coolidge-itgen";
+        reg = <0 0x27000000 0 0x1104>;
+        #interrupt-cells = <2>;
+        interrupt-controller;
+        msi-parent = <&apic_mailbox>;
+    };
+
+...
-- 
2.45.2

Re: [RFC PATCH v3 06/37] dt-bindings: Add binding for kalray,coolidge-itgen

[Rob Herring (Arm)]

On Mon, 22 Jul 2024 11:41:17 +0200, ysionneau@kalrayinc.com wrote:
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add binding for Kalray Coolidge Interrupt Generator.
> 
> Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3: Fixed bindings to adhere to dt-schema
> ---
>  .../kalray,coolidge-itgen.yaml                | 55 +++++++++++++++++++
>  1 file changed, 55 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-itgen.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-itgen.example.dtb: interrupt-controller@27000000: reg: [[0, 654311424], [0, 4356]] is too long
	from schema $id: http://devicetree.org/schemas/interrupt-controller/kalray,coolidge-itgen.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240722094226.21602-7-ysionneau@kalrayinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

[RFC PATCH v3 07/37] dt-bindings: Add binding for kalray,coolidge-ipi-ctrl

[ysionneau]

From: Yann Sionneau <ysionneau@kalrayinc.com>

Add binding for Kalray Coolidge IPI controller.

Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
---

Notes:

V2 -> V3:
- fixed bindings to adhere to dt-schema
- moved to interrupt-controller directory, like the related driver
---
 .../kalray,coolidge-ipi-ctrl.yaml             | 79 +++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml
new file mode 100644
index 0000000000000..91e3afe4f1ca5
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kalray Coolidge SoC Inter-Processor Interrupt Controller (IPI)
+
+maintainers:
+  - Jonathan Borne <jborne@kalrayinc.com>
+  - Julian Vetter <jvetter@kalrayinc.com>
+  - Yann Sionneau <ysionneau@kalrayinc.com>
+
+description: |
+  The Inter-Processor Interrupt Controller (IPI) provides a fast synchronization
+  mechanism to the software. It exposes eight independent set of registers that
+  can be use to notify each processor in the cluster.
+  A set of registers contains two 32-bit registers:
+    - 17-bit interrupt control, one bit per core, raise an interrupt on write
+    - 17-bit mask, one per core, to enable interrupts
+
+  Bit at offsets 0 to 15 selects cores in the cluster, respectively PE0 to PE15,
+  while bit at offset 16 is for the cluster Resource Manager (RM) core.
+
+  The eight output interrupts are connected to each processor core interrupt
+  controller (intc).
+
+properties:
+  compatible:
+    const: kalray,coolidge-ipi-ctrl
+
+  reg:
+    maxItems: 1
+
+  interrupts-extended:
+    maxItems: 16
+    description: |
+      Specifies the interrupt line the IPI controller will raise on the core INTC.
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 0
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+  - interrupt-controller
+  - '#interrupt-cells'
+
+examples:
+  - |
+    ipi: inter-processor-interrupt@ad0000 {
+        compatible = "kalray,coolidge-ipi-ctrl";
+        reg = <0x00 0xad0000 0x00 0x1000>;
+        #interrupt-cells = <0>;
+        interrupt-controller;
+        interrupts-extended = <&core_intc0 24>,
+                              <&core_intc1 24>,
+                              <&core_intc2 24>,
+                              <&core_intc3 24>,
+                              <&core_intc4 24>,
+                              <&core_intc5 24>,
+                              <&core_intc6 24>,
+                              <&core_intc7 24>,
+                              <&core_intc8 24>,
+                              <&core_intc9 24>,
+                              <&core_intc10 24>,
+                              <&core_intc11 24>,
+                              <&core_intc12 24>,
+                              <&core_intc13 24>,
+                              <&core_intc14 24>,
+                              <&core_intc15 24>;
+    };
+
+...
-- 
2.45.2

Re: [RFC PATCH v3 07/37] dt-bindings: Add binding for kalray,coolidge-ipi-ctrl

[Rob Herring (Arm)]

On Mon, 22 Jul 2024 11:41:18 +0200, ysionneau@kalrayinc.com wrote:
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add binding for Kalray Coolidge IPI controller.
> 
> Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3:
> - fixed bindings to adhere to dt-schema
> - moved to interrupt-controller directory, like the related driver
> ---
>  .../kalray,coolidge-ipi-ctrl.yaml             | 79 +++++++++++++++++++
>  1 file changed, 79 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.example.dtb: inter-processor-interrupt@ad0000: reg: [[0, 11337728], [0, 4096]] is too long
	from schema $id: http://devicetree.org/schemas/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240722094226.21602-8-ysionneau@kalrayinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [RFC PATCH v3 07/37] dt-bindings: Add binding for kalray,coolidge-ipi-ctrl

[Rob Herring]

On Mon, Jul 22, 2024 at 11:41:18AM +0200, ysionneau@kalrayinc.com wrote:
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add binding for Kalray Coolidge IPI controller.
> 
> Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3:
> - fixed bindings to adhere to dt-schema
> - moved to interrupt-controller directory, like the related driver
> ---
>  .../kalray,coolidge-ipi-ctrl.yaml             | 79 +++++++++++++++++++
>  1 file changed, 79 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml
> new file mode 100644
> index 0000000000000..91e3afe4f1ca5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml
> @@ -0,0 +1,79 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Kalray Coolidge SoC Inter-Processor Interrupt Controller (IPI)
> +
> +maintainers:
> +  - Jonathan Borne <jborne@kalrayinc.com>
> +  - Julian Vetter <jvetter@kalrayinc.com>
> +  - Yann Sionneau <ysionneau@kalrayinc.com>
> +
> +description: |
> +  The Inter-Processor Interrupt Controller (IPI) provides a fast synchronization
> +  mechanism to the software. It exposes eight independent set of registers that
> +  can be use to notify each processor in the cluster.
> +  A set of registers contains two 32-bit registers:
> +    - 17-bit interrupt control, one bit per core, raise an interrupt on write
> +    - 17-bit mask, one per core, to enable interrupts
> +
> +  Bit at offsets 0 to 15 selects cores in the cluster, respectively PE0 to PE15,
> +  while bit at offset 16 is for the cluster Resource Manager (RM) core.
> +
> +  The eight output interrupts are connected to each processor core interrupt
> +  controller (intc).

It says there are 16 interrupt outputs below...

> +
> +properties:
> +  compatible:
> +    const: kalray,coolidge-ipi-ctrl
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts-extended:
> +    maxItems: 16
> +    description: |
> +      Specifies the interrupt line the IPI controller will raise on the core INTC.
> +
> +  interrupt-controller: true
> +
> +  '#interrupt-cells':
> +    const: 0
> +
> +additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts-extended
> +  - interrupt-controller
> +  - '#interrupt-cells'
> +
> +examples:
> +  - |
> +    ipi: inter-processor-interrupt@ad0000 {
> +        compatible = "kalray,coolidge-ipi-ctrl";
> +        reg = <0x00 0xad0000 0x00 0x1000>;
> +        #interrupt-cells = <0>;
> +        interrupt-controller;
> +        interrupts-extended = <&core_intc0 24>,
> +                              <&core_intc1 24>,
> +                              <&core_intc2 24>,
> +                              <&core_intc3 24>,
> +                              <&core_intc4 24>,
> +                              <&core_intc5 24>,
> +                              <&core_intc6 24>,
> +                              <&core_intc7 24>,
> +                              <&core_intc8 24>,
> +                              <&core_intc9 24>,
> +                              <&core_intc10 24>,
> +                              <&core_intc11 24>,
> +                              <&core_intc12 24>,
> +                              <&core_intc13 24>,
> +                              <&core_intc14 24>,
> +                              <&core_intc15 24>;
> +    };
> +
> +...
> -- 
> 2.45.2
> 
> 
> 
> 
> 

Re: [RFC PATCH v3 07/37] dt-bindings: Add binding for kalray,coolidge-ipi-ctrl

[Yann Sionneau]

Hello Rob,

On 22/07/2024 22:50, Rob Herring wrote:
> On Mon, Jul 22, 2024 at 11:41:18AM +0200, ysionneau@kalrayinc.com wrote:
>> From: Yann Sionneau <ysionneau@kalrayinc.com>
>>
>> Add binding for Kalray Coolidge IPI controller.
>>
>> Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
>> Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
>> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
>> ---
>>
>> Notes:
>>
>> V2 -> V3:
>> - fixed bindings to adhere to dt-schema
>> - moved to interrupt-controller directory, like the related driver
>> ---
>>  .../kalray,coolidge-ipi-ctrl.yaml             | 79 +++++++++++++++++++
>>  1 file changed, 79 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml
>> new file mode 100644
>> index 0000000000000..91e3afe4f1ca5
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml
>> [...]
>> +
>> +description: |
>> +  The Inter-Processor Interrupt Controller (IPI) provides a fast synchronization
>> +  mechanism to the software. It exposes eight independent set of registers that
>> +  can be use to notify each processor in the cluster.
>> +  A set of registers contains two 32-bit registers:
>> +    - 17-bit interrupt control, one bit per core, raise an interrupt on write
>> +    - 17-bit mask, one per core, to enable interrupts
>> +
>> +  Bit at offsets 0 to 15 selects cores in the cluster, respectively PE0 to PE15,
>> +  while bit at offset 16 is for the cluster Resource Manager (RM) core.
>> +
>> +  The eight output interrupts are connected to each processor core interrupt
>> +  controller (intc).
> It says there are 16 interrupt outputs below...

In reality, the ipi-ctrl hw can generate 8 interrupts per core, and there are 16 PE (Processing Element) cores and 1 RM (Resource Manager) core.

But, so far, our kernel port only uses 1 interrupt per core (for IPI) and only for the 16 PE (the RM does not run Linux).

Should we describe in the yaml all the hw can do?

Or only what we do use?

>
>> [...]
>> +
>> +  interrupts-extended:
>> +    maxItems: 16
>> +    description: |
>> +      Specifies the interrupt line the IPI controller will raise on the core INTC.
>> +
>> + [...]
>> +
>> +examples:
>> +  - |
>> +    ipi: inter-processor-interrupt@ad0000 {
>> +        compatible = "kalray,coolidge-ipi-ctrl";
>> +        reg = <0x00 0xad0000 0x00 0x1000>;
>> +        #interrupt-cells = <0>;
>> +        interrupt-controller;
>> +        interrupts-extended = <&core_intc0 24>,
>> +                              <&core_intc1 24>,
>> +                              <&core_intc2 24>,
>> +                              <&core_intc3 24>,
>> +                              <&core_intc4 24>,
>> +                              <&core_intc5 24>,
>> +                              <&core_intc6 24>,
>> +                              <&core_intc7 24>,
>> +                              <&core_intc8 24>,
>> +                              <&core_intc9 24>,
>> +                              <&core_intc10 24>,
>> +                              <&core_intc11 24>,
>> +                              <&core_intc12 24>,
>> +                              <&core_intc13 24>,
>> +                              <&core_intc14 24>,
>> +                              <&core_intc15 24>;
>> +    };
>> +
>> +...

Thanks for your review!

Regards,

-- 

Yann

[RFC PATCH v3 08/37] dt-bindings: Add binding for kalray,coolidge-dsu-clock

[ysionneau]

From: Yann Sionneau <ysionneau@kalrayinc.com>

Add binding for Kalray Coolidge DSU (Debug System Unit) clock.

Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
---

Notes:

V2 -> V3: New patch
---
 .../clock/kalray,coolidge-dsu-clock.yaml      | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/kalray,coolidge-dsu-clock.yaml

diff --git a/Documentation/devicetree/bindings/clock/kalray,coolidge-dsu-clock.yaml b/Documentation/devicetree/bindings/clock/kalray,coolidge-dsu-clock.yaml
new file mode 100644
index 0000000000000..a7f6239b17c12
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/kalray,coolidge-dsu-clock.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/kalray,coolidge-dsu-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kalray Coolidge DSU Clock
+
+maintainers:
+  - Jonathan Borne <jborne@kalrayinc.com>
+  - Julian Vetter <jvetter@kalrayinc.com>
+  - Yann Sionneau <ysionneau@kalrayinc.com>
+
+description: |
+  DSU Clock is a free running counter that runs at Cluster clock frequency.
+
+properties:
+  compatible:
+    const: kalray,coolidge-dsu-clock
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+required:
+  - reg
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    dsu_clock@a44180 {
+        compatible = "kalray,coolidge-dsu-clock";
+        reg = <0x00 0xa44180 0x00 0x08>;
+        clocks = <&core_clk>;
+    };
-- 
2.45.2

Re: [RFC PATCH v3 08/37] dt-bindings: Add binding for kalray,coolidge-dsu-clock

[Rob Herring (Arm)]

On Mon, 22 Jul 2024 11:41:19 +0200, ysionneau@kalrayinc.com wrote:
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add binding for Kalray Coolidge DSU (Debug System Unit) clock.
> 
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3: New patch
> ---
>  .../clock/kalray,coolidge-dsu-clock.yaml      | 39 +++++++++++++++++++
>  1 file changed, 39 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/kalray,coolidge-dsu-clock.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/kalray,coolidge-dsu-clock.example.dtb: dsu_clock@a44180: reg: [[0, 10764672], [0, 8]] is too long
	from schema $id: http://devicetree.org/schemas/clock/kalray,coolidge-dsu-clock.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240722094226.21602-9-ysionneau@kalrayinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [RFC PATCH v3 08/37] dt-bindings: Add binding for kalray,coolidge-dsu-clock

[Stephen Boyd]

Quoting ysionneau@kalrayinc.com (2024-07-22 02:41:19)
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add binding for Kalray Coolidge DSU (Debug System Unit) clock.
> 
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3: New patch
> ---
>  .../clock/kalray,coolidge-dsu-clock.yaml      | 39 +++++++++++++++++++
>  1 file changed, 39 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/kalray,coolidge-dsu-clock.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/kalray,coolidge-dsu-clock.yaml b/Documentation/devicetree/bindings/clock/kalray,coolidge-dsu-clock.yaml
> new file mode 100644
> index 0000000000000..a7f6239b17c12
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/kalray,coolidge-dsu-clock.yaml
> @@ -0,0 +1,39 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/kalray,coolidge-dsu-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Kalray Coolidge DSU Clock

Nobody knows what DSU is here. Just spell it out and then put the
acronym:

	Debug System Unit (DSU)

> +
> +maintainers:
> +  - Jonathan Borne <jborne@kalrayinc.com>
> +  - Julian Vetter <jvetter@kalrayinc.com>
> +  - Yann Sionneau <ysionneau@kalrayinc.com>
> +
> +description: |
> +  DSU Clock is a free running counter that runs at Cluster clock frequency.
> +
> +properties:
> +  compatible:
> +    const: kalray,coolidge-dsu-clock
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +required:
> +  - reg
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    dsu_clock@a44180 {
> +        compatible = "kalray,coolidge-dsu-clock";
> +        reg = <0x00 0xa44180 0x00 0x08>;

This looks like it's part of some bigger module, possible DSU in
general. Is that true? If so, please implement the binding for DSU
instead.

[RFC PATCH v3 09/37] dt-bindings: Add binding for kalray,kv3-1-timer

[ysionneau]

From: Yann Sionneau <ysionneau@kalrayinc.com>

Add binding for Kalray kv3-1 core timer.

Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
---

Notes:

V2 -> V3: New patch
---
 .../bindings/timer/kalray,kv3-1-timer.yaml    | 57 +++++++++++++++++++
 1 file changed, 57 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/kalray,kv3-1-timer.yaml

diff --git a/Documentation/devicetree/bindings/timer/kalray,kv3-1-timer.yaml b/Documentation/devicetree/bindings/timer/kalray,kv3-1-timer.yaml
new file mode 100644
index 0000000000000..1932f28a05a18
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/kalray,kv3-1-timer.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/kalray,kv3-1-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kalray kv3-1 core timer
+
+maintainers:
+  - Jonathan Borne <jborne@kalrayinc.com>
+  - Julian Vetter <jvetter@kalrayinc.com>
+  - Yann Sionneau <ysionneau@kalrayinc.com>
+
+description: |
+  Timer tightly coupled to the kv3-1 processor core. It is configured via core SFR.
+  It triggers an interrupt directly on core-intc.
+
+properties:
+  compatible:
+    const: kalray,kv3-1-timer
+
+  interrupts-extended:
+    maxItems: 16
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - interrupts-extended
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    core_timer {
+        compatible = "kalray,kv3-1-timer";
+        clocks = <&core_clk>;
+        interrupts-extended = <&core_intc0 0>,
+                              <&core_intc1 0>,
+                              <&core_intc2 0>,
+                              <&core_intc3 0>,
+                              <&core_intc4 0>,
+                              <&core_intc5 0>,
+                              <&core_intc6 0>,
+                              <&core_intc7 0>,
+                              <&core_intc8 0>,
+                              <&core_intc9 0>,
+                              <&core_intc10 0>,
+                              <&core_intc11 0>,
+                              <&core_intc12 0>,
+                              <&core_intc13 0>,
+                              <&core_intc14 0>,
+                              <&core_intc15 0>;
+    };
+
-- 
2.45.2

Re: [RFC PATCH v3 09/37] dt-bindings: Add binding for kalray,kv3-1-timer

[Rob Herring]

On Mon, Jul 22, 2024 at 11:41:20AM +0200, ysionneau@kalrayinc.com wrote:
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add binding for Kalray kv3-1 core timer.
> 
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3: New patch
> ---
>  .../bindings/timer/kalray,kv3-1-timer.yaml    | 57 +++++++++++++++++++
>  1 file changed, 57 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/timer/kalray,kv3-1-timer.yaml
> 
> diff --git a/Documentation/devicetree/bindings/timer/kalray,kv3-1-timer.yaml b/Documentation/devicetree/bindings/timer/kalray,kv3-1-timer.yaml
> new file mode 100644
> index 0000000000000..1932f28a05a18
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/kalray,kv3-1-timer.yaml
> @@ -0,0 +1,57 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/kalray,kv3-1-timer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Kalray kv3-1 core timer
> +
> +maintainers:
> +  - Jonathan Borne <jborne@kalrayinc.com>
> +  - Julian Vetter <jvetter@kalrayinc.com>
> +  - Yann Sionneau <ysionneau@kalrayinc.com>
> +
> +description: |

Don't need '|' if no formatting.

> +  Timer tightly coupled to the kv3-1 processor core. It is configured via core SFR.
> +  It triggers an interrupt directly on core-intc.
> +
> +properties:
> +  compatible:
> +    const: kalray,kv3-1-timer
> +
> +  interrupts-extended:
> +    maxItems: 16

I assume this is 1 interrupt per core, but I shouldn't have to assume 
that.

Only 16 cores supported?

> +
> +  clocks:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - interrupts-extended
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    core_timer {
> +        compatible = "kalray,kv3-1-timer";
> +        clocks = <&core_clk>;
> +        interrupts-extended = <&core_intc0 0>,
> +                              <&core_intc1 0>,
> +                              <&core_intc2 0>,
> +                              <&core_intc3 0>,
> +                              <&core_intc4 0>,
> +                              <&core_intc5 0>,
> +                              <&core_intc6 0>,
> +                              <&core_intc7 0>,
> +                              <&core_intc8 0>,
> +                              <&core_intc9 0>,
> +                              <&core_intc10 0>,
> +                              <&core_intc11 0>,
> +                              <&core_intc12 0>,
> +                              <&core_intc13 0>,
> +                              <&core_intc14 0>,
> +                              <&core_intc15 0>;
> +    };
> +
> -- 
> 2.45.2
> 
> 
> 
> 
> 

[RFC PATCH v3 10/37] dt-bindings: kalray: Add CPU bindings for Kalray kvx

[ysionneau]

From: Yann Sionneau <ysionneau@kalrayinc.com>

Add Kalray kvx CPU bindings.

Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
---

Notes:

V2 -> V3: New patch
---
 .../devicetree/bindings/kalray/cpus.yaml      | 105 ++++++++++++++++++
 1 file changed, 105 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/kalray/cpus.yaml

diff --git a/Documentation/devicetree/bindings/kalray/cpus.yaml b/Documentation/devicetree/bindings/kalray/cpus.yaml
new file mode 100644
index 0000000000000..cdf1f10573da7
--- /dev/null
+++ b/Documentation/devicetree/bindings/kalray/cpus.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/kalray/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kalray CPUs
+
+maintainers:
+  - Jonathan Borne <jborne@kalrayinc.com>
+  - Julian Vetter <jvetter@kalrayinc.com>
+  - Yann Sionneau <ysionneau@kalrayinc.com>
+
+allOf:
+  - $ref: /schemas/cpu.yaml#
+
+properties:
+  reg:
+    maxItems: 1
+    description: |
+      Contains the CPU number.
+
+  compatible:
+    oneOf:
+      - items:
+          - const: kalray,kv3-1-pe
+          - const: kalray,kv3-pe
+
+  clocks:
+    maxItems: 1
+
+  enable-method:
+    const: "kalray,coolidge-pwr-ctrl"
+
+  interrupt-controller:
+    type: object
+    additionalProperties: false
+    description: Describes the CPU's local interrupt controller
+
+    properties:
+      '#interrupt-cells':
+        const: 1
+
+      compatible:
+        const: kalray,kv3-1-intc
+
+      interrupt-controller: true
+
+      '#address-cells':
+        const: 0
+
+    required:
+      - compatible
+      - '#interrupt-cells'
+      - '#address-cells'
+      - interrupt-controller
+
+if:
+  properties:
+    reg:
+      const: 0
+then:
+  required:
+    - clocks
+
+required:
+  - reg
+  - compatible
+  - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+  - |
+
+    cpus {
+        #size-cells = <0>;
+        #address-cells = <1>;
+
+       cpu@0 {
+         compatible = "kalray,kv3-1-pe";
+         device_type = "cpu";
+         reg = <0>;
+         clocks = <&core_clk>;
+         cpu_intc0: interrupt-controller {
+           compatible = "kalray,kv3-1-intc";
+           #interrupt-cells = <1>;
+           #address-cells = <0>;
+           interrupt-controller;
+         };
+       };
+
+
+       cpu@1 {
+         compatible = "kalray,kv3-1-pe";
+         device_type = "cpu";
+         reg = <1>;
+         cpu_intc1: interrupt-controller {
+           compatible = "kalray,kv3-1-intc";
+           #interrupt-cells = <1>;
+           #address-cells = <0>;
+           interrupt-controller;
+         };
+       };
+    };
-- 
2.45.2

Re: [RFC PATCH v3 10/37] dt-bindings: kalray: Add CPU bindings for Kalray kvx

[Rob Herring (Arm)]

On Mon, 22 Jul 2024 11:41:21 +0200, ysionneau@kalrayinc.com wrote:
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add Kalray kvx CPU bindings.
> 
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3: New patch
> ---
>  .../devicetree/bindings/kalray/cpus.yaml      | 105 ++++++++++++++++++
>  1 file changed, 105 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/kalray/cpus.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/kalray/cpus.example.dtb: cpu@0: compatible: ['kalray,kv3-1-pe'] is too short
	from schema $id: http://devicetree.org/schemas/kalray/cpus.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/kalray/cpus.example.dtb: cpu@1: compatible: ['kalray,kv3-1-pe'] is too short
	from schema $id: http://devicetree.org/schemas/kalray/cpus.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240722094226.21602-11-ysionneau@kalrayinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [RFC PATCH v3 10/37] dt-bindings: kalray: Add CPU bindings for Kalray kvx

[Rob Herring]

On Mon, Jul 22, 2024 at 11:41:21AM +0200, ysionneau@kalrayinc.com wrote:
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add Kalray kvx CPU bindings.
> 
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3: New patch
> ---
>  .../devicetree/bindings/kalray/cpus.yaml      | 105 ++++++++++++++++++
>  1 file changed, 105 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/kalray/cpus.yaml
> 
> diff --git a/Documentation/devicetree/bindings/kalray/cpus.yaml b/Documentation/devicetree/bindings/kalray/cpus.yaml
> new file mode 100644
> index 0000000000000..cdf1f10573da7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/kalray/cpus.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/kalray/cpus.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Kalray CPUs
> +
> +maintainers:
> +  - Jonathan Borne <jborne@kalrayinc.com>
> +  - Julian Vetter <jvetter@kalrayinc.com>
> +  - Yann Sionneau <ysionneau@kalrayinc.com>
> +
> +allOf:
> +  - $ref: /schemas/cpu.yaml#
> +
> +properties:
> +  reg:
> +    maxItems: 1
> +    description: |

Don't need '|' if no formatting.

> +      Contains the CPU number.

Ideally this is tied to something in the h/w and not just made up. If 
so, detail that here.

> +
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: kalray,kv3-1-pe
> +          - const: kalray,kv3-pe

What's the difference between these 2?

> +
> +  clocks:
> +    maxItems: 1
> +
> +  enable-method:
> +    const: "kalray,coolidge-pwr-ctrl"

Why is this needed if there's only 1 possible option?

It doesn't need quotes either.

> +
> +  interrupt-controller:
> +    type: object
> +    additionalProperties: false
> +    description: Describes the CPU's local interrupt controller
> +
> +    properties:
> +      '#interrupt-cells':
> +        const: 1
> +
> +      compatible:
> +        const: kalray,kv3-1-intc
> +
> +      interrupt-controller: true
> +
> +      '#address-cells':
> +        const: 0
> +
> +    required:
> +      - compatible
> +      - '#interrupt-cells'
> +      - '#address-cells'
> +      - interrupt-controller
> +
> +if:
> +  properties:
> +    reg:
> +      const: 0
> +then:
> +  required:
> +    - clocks
> +
> +required:
> +  - reg
> +  - compatible
> +  - interrupt-controller
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +
> +    cpus {
> +        #size-cells = <0>;
> +        #address-cells = <1>;
> +
> +       cpu@0 {
> +         compatible = "kalray,kv3-1-pe";
> +         device_type = "cpu";
> +         reg = <0>;
> +         clocks = <&core_clk>;
> +         cpu_intc0: interrupt-controller {
> +           compatible = "kalray,kv3-1-intc";
> +           #interrupt-cells = <1>;
> +           #address-cells = <0>;
> +           interrupt-controller;
> +         };
> +       };
> +
> +

One blank line.

> +       cpu@1 {
> +         compatible = "kalray,kv3-1-pe";
> +         device_type = "cpu";
> +         reg = <1>;
> +         cpu_intc1: interrupt-controller {
> +           compatible = "kalray,kv3-1-intc";
> +           #interrupt-cells = <1>;
> +           #address-cells = <0>;
> +           interrupt-controller;
> +         };
> +       };
> +    };
> -- 
> 2.45.2
> 
> 
> 
> 
> 

[RFC PATCH v3 11/37] dt-bindings: kalray: Add Kalray SoC board compatibles

[ysionneau]

From: Yann Sionneau <ysionneau@kalrayinc.com>

Add Kalray SoC board bindings.

Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
---

Notes:

V2 -> V3: New patch
---
 .../devicetree/bindings/kalray/kalray.yaml    | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/kalray/kalray.yaml

diff --git a/Documentation/devicetree/bindings/kalray/kalray.yaml b/Documentation/devicetree/bindings/kalray/kalray.yaml
new file mode 100644
index 0000000000000..3da817da9b2fe
--- /dev/null
+++ b/Documentation/devicetree/bindings/kalray/kalray.yaml
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/kalray/kalray.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kalray SoC-based boards
+
+maintainers:
+  - Jonathan Borne <jborne@kalrayinc.com>
+  - Julian Vetter <jvetter@kalrayinc.com>
+  - Yann Sionneau <ysionneau@kalrayinc.com>
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: Kalray Coolidge SoC on qemu
+        const: kalray,coolidge-qemu
+
+additionalProperties: true
-- 
2.45.2

[RFC PATCH v3 36/37] kvx: dts: DeviceTree for qemu emulated Coolidge SoC

[ysionneau]

From: Yann Sionneau <ysionneau@kalrayinc.com>

Add device tree for QEMU that emulates a Coolidge V1 SoC.

Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
---

Notes:

V2 -> V3: New patch
---
 arch/kvx/boot/dts/Makefile          |   1 +
 arch/kvx/boot/dts/coolidge-qemu.dts | 444 ++++++++++++++++++++++++++++
 2 files changed, 445 insertions(+)
 create mode 100644 arch/kvx/boot/dts/Makefile
 create mode 100644 arch/kvx/boot/dts/coolidge-qemu.dts

diff --git a/arch/kvx/boot/dts/Makefile b/arch/kvx/boot/dts/Makefile
new file mode 100644
index 0000000000000..cd27ceb7a6cce
--- /dev/null
+++ b/arch/kvx/boot/dts/Makefile
@@ -0,0 +1 @@
+dtb-y += coolidge-qemu.dtb
diff --git a/arch/kvx/boot/dts/coolidge-qemu.dts b/arch/kvx/boot/dts/coolidge-qemu.dts
new file mode 100644
index 0000000000000..1d5af0d2e687d
--- /dev/null
+++ b/arch/kvx/boot/dts/coolidge-qemu.dts
@@ -0,0 +1,444 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/dts-v1/;
+/*
+ * Copyright (C) 2024, Kalray Inc.
+ */
+
+/ {
+	model = "Kalray Coolidge processor (QEMU)";
+	compatible = "kalray,coolidge-qemu";
+	#address-cells = <0x02>;
+	#size-cells = <0x02>;
+
+	chosen {
+		stdout-path = "/axi/serial@20210000";
+	};
+
+	memory@100000000 {
+		phandle = <0x40>;
+		reg = <0x01 0x00 0x00 0x8000000>;
+		device_type = "memory";
+	};
+
+	axi {
+		compatible = "simple-bus";
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+
+		virtio-mmio@30003c00 {
+			compatible = "virtio,mmio";
+			reg = <0x00 0x30003c00 0x00 0x200>;
+			interrupt-parent = <&itgen0>;
+			interrupts = <0x9e 0x04>;
+		};
+
+		virtio-mmio@30003e00 {
+			compatible = "virtio,mmio";
+			reg = <0x00 0x30003e00 0x00 0x200>;
+			interrupt-parent = <&itgen0>;
+			interrupts = <0x9f 0x04>;
+		};
+
+		itgen0: itgen_soc_periph0@27000000 {
+			compatible = "kalray,coolidge-itgen";
+			reg = <0x00 0x27000000 0x00 0x1104>;
+			msi-parent = <&apic_mailbox>;
+			#interrupt-cells = <0x02>;
+			interrupt-controller;
+		};
+
+		serial@20210000 {
+			reg-shift = <0x02>;
+			reg-io-width = <0x04>;
+			clocks = <&ref_clk>;
+			interrupts = <0x29 0x04>;
+			interrupt-parent = <&itgen0>;
+			reg = <0x00 0x20210000 0x00 0x100>;
+			compatible = "snps,dw-apb-uart";
+		};
+
+		serial@20211000 {
+			reg-shift = <0x02>;
+			reg-io-width = <0x04>;
+			phandle = <0x3c>;
+			clocks = <&ref_clk>;
+			interrupts = <0x2a 0x04>;
+			interrupt-parent = <&itgen0>;
+			reg = <0x00 0x20211000 0x00 0x100>;
+			compatible = "snps,dw-apb-uart";
+		};
+
+		serial@20212000 {
+			reg-shift = <0x02>;
+			reg-io-width = <0x04>;
+			phandle = <0x3b>;
+			clocks = <&ref_clk>;
+			interrupts = <0x2b 0x04>;
+			interrupt-parent = <&itgen0>;
+			reg = <0x00 0x20212000 0x00 0x100>;
+			compatible = "snps,dw-apb-uart";
+		};
+
+		serial@20213000 {
+			reg-shift = <0x02>;
+			reg-io-width = <0x04>;
+			phandle = <0x3a>;
+			clocks = <&ref_clk>;
+			interrupts = <0x2c 0x04>;
+			interrupt-parent = <&itgen0>;
+			reg = <0x00 0x20213000 0x00 0x100>;
+			compatible = "snps,dw-apb-uart";
+		};
+
+		serial@20214000 {
+			reg-shift = <0x02>;
+			reg-io-width = <0x04>;
+			phandle = <0x39>;
+			clocks = <&ref_clk>;
+			interrupts = <0x2d 0x04>;
+			interrupt-parent = <&itgen0>;
+			reg = <0x00 0x20214000 0x00 0x100>;
+			compatible = "snps,dw-apb-uart";
+		};
+
+		serial@20215000 {
+			reg-shift = <0x02>;
+			reg-io-width = <0x04>;
+			phandle = <0x38>;
+			clocks = <&ref_clk>;
+			interrupts = <0x2e 0x04>;
+			interrupt-parent = <&itgen0>;
+			reg = <0x00 0x20215000 0x00 0x100>;
+			compatible = "snps,dw-apb-uart";
+		};
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00 0x00 0x00 0x400000>;
+	};
+
+	apic_mailbox: apic_mailbox@a00000 {
+		compatible = "kalray,coolidge-apic-mailbox";
+		reg = <0x00 0xa00000 0x00 0xea00>;
+		#interrupt-cells = <0x00>;
+		#address-cells = <0>;
+		interrupt-parent = <&apic_gic>;
+		interrupts = <0x00>, <0x01>, <0x02>, <0x03>, <0x04>, <0x05>,
+			     <0x06>, <0x07>, <0x08>, <0x09>, <0x0a>, <0x0b>,
+			     <0x0c>, <0x0d>, <0x0e>, <0x0f>, <0x10>, <0x11>,
+			     <0x12>, <0x13>, <0x14>, <0x15>, <0x16>, <0x17>,
+			     <0x18>, <0x19>, <0x1a>, <0x1b>, <0x1c>, <0x1d>,
+			     <0x1e>, <0x1f>, <0x20>, <0x21>, <0x22>, <0x23>,
+			     <0x24>, <0x25>, <0x26>, <0x27>, <0x28>, <0x29>,
+			     <0x2a>, <0x2b>, <0x2c>, <0x2d>, <0x2e>, <0x2f>,
+			     <0x30>, <0x31>, <0x32>, <0x33>, <0x34>, <0x35>,
+			     <0x36>, <0x37>, <0x38>, <0x39>, <0x3a>, <0x3b>,
+			     <0x3c>, <0x3d>, <0x3e>, <0x3f>, <0x40>, <0x41>,
+			     <0x42>, <0x43>, <0x44>, <0x45>, <0x46>, <0x47>,
+			     <0x48>, <0x49>, <0x4a>, <0x4b>, <0x4c>, <0x4d>,
+			     <0x4e>, <0x4f>, <0x50>, <0x51>, <0x52>, <0x53>,
+			     <0x54>, <0x55>, <0x56>, <0x57>, <0x58>, <0x59>,
+			     <0x5a>, <0x5b>, <0x5c>, <0x5d>, <0x5e>, <0x5f>,
+			     <0x60>, <0x61>, <0x62>, <0x63>, <0x64>, <0x65>,
+			     <0x66>, <0x67>, <0x68>, <0x69>, <0x6a>, <0x6b>,
+			     <0x6c>, <0x6d>, <0x6e>, <0x6f>, <0x70>, <0x71>,
+			     <0x72>, <0x73>, <0x74>;
+		interrupt-controller;
+		msi-controller;
+	};
+
+	apic_gic: apic_gic@a20000 {
+		compatible = "kalray,coolidge-apic-gic";
+		reg = <0x00 0xa20000 0x00 0x12000>;
+		#interrupt-cells = <0x01>;
+		interrupts-extended = <&core_intc0 0x4>,
+				      <&core_intc1 0x4>,
+				      <&core_intc2 0x4>,
+				      <&core_intc3 0x4>,
+				      <&core_intc4 0x4>,
+				      <&core_intc5 0x4>,
+				      <&core_intc6 0x4>,
+				      <&core_intc7 0x4>,
+				      <&core_intc8 0x4>,
+				      <&core_intc9 0x4>,
+				      <&core_intc10 0x4>,
+				      <&core_intc11 0x4>,
+				      <&core_intc12 0x4>,
+				      <&core_intc13 0x4>,
+				      <&core_intc14 0x4>,
+				      <&core_intc15 0x4>;
+		interrupt-controller;
+	};
+
+	pwr_ctrl: pwr_ctrl@a40000 {
+		compatible = "kalray,coolidge-pwr-ctrl";
+		reg = <0x00 0xa40000 0x00 0x4188>;
+	};
+
+	dsu_clock@a44180 {
+		compatible = "kalray,coolidge-dsu-clock";
+		reg = <0x00 0xa44180 0x00 0x08>;
+		clocks = <&core_clk>;
+	};
+
+	ipi_ctrl@ad0000 {
+		compatible = "kalray,coolidge-ipi-ctrl";
+		reg = <0x00 0xad0000 0x00 0x1000>;
+		#interrupt-cells = <0>;
+		interrupt-controller;
+		interrupts-extended = <&core_intc0 0x18>,
+				      <&core_intc1 0x18>,
+				      <&core_intc2 0x18>,
+				      <&core_intc3 0x18>,
+				      <&core_intc4 0x18>,
+				      <&core_intc5 0x18>,
+				      <&core_intc6 0x18>,
+				      <&core_intc7 0x18>,
+				      <&core_intc8 0x18>,
+				      <&core_intc9 0x18>,
+				      <&core_intc10 0x18>,
+				      <&core_intc11 0x18>,
+				      <&core_intc12 0x18>,
+				      <&core_intc13 0x18>,
+				      <&core_intc14 0x18>,
+				      <&core_intc15 0x18>;
+	};
+
+	core_timer {
+		compatible = "kalray,kv3-1-timer";
+		clocks = <&core_clk>;
+		interrupts-extended = <&core_intc0 0>,
+				      <&core_intc1 0>,
+				      <&core_intc2 0>,
+				      <&core_intc3 0>,
+				      <&core_intc4 0>,
+				      <&core_intc5 0>,
+				      <&core_intc6 0>,
+				      <&core_intc7 0>,
+				      <&core_intc8 0>,
+				      <&core_intc9 0>,
+				      <&core_intc10 0>,
+				      <&core_intc11 0>,
+				      <&core_intc12 0>,
+				      <&core_intc13 0>,
+				      <&core_intc14 0>,
+				      <&core_intc15 0>;
+	};
+
+	clocks {
+
+		core_clk: core_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <0x3b9aca00>;
+			#clock-cells = <0x00>;
+		};
+
+		ref_clk: ref_clk {
+			clock-frequency = <0x5f5e100>;
+			#clock-cells = <0x00>;
+			compatible = "fixed-clock";
+		};
+	};
+
+	cpus {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		enable-method = "kalray,coolidge-pwr-ctrl";
+
+		cpu@0 {
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			device_type = "cpu";
+			reg = <0x00>;
+			clocks = <&core_clk>;
+			core_intc0: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			reg = <0x01>;
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			core_intc1: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			reg = <0x02>;
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			core_intc2: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			reg = <0x03>;
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			core_intc3: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@4 {
+			device_type = "cpu";
+			reg = <0x04>;
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			core_intc4: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@5 {
+			device_type = "cpu";
+			reg = <0x05>;
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			core_intc5: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@6 {
+			device_type = "cpu";
+			reg = <0x06>;
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			core_intc6: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@7 {
+			device_type = "cpu";
+			reg = <0x07>;
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			core_intc7: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@8 {
+			device_type = "cpu";
+			reg = <0x08>;
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			core_intc8: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@9 {
+			device_type = "cpu";
+			reg = <0x09>;
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			core_intc9: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@10 {
+			device_type = "cpu";
+			reg = <0x0a>;
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			core_intc10: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@11 {
+			device_type = "cpu";
+			reg = <0x0b>;
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			core_intc11: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@12 {
+			device_type = "cpu";
+			reg = <0x0c>;
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			core_intc12: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@13 {
+			device_type = "cpu";
+			reg = <0x0d>;
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			core_intc13: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@14 {
+			device_type = "cpu";
+			reg = <0x0e>;
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			core_intc14: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+		cpu@15 {
+			device_type = "cpu";
+			reg = <0x0f>;
+			compatible = "kalray,kv3-1-pe","kalray,kv3-pe";
+			core_intc15: interrupt-controller {
+				compatible = "kalray,kv3-1-intc";
+				#interrupt-cells = <0x01>;
+				#address-cells = <0x0>;
+				interrupt-controller;
+			};
+		};
+
+	};
+};
-- 
2.45.2

Re: [RFC PATCH v3 36/37] kvx: dts: DeviceTree for qemu emulated Coolidge SoC

[Krzysztof Kozlowski]

On 22/07/2024 11:41, ysionneau@kalrayinc.com wrote:
> From: Yann Sionneau <ysionneau@kalrayinc.com>
> 
> Add device tree for QEMU that emulates a Coolidge V1 SoC.
> 
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3: New patch
> ---
>  arch/kvx/boot/dts/Makefile          |   1 +
>  arch/kvx/boot/dts/coolidge-qemu.dts | 444 ++++++++++++++++++++++++++++
>  2 files changed, 445 insertions(+)
>  create mode 100644 arch/kvx/boot/dts/Makefile
>  create mode 100644 arch/kvx/boot/dts/coolidge-qemu.dts
> 
> diff --git a/arch/kvx/boot/dts/Makefile b/arch/kvx/boot/dts/Makefile
> new file mode 100644
> index 0000000000000..cd27ceb7a6cce
> --- /dev/null
> +++ b/arch/kvx/boot/dts/Makefile
> @@ -0,0 +1 @@
> +dtb-y += coolidge-qemu.dtb
> diff --git a/arch/kvx/boot/dts/coolidge-qemu.dts b/arch/kvx/boot/dts/coolidge-qemu.dts
> new file mode 100644
> index 0000000000000..1d5af0d2e687d
> --- /dev/null
> +++ b/arch/kvx/boot/dts/coolidge-qemu.dts
> @@ -0,0 +1,444 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/dts-v1/;
> +/*
> + * Copyright (C) 2024, Kalray Inc.
> + */
> +
> +/ {
> +	model = "Kalray Coolidge processor (QEMU)";
> +	compatible = "kalray,coolidge-qemu";
> +	#address-cells = <0x02>;

That's not a hex, so just <2>

> +	#size-cells = <0x02>;
> +
> +	chosen {
> +		stdout-path = "/axi/serial@20210000";

No, use phandle/label.

> +	};
> +
> +	memory@100000000 {
> +		phandle = <0x40>;
> +		reg = <0x01 0x00 0x00 0x8000000>;
> +		device_type = "memory";
> +	};
> +
> +	axi {
> +		compatible = "simple-bus";
> +		#address-cells = <0x02>;

Same problem.


> +		#size-cells = <0x02>;
> +		ranges;
> +
> +		virtio-mmio@30003c00 {

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation


> +			compatible = "virtio,mmio";
> +			reg = <0x00 0x30003c00 0x00 0x200>;
> +			interrupt-parent = <&itgen0>;
> +			interrupts = <0x9e 0x04>;
> +		};
> +
> +		virtio-mmio@30003e00 {
> +			compatible = "virtio,mmio";
> +			reg = <0x00 0x30003e00 0x00 0x200>;
> +			interrupt-parent = <&itgen0>;
> +			interrupts = <0x9f 0x04>;
> +		};
> +
> +		itgen0: itgen_soc_periph0@27000000 {

Please follow DTS coding style.

> +			compatible = "kalray,coolidge-itgen";
> +			reg = <0x00 0x27000000 0x00 0x1104>;
> +			msi-parent = <&apic_mailbox>;
> +			#interrupt-cells = <0x02>;
> +			interrupt-controller;
> +		};
> +
> +		serial@20210000 {
> +			reg-shift = <0x02>;
> +			reg-io-width = <0x04>;

Sorry, but width and shift are rarely hex values. Make your code
readable. Adhere to existing coding style.


> +			clocks = <&ref_clk>;
> +			interrupts = <0x29 0x04>;
> +			interrupt-parent = <&itgen0>;
> +			reg = <0x00 0x20210000 0x00 0x100>;
> +			compatible = "snps,dw-apb-uart";

Follow DTS coding style - order the properties correctly.


> +		};
> +
> +		serial@20211000 {
> +			reg-shift = <0x02>;
> +			reg-io-width = <0x04>;
> +			phandle = <0x3c>;
> +			clocks = <&ref_clk>;
> +			interrupts = <0x2a 0x04>;
> +			interrupt-parent = <&itgen0>;
> +			reg = <0x00 0x20211000 0x00 0x100>;
> +			compatible = "snps,dw-apb-uart";
> +		};
> +
> +		serial@20212000 {
> +			reg-shift = <0x02>;
> +			reg-io-width = <0x04>;
> +			phandle = <0x3b>;
> +			clocks = <&ref_clk>;
> +			interrupts = <0x2b 0x04>;
> +			interrupt-parent = <&itgen0>;
> +			reg = <0x00 0x20212000 0x00 0x100>;
> +			compatible = "snps,dw-apb-uart";
> +		};
> +
> +		serial@20213000 {
> +			reg-shift = <0x02>;
> +			reg-io-width = <0x04>;
> +			phandle = <0x3a>;
> +			clocks = <&ref_clk>;
> +			interrupts = <0x2c 0x04>;
> +			interrupt-parent = <&itgen0>;
> +			reg = <0x00 0x20213000 0x00 0x100>;
> +			compatible = "snps,dw-apb-uart";
> +		};
> +
> +		serial@20214000 {
> +			reg-shift = <0x02>;
> +			reg-io-width = <0x04>;
> +			phandle = <0x39>;
> +			clocks = <&ref_clk>;
> +			interrupts = <0x2d 0x04>;
> +			interrupt-parent = <&itgen0>;
> +			reg = <0x00 0x20214000 0x00 0x100>;
> +			compatible = "snps,dw-apb-uart";
> +		};
> +
> +		serial@20215000 {
> +			reg-shift = <0x02>;
> +			reg-io-width = <0x04>;
> +			phandle = <0x38>;
> +			clocks = <&ref_clk>;
> +			interrupts = <0x2e 0x04>;
> +			interrupt-parent = <&itgen0>;
> +			reg = <0x00 0x20215000 0x00 0x100>;
> +			compatible = "snps,dw-apb-uart";
> +		};
> +	};
> +
> +	memory@0 {

Why memory is in multiple places?

> +		device_type = "memory";
> +		reg = <0x00 0x00 0x00 0x400000>;
> +	};
> +
> +	apic_mailbox: apic_mailbox@a00000 {

Why this is outside of SoC? Where is the SoC anyway?

> +		compatible = "kalray,coolidge-apic-mailbox";

Your compatibles are confusing. What is the soc name? In other binding
you entirely omitted coolidge. See writing bindings (or any other recent
DTS which passed review) - it has rationale behind it.

> +		reg = <0x00 0xa00000 0x00 0xea00>;
> +		#interrupt-cells = <0x00>;
> +		#address-cells = <0>;

And this is not <0x0>? It's like random coding style.

I stopped reviewing here. Rest of the DTS does not look better.

Best regards,
Krzysztof

Re: [RFC PATCH v3 36/37] kvx: dts: DeviceTree for qemu emulated Coolidge SoC

[Conor Dooley]

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On Mon, Jul 22, 2024 at 11:55:46AM +0200, Krzysztof Kozlowski wrote:
> On 22/07/2024 11:41, ysionneau@kalrayinc.com wrote:
> > From: Yann Sionneau <ysionneau@kalrayinc.com>
> > 
> > Add device tree for QEMU that emulates a Coolidge V1 SoC.

> > +	model = "Kalray Coolidge processor (QEMU)";
> > +	compatible = "kalray,coolidge-qemu";

I'm not sure that this should even be in the kernel. Why isn't QEMU able
to generate a devicetree for this emulated platform, like it can on
other architectures?

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Re: [RFC PATCH v3 36/37] kvx: dts: DeviceTree for qemu emulated Coolidge SoC

[Yann Sionneau]

Hello Krzysztof,

On 22/07/2024 11:55, Krzysztof Kozlowski wrote:
> On 22/07/2024 11:41, ysionneau@kalrayinc.com wrote:
>> From: Yann Sionneau <ysionneau@kalrayinc.com>
>>
>> Add device tree for QEMU that emulates a Coolidge V1 SoC.
>>
>> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
>> ---
>>
>> Notes:
>>
>> V2 -> V3: New patch
>> ---
>>  arch/kvx/boot/dts/Makefile          |   1 +
>>  arch/kvx/boot/dts/coolidge-qemu.dts | 444 ++++++++++++++++++++++++++++
>>  2 files changed, 445 insertions(+)
>>  create mode 100644 arch/kvx/boot/dts/Makefile
>>  create mode 100644 arch/kvx/boot/dts/coolidge-qemu.dts
>>
>> diff --git a/arch/kvx/boot/dts/Makefile b/arch/kvx/boot/dts/Makefile
>> new file mode 100644
>> index 0000000000000..cd27ceb7a6cce
>> --- /dev/null
>> +++ b/arch/kvx/boot/dts/Makefile
>> @@ -0,0 +1 @@
>> +dtb-y += coolidge-qemu.dtb
>> diff --git a/arch/kvx/boot/dts/coolidge-qemu.dts b/arch/kvx/boot/dts/coolidge-qemu.dts
>> new file mode 100644
>> index 0000000000000..1d5af0d2e687d
>> --- /dev/null
>> +++ b/arch/kvx/boot/dts/coolidge-qemu.dts
>> @@ -0,0 +1,444 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later
>> +/dts-v1/;
>> +/*
>> + * Copyright (C) 2024, Kalray Inc.
>> + */
>> +
>> +/ {
>> +	model = "Kalray Coolidge processor (QEMU)";
>> +	compatible = "kalray,coolidge-qemu";
>> +	#address-cells = <0x02>;
> That's not a hex, so just <2>
Ack, I will fix this.
>
>> +	#size-cells = <0x02>;
>> +
>> +	chosen {
>> +		stdout-path = "/axi/serial@20210000";
> No, use phandle/label.
Ack, I will fix this. However can you point me to where this is documented? In https://www.kernel.org/doc/Documentation/devicetree/bindings/chosen.txt I can see a path is used as example and not a phandle/label.
>
>> +	};
>> +
>> +	memory@100000000 {
>> +		phandle = <0x40>;
>> +		reg = <0x01 0x00 0x00 0x8000000>;
>> +		device_type = "memory";
>> +	};
>> +
>> +	axi {
>> +		compatible = "simple-bus";
>> +		#address-cells = <0x02>;
> Same problem.
Ack.
>
>
>> +		#size-cells = <0x02>;
>> +		ranges;
>> +
>> +		virtio-mmio@30003c00 {
> Node names should be generic. See also an explanation and list of
> examples (not exhaustive) in DT specification:
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

I fail to understand what I should put even after reading the link above. This node is kind of "generic" and could be used either for a virtio-block device or a virtio-net device.

Could you elaborate on this please?

>
>
>> +			compatible = "virtio,mmio";
>> +			reg = <0x00 0x30003c00 0x00 0x200>;
>> +			interrupt-parent = <&itgen0>;
>> +			interrupts = <0x9e 0x04>;
>> +		};
>> +
>> +		virtio-mmio@30003e00 {
>> +			compatible = "virtio,mmio";
>> +			reg = <0x00 0x30003e00 0x00 0x200>;
>> +			interrupt-parent = <&itgen0>;
>> +			interrupts = <0x9f 0x04>;
>> +		};
>> +
>> +		itgen0: itgen_soc_periph0@27000000 {
> Please follow DTS coding style.
Oops, ack, I will fix this and replace "_" with "-" in node/property names.
>
>> +			compatible = "kalray,coolidge-itgen";
>> +			reg = <0x00 0x27000000 0x00 0x1104>;
>> +			msi-parent = <&apic_mailbox>;
>> +			#interrupt-cells = <0x02>;
>> +			interrupt-controller;
>> +		};
>> +
>> +		serial@20210000 {
>> +			reg-shift = <0x02>;
>> +			reg-io-width = <0x04>;
> Sorry, but width and shift are rarely hex values. Make your code
> readable. Adhere to existing coding style.
Ack, I will fix this.
>
>
>> +			clocks = <&ref_clk>;
>> +			interrupts = <0x29 0x04>;
>> +			interrupt-parent = <&itgen0>;
>> +			reg = <0x00 0x20210000 0x00 0x100>;
>> +			compatible = "snps,dw-apb-uart";
> Follow DTS coding style - order the properties correctly.
Oops, ack, I will fix this.
>
>
>> +		};
>> +
>> +		serial@20211000 {
>> +			reg-shift = <0x02>;
>> +			reg-io-width = <0x04>;
>> +			phandle = <0x3c>;
>> +			clocks = <&ref_clk>;
>> +			interrupts = <0x2a 0x04>;
>> +			interrupt-parent = <&itgen0>;
>> +			reg = <0x00 0x20211000 0x00 0x100>;
>> +			compatible = "snps,dw-apb-uart";
>> +		};
>> +
>> +		serial@20212000 {
>> +			reg-shift = <0x02>;
>> +			reg-io-width = <0x04>;
>> +			phandle = <0x3b>;
>> +			clocks = <&ref_clk>;
>> +			interrupts = <0x2b 0x04>;
>> +			interrupt-parent = <&itgen0>;
>> +			reg = <0x00 0x20212000 0x00 0x100>;
>> +			compatible = "snps,dw-apb-uart";
>> +		};
>> +
>> +		serial@20213000 {
>> +			reg-shift = <0x02>;
>> +			reg-io-width = <0x04>;
>> +			phandle = <0x3a>;
>> +			clocks = <&ref_clk>;
>> +			interrupts = <0x2c 0x04>;
>> +			interrupt-parent = <&itgen0>;
>> +			reg = <0x00 0x20213000 0x00 0x100>;
>> +			compatible = "snps,dw-apb-uart";
>> +		};
>> +
>> +		serial@20214000 {
>> +			reg-shift = <0x02>;
>> +			reg-io-width = <0x04>;
>> +			phandle = <0x39>;
>> +			clocks = <&ref_clk>;
>> +			interrupts = <0x2d 0x04>;
>> +			interrupt-parent = <&itgen0>;
>> +			reg = <0x00 0x20214000 0x00 0x100>;
>> +			compatible = "snps,dw-apb-uart";
>> +		};
>> +
>> +		serial@20215000 {
>> +			reg-shift = <0x02>;
>> +			reg-io-width = <0x04>;
>> +			phandle = <0x38>;
>> +			clocks = <&ref_clk>;
>> +			interrupts = <0x2e 0x04>;
>> +			interrupt-parent = <&itgen0>;
>> +			reg = <0x00 0x20215000 0x00 0x100>;
>> +			compatible = "snps,dw-apb-uart";
>> +		};
>> +	};
>> +
>> +	memory@0 {
> Why memory is in multiple places?
I should put all memory nodes one after another? Ok I will do this.
>
>> +		device_type = "memory";
>> +		reg = <0x00 0x00 0x00 0x400000>;
>> +	};
>> +
>> +	apic_mailbox: apic_mailbox@a00000 {
> Why this is outside of SoC? Where is the SoC anyway?

Oops, I didn't know it was mandatory to put a soc { } in the DT, I've browsed the DT spec and the "soc" node is not formally described as something special. Maybe this needs to be documented somewhere?

I reckon it's a nice way to separate what's on the board (PCB) and what's in the SoC.

I'll add a `soc { [...] };` in the next patch iteration that will contain what's in the SoC.

>
>> +		compatible = "kalray,coolidge-apic-mailbox";
> Your compatibles are confusing. What is the soc name? In other binding
> you entirely omitted coolidge. See writing bindings (or any other recent
> DTS which passed review) - it has rationale behind it.

SoC name is "Coolidge" and the "APIC Mailbox" hw is in the SoC, it is memory mapped.

But I guess this point is now already more clear since my last emails answering the "core intc" reviews.

>
>> +		reg = <0x00 0xa00000 0x00 0xea00>;
>> +		#interrupt-cells = <0x00>;
>> +		#address-cells = <0>;
> And this is not <0x0>? It's like random coding style.
Oops, I will clean this up for next iteration.
>
> I stopped reviewing here. Rest of the DTS does not look better.

I'm sorry if it looks like a mess here, I am new to submitting DT upstream and it looks like I failed to apply all the rules.

I thank you for taking the time to review it nonetheless and I hope my next patch iterations will be better and easier to review.

Regards,

-- 

Yann

Re: [RFC PATCH v3 36/37] kvx: dts: DeviceTree for qemu emulated Coolidge SoC

[Krzysztof Kozlowski]

On 31/07/2024 17:38, Yann Sionneau wrote:

>>
>>> +	#size-cells = <0x02>;
>>> +
>>> +	chosen {
>>> +		stdout-path = "/axi/serial@20210000";
>> No, use phandle/label.
> Ack, I will fix this. However can you point me to where this is documented? In https://www.kernel.org/doc/Documentation/devicetree/bindings/chosen.txt I can see a path is used as example and not a phandle/label.

That's just sanity and common (maybe except Tegra) style... Almost every
source uses this, because it gives you code which is independent of node
ordering, node names and unit addresses.

What if I change in next patch axi->soc, how usually we code it?

Override by label/phandle was mentioned many times on mailing lists as
preferred.

>>
>>> +	};
>>> +
>>> +	memory@100000000 {
>>> +		phandle = <0x40>;
>>> +		reg = <0x01 0x00 0x00 0x8000000>;
>>> +		device_type = "memory";
>>> +	};
>>> +
>>> +	axi {
>>> +		compatible = "simple-bus";
>>> +		#address-cells = <0x02>;
>> Same problem.
> Ack.
>>
>>
>>> +		#size-cells = <0x02>;
>>> +		ranges;
>>> +
>>> +		virtio-mmio@30003c00 {
>> Node names should be generic. See also an explanation and list of
>> examples (not exhaustive) in DT specification:
>> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> 
> I fail to understand what I should put even after reading the link above. This node is kind of "generic" and could be used either for a virtio-block device or a virtio-net device.
> 
> Could you elaborate on this please?

Just go with virtio.

> 
>>
>>
>>> +			compatible = "virtio,mmio";
>>> +			reg = <0x00 0x30003c00 0x00 0x200>;
>>> +			interrupt-parent = <&itgen0>;
>>> +			interrupts = <0x9e 0x04>;
>>> +		};
>>> +
>>> +		virtio-mmio@30003e00 {
>>> +			compatible = "virtio,mmio";
>>> +			reg = <0x00 0x30003e00 0x00 0x200>;
>>> +			interrupt-parent = <&itgen0>;
>>> +			interrupts = <0x9f 0x04>;
>>> +		};
>>> +
>>> +		itgen0: itgen_soc_periph0@27000000 {
>> Please follow DTS coding style.
> Oops, ack, I will fix this and replace "_" with "-" in node/property names.
>>
>>> +			compatible = "kalray,coolidge-itgen";
>>> +			reg = <0x00 0x27000000 0x00 0x1104>;
>>> +			msi-parent = <&apic_mailbox>;
>>> +			#interrupt-cells = <0x02>;
>>> +			interrupt-controller;
>>> +		};
>>> +
>>> +		serial@20210000 {
>>> +			reg-shift = <0x02>;
>>> +			reg-io-width = <0x04>;
>> Sorry, but width and shift are rarely hex values. Make your code
>> readable. Adhere to existing coding style.
> Ack, I will fix this.
>>
>>
>>> +			clocks = <&ref_clk>;
>>> +			interrupts = <0x29 0x04>;
>>> +			interrupt-parent = <&itgen0>;
>>> +			reg = <0x00 0x20210000 0x00 0x100>;
>>> +			compatible = "snps,dw-apb-uart";
>> Follow DTS coding style - order the properties correctly.
> Oops, ack, I will fix this.
>>
>>
>>> +		};
>>> +
>>> +		serial@20211000 {
>>> +			reg-shift = <0x02>;
>>> +			reg-io-width = <0x04>;
>>> +			phandle = <0x3c>;
>>> +			clocks = <&ref_clk>;
>>> +			interrupts = <0x2a 0x04>;
>>> +			interrupt-parent = <&itgen0>;
>>> +			reg = <0x00 0x20211000 0x00 0x100>;
>>> +			compatible = "snps,dw-apb-uart";
>>> +		};
>>> +
>>> +		serial@20212000 {
>>> +			reg-shift = <0x02>;
>>> +			reg-io-width = <0x04>;
>>> +			phandle = <0x3b>;
>>> +			clocks = <&ref_clk>;
>>> +			interrupts = <0x2b 0x04>;
>>> +			interrupt-parent = <&itgen0>;
>>> +			reg = <0x00 0x20212000 0x00 0x100>;
>>> +			compatible = "snps,dw-apb-uart";
>>> +		};
>>> +
>>> +		serial@20213000 {
>>> +			reg-shift = <0x02>;
>>> +			reg-io-width = <0x04>;
>>> +			phandle = <0x3a>;
>>> +			clocks = <&ref_clk>;
>>> +			interrupts = <0x2c 0x04>;
>>> +			interrupt-parent = <&itgen0>;
>>> +			reg = <0x00 0x20213000 0x00 0x100>;
>>> +			compatible = "snps,dw-apb-uart";
>>> +		};
>>> +
>>> +		serial@20214000 {
>>> +			reg-shift = <0x02>;
>>> +			reg-io-width = <0x04>;
>>> +			phandle = <0x39>;
>>> +			clocks = <&ref_clk>;
>>> +			interrupts = <0x2d 0x04>;
>>> +			interrupt-parent = <&itgen0>;
>>> +			reg = <0x00 0x20214000 0x00 0x100>;
>>> +			compatible = "snps,dw-apb-uart";
>>> +		};
>>> +
>>> +		serial@20215000 {
>>> +			reg-shift = <0x02>;
>>> +			reg-io-width = <0x04>;
>>> +			phandle = <0x38>;
>>> +			clocks = <&ref_clk>;
>>> +			interrupts = <0x2e 0x04>;
>>> +			interrupt-parent = <&itgen0>;
>>> +			reg = <0x00 0x20215000 0x00 0x100>;
>>> +			compatible = "snps,dw-apb-uart";
>>> +		};
>>> +	};
>>> +
>>> +	memory@0 {
>> Why memory is in multiple places?
> I should put all memory nodes one after another? Ok I will do this.
>>
>>> +		device_type = "memory";
>>> +		reg = <0x00 0x00 0x00 0x400000>;
>>> +	};
>>> +
>>> +	apic_mailbox: apic_mailbox@a00000 {
>> Why this is outside of SoC? Where is the SoC anyway?
> 
> Oops, I didn't know it was mandatory to put a soc { } in the DT, I've browsed the DT spec and the "soc" node is not formally described as something special. Maybe this needs to be documented somewhere?
> 
> I reckon it's a nice way to separate what's on the board (PCB) and what's in the SoC.
> 
> I'll add a `soc { [...] };` in the next patch iteration that will contain what's in the SoC.

Coding style, emails, all new DTS since some years or talks on numerous
conferences... All this code looks like you took some vendor downstream
code and sent it. That's not how it works. You take recent, reviewed DTS
and use it as template. Qualcomm sm8650 or x1e8010 are good examples.

> 
>>
>>> +		compatible = "kalray,coolidge-apic-mailbox";
>> Your compatibles are confusing. What is the soc name? In other binding
>> you entirely omitted coolidge. See writing bindings (or any other recent
>> DTS which passed review) - it has rationale behind it.
> 
> SoC name is "Coolidge" and the "APIC Mailbox" hw is in the SoC, it is memory mapped.
> 
> But I guess this point is now already more clear since my last emails answering the "core intc" reviews.
> 
>>


Best regards,
Krzysztof

[RFC PATCH v3 37/37] Add Kalray Inc. to the list of vendor-prefixes.yaml

[ysionneau]

From: Julian Vetter <jvetter@kalrayinc.com>

Signed-off-by: Julian Vetter <jvetter@kalrayinc.com>
Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
---

Notes:

V2 -> V3: New patch
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index fbf47f0bacf1a..65954a1077ed7 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -754,6 +754,8 @@ patternProperties:
     description: Jide Tech
   "^joz,.*":
     description: JOZ BV
+  "^kalray,.*":
+    description: Kalray Inc.
   "^kam,.*":
     description: Kamstrup A/S
   "^karo,.*":
-- 
2.45.2

Re: [RFC PATCH v3 37/37] Add Kalray Inc. to the list of vendor-prefixes.yaml

[Krzysztof Kozlowski]

On 22/07/2024 11:41, ysionneau@kalrayinc.com wrote:
> From: Julian Vetter <jvetter@kalrayinc.com>
> 

Missing commit msg.

> Signed-off-by: Julian Vetter <jvetter@kalrayinc.com>
> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
> ---
> 
> Notes:
> 
> V2 -> V3: New patch

Bindings come before users.


Best regards,
Krzysztof

Re: [RFC PATCH v3 37/37] Add Kalray Inc. to the list of vendor-prefixes.yaml

[Yann Sionneau]

Hello Krzysztof,

On 22/07/2024 11:56, Krzysztof Kozlowski wrote:
> On 22/07/2024 11:41, ysionneau@kalrayinc.com wrote:
>> From: Julian Vetter <jvetter@kalrayinc.com>
>>
>>
> Missing commit msg.
Ack, will fix.
>
>> Signed-off-by: Julian Vetter <jvetter@kalrayinc.com>
>> Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
>> ---
>>
>> Notes:
>>
>> V2 -> V3: New patch
> Bindings come before users.

Oops, ok.

Regards,

-- 

Yann