From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EB5523A564; Tue, 22 Jul 2025 09:20:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753176007; cv=none; b=knzUF29lrp5zvouYhM00HG1e/MtVoH7nfq2v6vObftwlCgY/ihBcpZIznZFuQam+Mp416lFf4nCXjVw25q/VI8Mtmc3FcnNfeOfXkJUEERkoGpsJGvT0GyRQ2GgczkzUn1zbr36BHWc8a23/4HgCO9G+DzDvknWrBzPJfZ3XVFc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753176007; c=relaxed/simple; bh=B1T2MWPDPDtUYOSFsDx/tfdQ/pEGziEZ3AKWuscvoqs=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Q8kmb/hDvsK5PFVvurG790yUVach2K1IK1dUAky0Xl6UWnqd2bvlYfraXgeapJr7ZgWpZxHSAySlF/xhvfRRXGyMOO0MmAl3k2v0QMzCadCbCrugwjiDEOEtYrM3LvWXOKpJtLpxFKHRKeYUajJbkrFFsatAjfrxMTEa3KHP80c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iXUykyln; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iXUykyln" Received: by smtp.kernel.org (Postfix) with ESMTPSA id ECA3CC4CEEB; Tue, 22 Jul 2025 09:20:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753176007; bh=B1T2MWPDPDtUYOSFsDx/tfdQ/pEGziEZ3AKWuscvoqs=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=iXUykyln4dJhQGpxCRNG5+tveBFfMM/aZyBOVCGy/PEZz9eR8G5iK1skRzqTr0fHq kN0teNAZyFW9l2F+koQIDL7iZU03RH4YYLAd8CEV0PviK9kAPjeCVFV1fh2scUA2xe dBlku0E1DO2YV1HCqX3mZZCpqpdyxKVfk3A7scH8wkQ771S8yuJkbMATcAyI95r38W ORg2mmWFd0g3dlAVVN6cvqtBxpq2JNXja6QBPiGoWO3WMrBgyayUjFy0G5WSh6+1Qk rxbugE3vsX/PSap08fUMLLVLWKfh5YrypS4A1UMGSl2P0PYdWrwbKWxGebPbk95dTD kEDEgFR3jfiow== Message-ID: <2fd202a6-2c92-469c-81c0-8852562d4e35@kernel.org> Date: Tue, 22 Jul 2025 11:19:59 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 03/13] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: support dual TCSR registers To: Xiangxu Yin , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmitry.baryshkov@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, fange.zhang@oss.qualcomm.com, quic_lliu6@quicinc.com, quic_yongmou@quicinc.com References: <20250722-add-displayport-support-for-qcs615-platform-v2-0-42b4037171f8@oss.qualcomm.com> <20250722-add-displayport-support-for-qcs615-platform-v2-3-42b4037171f8@oss.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 22/07/2025 09:22, Xiangxu Yin wrote: > Add support for specifying two TCSR register addresses in the > qcom,tcsr-reg property to enable DP-only mode switching. This change > maintains backward compatibility with the original single-register > format. > > Also update #clock-cells and #phy-cells to <1> to support clock and PHY > provider interfaces, respectively. This is required for platforms that > consume the PHY clock and select PHY mode dynamically. > > Signed-off-by: Xiangxu Yin > --- > .../bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 28 +++++++++++++++++----- > 1 file changed, 22 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml > index 1636285fbe535c430fdf792b33a5e9c523de323b..badfc46cda6c3a128688ac63b00d97dc2ba742d6 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml > @@ -44,13 +44,21 @@ properties: > vdda-pll-supply: true > > "#clock-cells": > - const: 0 > + oneOf: > + - description: Set to 0 for legacy platforms without clock provider > + const: 0 > + - description: Set to 1 to expose PHY pipe clock. > + const: 1 > > clock-output-names: > maxItems: 1 > > "#phy-cells": > - const: 0 > + oneOf: > + - description: Set to 0 for legacy platforms > + const: 0 > + - description: Set to 1 to supports mode selection (e.g. USB/DP) > + const: 1 I don't understand why EXISTING platforms now get more clocks. What did you change in the hardware? This you must explain in the commit msg. Best regards, Krzysztof