[PATCH 0/4] MediaTek MT8192 dtbs_check fixes

[PATCH 0/4] MediaTek MT8192 dtbs_check fixes

[AngeloGioacchino Del Regno]

This series addresses most of the MediaTek MT8192 dtbs_check warnings
by adding a missing SPI NOR flash compatible string and fixing both
the audsys binding and devicetree node name.

AngeloGioacchino Del Regno (4):
  dt-bindings: mtd: jedec,spi-nor: Add Winbond W25Q(32/64/128/256)JWM
  ASoC: dt-bindings: mt8192-afe-pcm: Fix clocks and clock-names
  dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant
  arm64: dts: mediatek: mt8192: Rename mt8192-afe-pcm to
    audio-controller

 .../arm/mediatek/mediatek,audsys.yaml         |  46 +++--
 .../bindings/mtd/jedec,spi-nor.yaml           |   2 +-
 .../bindings/sound/mt8192-afe-pcm.yaml        | 176 ++++++++++++++++--
 arch/arm64/boot/dts/mediatek/mt8192.dtsi      |   2 +-
 4 files changed, 197 insertions(+), 29 deletions(-)

-- 
2.52.0

[PATCH 1/4] dt-bindings: mtd: jedec,spi-nor: Add Winbond W25Q(32/64/128/256)JWM

[AngeloGioacchino Del Regno]

Add Winbond W25Q32JWM, W25Q64JWM, W25Q128JWM, W25Q256JWM to the
allowed compatible strings pattern.

This also resolves a dtbs_check warning happening on all of the
MediaTek MT8192 Chromebooks devicetrees (for winbond,w25q64jwm).

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
index 587af4968255..2db446c9ca9b 100644
--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
+++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
@@ -29,7 +29,7 @@ properties:
               (sst,)?sst26wf016b|\
               (sst,)?sst25wf(040b|080)|\
               winbond,w25x(80|32)|\
-              (winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$"
+              (winbond,)?w25q(16|32(w|dw)?|64(dw|jwm)?|80bl|128(fw|jwm)?|256(jwm)?))$"
           - const: jedec,spi-nor
       - items:
           - enum:
-- 
2.52.0

[PATCH 2/4] ASoC: dt-bindings: mt8192-afe-pcm: Fix clocks and clock-names

[AngeloGioacchino Del Regno]

Both clocks and clock-names are missing (a lot of) entries: add
all the used audio clocks and their description and also fix the
example node.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../bindings/sound/mt8192-afe-pcm.yaml        | 176 ++++++++++++++++--
 1 file changed, 162 insertions(+), 14 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
index 8ddf49b0040d..16ae3328f70d 100644
--- a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
+++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
@@ -47,16 +47,118 @@ properties:
       - description: AFE clock
       - description: ADDA DAC clock
       - description: ADDA DAC pre-distortion clock
-      - description: audio infra sys clock
-      - description: audio infra 26M clock
+      - description: ADDA ADC clock
+      - description: ADDA6 ADC clock
+      - description: Audio low-jitter 22.5792m clock
+      - description: Audio low-jitter 24.576m clock
+      - description: Audio PLL1 tuner clock
+      - description: Audio PLL2 tuner clock
+      - description: Audio Time-Division Multiplexing interface clock
+      - description: ADDA ADC Sine Generator clock
+      - description: audio Non-LE clock
+      - description: Audio DAC High-Resolution clock
+      - description: Audio High-Resolution ADC clock
+      - description: Audio High-Resolution ADC SineGen clock
+      - description: Audio ADDA6 High-Resolution ADC clock
+      - description: Tertiary ADDA DAC clock
+      - description: Tertiary ADDA DAC pre-distortion clock
+      - description: Tertiary ADDA DAC Sine Generator clock
+      - description: Tertiary ADDA DAC High-Resolution clock
+      - description: Audio infra sys clock
+      - description: Audio infra 26M clock
+      - description: Mux for audio clock
+      - description: Mux for audio internal bus clock
+      - description: Mux main divider by 4
+      - description: Primary audio mux
+      - description: Primary audio PLL
+      - description: Secondary audio mux
+      - description: Secondary audio PLL
+      - description: Primary audio en-generator clock
+      - description: Primary PLL divider by 4 for IEC
+      - description: Secondary audio en-generator clock
+      - description: Secondary PLL divider by 4 for IEC
+      - description: Mux selector for I2S port 0
+      - description: Mux selector for I2S port 1
+      - description: Mux selector for I2S port 2
+      - description: Mux selector for I2S port 3
+      - description: Mux selector for I2S port 4
+      - description: Mux selector for I2S port 5
+      - description: Mux selector for I2S port 6
+      - description: Mux selector for I2S port 7
+      - description: Mux selector for I2S port 8
+      - description: Mux selector for I2S port 9
+      - description: APLL1 and APLL2 divider for I2S port 0
+      - description: APLL1 and APLL2 divider for I2S port 1
+      - description: APLL1 and APLL2 divider for I2S port 2
+      - description: APLL1 and APLL2 divider for I2S port 3
+      - description: APLL1 and APLL2 divider for I2S port 4
+      - description: APLL1 and APLL2 divider for IEC
+      - description: APLL1 and APLL2 divider for I2S port 5
+      - description: APLL1 and APLL2 divider for I2S port 6
+      - description: APLL1 and APLL2 divider for I2S port 7
+      - description: APLL1 and APLL2 divider for I2S port 8
+      - description: APLL1 and APLL2 divider for I2S port 9
+      - description: Top mux for audio subsystem
+      - description: 26MHz clock for audio subsystem
 
   clock-names:
     items:
       - const: aud_afe_clk
       - const: aud_dac_clk
       - const: aud_dac_predis_clk
+      - const: aud_adc_clk
+      - const: aud_adda6_adc_clk
+      - const: aud_apll22m_clk
+      - const: aud_apll24m_clk
+      - const: aud_apll1_tuner_clk
+      - const: aud_apll2_tuner_clk
+      - const: aud_tdm_clk
+      - const: aud_tml_clk
+      - const: aud_nle
+      - const: aud_dac_hires_clk
+      - const: aud_adc_hires_clk
+      - const: aud_adc_hires_tml
+      - const: aud_adda6_adc_hires_clk
+      - const: aud_3rd_dac_clk
+      - const: aud_3rd_dac_predis_clk
+      - const: aud_3rd_dac_tml
+      - const: aud_3rd_dac_hires_clk
       - const: aud_infra_clk
       - const: aud_infra_26m_clk
+      - const: top_mux_audio
+      - const: top_mux_audio_int
+      - const: top_mainpll_d4_d4
+      - const: top_mux_aud_1
+      - const: top_apll1_ck
+      - const: top_mux_aud_2
+      - const: top_apll2_ck
+      - const: top_mux_aud_eng1
+      - const: top_apll1_d4
+      - const: top_mux_aud_eng2
+      - const: top_apll2_d4
+      - const: top_i2s0_m_sel
+      - const: top_i2s1_m_sel
+      - const: top_i2s2_m_sel
+      - const: top_i2s3_m_sel
+      - const: top_i2s4_m_sel
+      - const: top_i2s5_m_sel
+      - const: top_i2s6_m_sel
+      - const: top_i2s7_m_sel
+      - const: top_i2s8_m_sel
+      - const: top_i2s9_m_sel
+      - const: top_apll12_div0
+      - const: top_apll12_div1
+      - const: top_apll12_div2
+      - const: top_apll12_div3
+      - const: top_apll12_div4
+      - const: top_apll12_divb
+      - const: top_apll12_div5
+      - const: top_apll12_div6
+      - const: top_apll12_div7
+      - const: top_apll12_div8
+      - const: top_apll12_div9
+      - const: top_mux_audio_h
+      - const: top_clk26m_clk
 
 required:
   - compatible
@@ -83,23 +185,69 @@ examples:
     afe: mt8192-afe-pcm {
         compatible = "mediatek,mt8192-audio";
         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&audsys CLK_AUD_AFE>, <&audsys CLK_AUD_DAC>,
+                 <&audsys CLK_AUD_DAC_PREDIS>, <&audsys CLK_AUD_ADC>,
+                 <&audsys CLK_AUD_ADDA6_ADC>, <&audsys CLK_AUD_22M>,
+                 <&audsys CLK_AUD_24M>, <&audsys CLK_AUD_APLL_TUNER>,
+                 <&audsys CLK_AUD_APLL2_TUNER>, <&audsys CLK_AUD_TDM>,
+                 <&audsys CLK_AUD_TML>, <&audsys CLK_AUD_NLE>,
+                 <&audsys CLK_AUD_DAC_HIRES>, <&audsys CLK_AUD_ADC_HIRES>,
+                 <&audsys CLK_AUD_ADC_HIRES_TML>, <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+                 <&audsys CLK_AUD_3RD_DAC>, <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+                 <&audsys CLK_AUD_3RD_DAC_TML>, <&audsys CLK_AUD_3RD_DAC_HIRES>,
+                 <&infracfg CLK_INFRA_AUDIO>, <&infracfg CLK_INFRA_AUDIO_26M_B>,
+                 <&topckgen CLK_TOP_AUDIO_SEL>, <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+                 <&topckgen CLK_TOP_MAINPLL_D4_D4>, <&topckgen CLK_TOP_AUD_1_SEL>,
+                 <&topckgen CLK_TOP_APLL1>, <&topckgen CLK_TOP_AUD_2_SEL>,
+                 <&topckgen CLK_TOP_APLL2>, <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+                 <&topckgen CLK_TOP_APLL1_D4>, <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+                 <&topckgen CLK_TOP_APLL2_D4>, <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+                 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+                 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+                 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+                 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+                 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, <&topckgen CLK_TOP_APLL12_DIV0>,
+                 <&topckgen CLK_TOP_APLL12_DIV1>, <&topckgen CLK_TOP_APLL12_DIV2>,
+                 <&topckgen CLK_TOP_APLL12_DIV3>, <&topckgen CLK_TOP_APLL12_DIV4>,
+                 <&topckgen CLK_TOP_APLL12_DIVB>, <&topckgen CLK_TOP_APLL12_DIV5>,
+                 <&topckgen CLK_TOP_APLL12_DIV6>, <&topckgen CLK_TOP_APLL12_DIV7>,
+                 <&topckgen CLK_TOP_APLL12_DIV8>, <&topckgen CLK_TOP_APLL12_DIV9>,
+                 <&topckgen CLK_TOP_AUDIO_H_SEL>, <&clk26m>;
+        clock-names = "aud_afe_clk", "aud_dac_clk",
+                      "aud_dac_predis_clk", "aud_adc_clk",
+                      "aud_adda6_adc_clk", "aud_apll22m_clk",
+                      "aud_apll24m_clk", "aud_apll1_tuner_clk",
+                      "aud_apll2_tuner_clk", "aud_tdm_clk",
+                      "aud_tml_clk", "aud_nle",
+                      "aud_dac_hires_clk", "aud_adc_hires_clk",
+                      "aud_adc_hires_tml", "aud_adda6_adc_hires_clk",
+                      "aud_3rd_dac_clk", "aud_3rd_dac_predis_clk",
+                      "aud_3rd_dac_tml", "aud_3rd_dac_hires_clk",
+                      "aud_infra_clk", "aud_infra_26m_clk",
+                      "top_mux_audio", "top_mux_audio_int",
+                      "top_mainpll_d4_d4", "top_mux_aud_1",
+                      "top_apll1_ck", "top_mux_aud_2",
+                      "top_apll2_ck", "top_mux_aud_eng1",
+                      "top_apll1_d4", "top_mux_aud_eng2",
+                      "top_apll2_d4", "top_i2s0_m_sel",
+                      "top_i2s1_m_sel", "top_i2s2_m_sel",
+                      "top_i2s3_m_sel", "top_i2s4_m_sel",
+                      "top_i2s5_m_sel", "top_i2s6_m_sel",
+                      "top_i2s7_m_sel", "top_i2s8_m_sel",
+                      "top_i2s9_m_sel", "top_apll12_div0",
+                      "top_apll12_div1", "top_apll12_div2",
+                      "top_apll12_div3", "top_apll12_div4",
+                      "top_apll12_divb", "top_apll12_div5",
+                      "top_apll12_div6", "top_apll12_div7",
+                      "top_apll12_div8", "top_apll12_div9",
+                      "top_mux_audio_h", "top_clk26m_clk";
+        memory-region = <&afe_dma_mem>;
+        power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
         resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>;
         reset-names = "audiosys";
         mediatek,apmixedsys = <&apmixedsys>;
         mediatek,infracfg = <&infracfg>;
         mediatek,topckgen = <&topckgen>;
-        power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
-        clocks = <&audsys CLK_AUD_AFE>,
-                 <&audsys CLK_AUD_DAC>,
-                 <&audsys CLK_AUD_DAC_PREDIS>,
-                 <&infracfg CLK_INFRA_AUDIO>,
-                 <&infracfg CLK_INFRA_AUDIO_26M_B>;
-        clock-names = "aud_afe_clk",
-                      "aud_dac_clk",
-                      "aud_dac_predis_clk",
-                      "aud_infra_clk",
-                      "aud_infra_26m_clk";
-        memory-region = <&afe_dma_mem>;
     };
 
 ...
-- 
2.52.0

[PATCH 3/4] dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant

[AngeloGioacchino Del Regno]

Add support for the mediatek,mt8192-audsys compatible, which uses
a different audio controller (mt8192-afe-pcm) compared to mt8183
and mt2701.

This resolves a dtbs_check warning on all MT8192 devicetrees.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../arm/mediatek/mediatek,audsys.yaml         | 46 +++++++++++++------
 1 file changed, 33 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml
index f3a761cbd0fd..09a6c16e7e82 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml
@@ -48,19 +48,39 @@ required:
   - compatible
   - '#clock-cells'
 
-if:
-  properties:
-    compatible:
-      contains:
-        const: mediatek,mt8183-audiosys
-then:
-  properties:
-    audio-controller:
-      $ref: /schemas/sound/mediatek,mt8183-audio.yaml#
-else:
-  properties:
-    audio-controller:
-      $ref: /schemas/sound/mediatek,mt2701-audio.yaml#
+allOf:
+ - if:
+     properties:
+       compatible:
+         contains:
+           enum:
+             - mediatek,mt2701-audsys
+             - mediatek,mt7622-audsys
+   then:
+     properties:
+       audio-controller:
+         $ref: /schemas/sound/mediatek,mt2701-audio.yaml#
+
+ - if:
+     properties:
+       compatible:
+         contains:
+           const: mediatek,mt8183-audiosys
+   then:
+     properties:
+       audio-controller:
+         $ref: /schemas/sound/mediatek,mt8183-audio.yaml#
+
+ - if:
+     properties:
+       compatible:
+         contains:
+           const: mediatek,mt8192-audsys
+   then:
+     properties:
+       audio-controller:
+         $ref: /schemas/sound/mt8192-afe-pcm.yaml#
+
 
 additionalProperties: false
 
-- 
2.52.0

[PATCH 4/4] arm64: dts: mediatek: mt8192: Rename mt8192-afe-pcm to audio-controller

[AngeloGioacchino Del Regno]

Device tree nodes should have generic names, and this one doesn't.
Rename the mt8192-afe-pcm subnode of audsys to `audio-controller`.

This commit brings no functional changes, but resolves dtbs_check
warnings.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 47dea10dd3b8..9f8f115edd4c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -973,7 +973,7 @@ audsys: syscon@11210000 {
 			reg = <0 0x11210000 0 0x2000>;
 			#clock-cells = <1>;
 
-			afe: mt8192-afe-pcm {
+			afe: audio-controller {
 				compatible = "mediatek,mt8192-audio";
 				interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
 				resets = <&watchdog 17>;
-- 
2.52.0

Re: [PATCH 1/4] dt-bindings: mtd: jedec,spi-nor: Add Winbond W25Q(32/64/128/256)JWM

[Pratyush Yadav]

On Thu, Jan 15 2026, AngeloGioacchino Del Regno wrote:

> Add Winbond W25Q32JWM, W25Q64JWM, W25Q128JWM, W25Q256JWM to the
> allowed compatible strings pattern.
>
> This also resolves a dtbs_check warning happening on all of the
> MediaTek MT8192 Chromebooks devicetrees (for winbond,w25q64jwm).

We normally don't allow adding any more device-specific compatibles.
This list here is only for legacy DTS. You should be using
"jedec,spi-nor" in your device trees.

>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> index 587af4968255..2db446c9ca9b 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> @@ -29,7 +29,7 @@ properties:
>                (sst,)?sst26wf016b|\
>                (sst,)?sst25wf(040b|080)|\
>                winbond,w25x(80|32)|\
> -              (winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$"
> +              (winbond,)?w25q(16|32(w|dw)?|64(dw|jwm)?|80bl|128(fw|jwm)?|256(jwm)?))$"
>            - const: jedec,spi-nor
>        - items:
>            - enum:

-- 
Regards,
Pratyush Yadav

Re: [PATCH 2/4] ASoC: dt-bindings: mt8192-afe-pcm: Fix clocks and clock-names

[Eugen Hristev]

On 1/15/26 14:56, AngeloGioacchino Del Regno wrote:
> Both clocks and clock-names are missing (a lot of) entries: add
> all the used audio clocks and their description and also fix the
> example node.

Hi Angelo,

This does not really look like a fix, if it was a fix I would expect a
Fixes tag, otherwise, it looks like you are adding a lot of clocks which
were not defined before

Eugen
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  .../bindings/sound/mt8192-afe-pcm.yaml        | 176 ++++++++++++++++--
>  1 file changed, 162 insertions(+), 14 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> index 8ddf49b0040d..16ae3328f70d 100644
> --- a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> @@ -47,16 +47,118 @@ properties:
>        - description: AFE clock
>        - description: ADDA DAC clock
>        - description: ADDA DAC pre-distortion clock
> -      - description: audio infra sys clock
> -      - description: audio infra 26M clock
> +      - description: ADDA ADC clock
> +      - description: ADDA6 ADC clock
> +      - description: Audio low-jitter 22.5792m clock
> +      - description: Audio low-jitter 24.576m clock
> +      - description: Audio PLL1 tuner clock
> +      - description: Audio PLL2 tuner clock
> +      - description: Audio Time-Division Multiplexing interface clock
> +      - description: ADDA ADC Sine Generator clock
> +      - description: audio Non-LE clock
> +      - description: Audio DAC High-Resolution clock
> +      - description: Audio High-Resolution ADC clock
> +      - description: Audio High-Resolution ADC SineGen clock
> +      - description: Audio ADDA6 High-Resolution ADC clock
> +      - description: Tertiary ADDA DAC clock
> +      - description: Tertiary ADDA DAC pre-distortion clock
> +      - description: Tertiary ADDA DAC Sine Generator clock
> +      - description: Tertiary ADDA DAC High-Resolution clock
> +      - description: Audio infra sys clock
> +      - description: Audio infra 26M clock
> +      - description: Mux for audio clock
> +      - description: Mux for audio internal bus clock
> +      - description: Mux main divider by 4
> +      - description: Primary audio mux
> +      - description: Primary audio PLL
> +      - description: Secondary audio mux
> +      - description: Secondary audio PLL
> +      - description: Primary audio en-generator clock
> +      - description: Primary PLL divider by 4 for IEC
> +      - description: Secondary audio en-generator clock
> +      - description: Secondary PLL divider by 4 for IEC
> +      - description: Mux selector for I2S port 0
> +      - description: Mux selector for I2S port 1
> +      - description: Mux selector for I2S port 2
> +      - description: Mux selector for I2S port 3
> +      - description: Mux selector for I2S port 4
> +      - description: Mux selector for I2S port 5
> +      - description: Mux selector for I2S port 6
> +      - description: Mux selector for I2S port 7
> +      - description: Mux selector for I2S port 8
> +      - description: Mux selector for I2S port 9
> +      - description: APLL1 and APLL2 divider for I2S port 0
> +      - description: APLL1 and APLL2 divider for I2S port 1
> +      - description: APLL1 and APLL2 divider for I2S port 2
> +      - description: APLL1 and APLL2 divider for I2S port 3
> +      - description: APLL1 and APLL2 divider for I2S port 4
> +      - description: APLL1 and APLL2 divider for IEC
> +      - description: APLL1 and APLL2 divider for I2S port 5
> +      - description: APLL1 and APLL2 divider for I2S port 6
> +      - description: APLL1 and APLL2 divider for I2S port 7
> +      - description: APLL1 and APLL2 divider for I2S port 8
> +      - description: APLL1 and APLL2 divider for I2S port 9
> +      - description: Top mux for audio subsystem
> +      - description: 26MHz clock for audio subsystem
>  
>    clock-names:
>      items:
>        - const: aud_afe_clk
>        - const: aud_dac_clk
>        - const: aud_dac_predis_clk
> +      - const: aud_adc_clk
> +      - const: aud_adda6_adc_clk
> +      - const: aud_apll22m_clk
> +      - const: aud_apll24m_clk
> +      - const: aud_apll1_tuner_clk
> +      - const: aud_apll2_tuner_clk
> +      - const: aud_tdm_clk
> +      - const: aud_tml_clk
> +      - const: aud_nle
> +      - const: aud_dac_hires_clk
> +      - const: aud_adc_hires_clk
> +      - const: aud_adc_hires_tml
> +      - const: aud_adda6_adc_hires_clk
> +      - const: aud_3rd_dac_clk
> +      - const: aud_3rd_dac_predis_clk
> +      - const: aud_3rd_dac_tml
> +      - const: aud_3rd_dac_hires_clk
>        - const: aud_infra_clk
>        - const: aud_infra_26m_clk
> +      - const: top_mux_audio
> +      - const: top_mux_audio_int
> +      - const: top_mainpll_d4_d4
> +      - const: top_mux_aud_1
> +      - const: top_apll1_ck
> +      - const: top_mux_aud_2
> +      - const: top_apll2_ck
> +      - const: top_mux_aud_eng1
> +      - const: top_apll1_d4
> +      - const: top_mux_aud_eng2
> +      - const: top_apll2_d4
> +      - const: top_i2s0_m_sel
> +      - const: top_i2s1_m_sel
> +      - const: top_i2s2_m_sel
> +      - const: top_i2s3_m_sel
> +      - const: top_i2s4_m_sel
> +      - const: top_i2s5_m_sel
> +      - const: top_i2s6_m_sel
> +      - const: top_i2s7_m_sel
> +      - const: top_i2s8_m_sel
> +      - const: top_i2s9_m_sel
> +      - const: top_apll12_div0
> +      - const: top_apll12_div1
> +      - const: top_apll12_div2
> +      - const: top_apll12_div3
> +      - const: top_apll12_div4
> +      - const: top_apll12_divb
> +      - const: top_apll12_div5
> +      - const: top_apll12_div6
> +      - const: top_apll12_div7
> +      - const: top_apll12_div8
> +      - const: top_apll12_div9
> +      - const: top_mux_audio_h
> +      - const: top_clk26m_clk
>  
>  required:
>    - compatible
> @@ -83,23 +185,69 @@ examples:
>      afe: mt8192-afe-pcm {
>          compatible = "mediatek,mt8192-audio";
>          interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&audsys CLK_AUD_AFE>, <&audsys CLK_AUD_DAC>,
> +                 <&audsys CLK_AUD_DAC_PREDIS>, <&audsys CLK_AUD_ADC>,
> +                 <&audsys CLK_AUD_ADDA6_ADC>, <&audsys CLK_AUD_22M>,
> +                 <&audsys CLK_AUD_24M>, <&audsys CLK_AUD_APLL_TUNER>,
> +                 <&audsys CLK_AUD_APLL2_TUNER>, <&audsys CLK_AUD_TDM>,
> +                 <&audsys CLK_AUD_TML>, <&audsys CLK_AUD_NLE>,
> +                 <&audsys CLK_AUD_DAC_HIRES>, <&audsys CLK_AUD_ADC_HIRES>,
> +                 <&audsys CLK_AUD_ADC_HIRES_TML>, <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> +                 <&audsys CLK_AUD_3RD_DAC>, <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> +                 <&audsys CLK_AUD_3RD_DAC_TML>, <&audsys CLK_AUD_3RD_DAC_HIRES>,
> +                 <&infracfg CLK_INFRA_AUDIO>, <&infracfg CLK_INFRA_AUDIO_26M_B>,
> +                 <&topckgen CLK_TOP_AUDIO_SEL>, <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> +                 <&topckgen CLK_TOP_MAINPLL_D4_D4>, <&topckgen CLK_TOP_AUD_1_SEL>,
> +                 <&topckgen CLK_TOP_APLL1>, <&topckgen CLK_TOP_AUD_2_SEL>,
> +                 <&topckgen CLK_TOP_APLL2>, <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> +                 <&topckgen CLK_TOP_APLL1_D4>, <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> +                 <&topckgen CLK_TOP_APLL2_D4>, <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> +                 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> +                 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> +                 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> +                 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> +                 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, <&topckgen CLK_TOP_APLL12_DIV0>,
> +                 <&topckgen CLK_TOP_APLL12_DIV1>, <&topckgen CLK_TOP_APLL12_DIV2>,
> +                 <&topckgen CLK_TOP_APLL12_DIV3>, <&topckgen CLK_TOP_APLL12_DIV4>,
> +                 <&topckgen CLK_TOP_APLL12_DIVB>, <&topckgen CLK_TOP_APLL12_DIV5>,
> +                 <&topckgen CLK_TOP_APLL12_DIV6>, <&topckgen CLK_TOP_APLL12_DIV7>,
> +                 <&topckgen CLK_TOP_APLL12_DIV8>, <&topckgen CLK_TOP_APLL12_DIV9>,
> +                 <&topckgen CLK_TOP_AUDIO_H_SEL>, <&clk26m>;
> +        clock-names = "aud_afe_clk", "aud_dac_clk",
> +                      "aud_dac_predis_clk", "aud_adc_clk",
> +                      "aud_adda6_adc_clk", "aud_apll22m_clk",
> +                      "aud_apll24m_clk", "aud_apll1_tuner_clk",
> +                      "aud_apll2_tuner_clk", "aud_tdm_clk",
> +                      "aud_tml_clk", "aud_nle",
> +                      "aud_dac_hires_clk", "aud_adc_hires_clk",
> +                      "aud_adc_hires_tml", "aud_adda6_adc_hires_clk",
> +                      "aud_3rd_dac_clk", "aud_3rd_dac_predis_clk",
> +                      "aud_3rd_dac_tml", "aud_3rd_dac_hires_clk",
> +                      "aud_infra_clk", "aud_infra_26m_clk",
> +                      "top_mux_audio", "top_mux_audio_int",
> +                      "top_mainpll_d4_d4", "top_mux_aud_1",
> +                      "top_apll1_ck", "top_mux_aud_2",
> +                      "top_apll2_ck", "top_mux_aud_eng1",
> +                      "top_apll1_d4", "top_mux_aud_eng2",
> +                      "top_apll2_d4", "top_i2s0_m_sel",
> +                      "top_i2s1_m_sel", "top_i2s2_m_sel",
> +                      "top_i2s3_m_sel", "top_i2s4_m_sel",
> +                      "top_i2s5_m_sel", "top_i2s6_m_sel",
> +                      "top_i2s7_m_sel", "top_i2s8_m_sel",
> +                      "top_i2s9_m_sel", "top_apll12_div0",
> +                      "top_apll12_div1", "top_apll12_div2",
> +                      "top_apll12_div3", "top_apll12_div4",
> +                      "top_apll12_divb", "top_apll12_div5",
> +                      "top_apll12_div6", "top_apll12_div7",
> +                      "top_apll12_div8", "top_apll12_div9",
> +                      "top_mux_audio_h", "top_clk26m_clk";
> +        memory-region = <&afe_dma_mem>;
> +        power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
>          resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>;
>          reset-names = "audiosys";
>          mediatek,apmixedsys = <&apmixedsys>;
>          mediatek,infracfg = <&infracfg>;
>          mediatek,topckgen = <&topckgen>;
> -        power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
> -        clocks = <&audsys CLK_AUD_AFE>,
> -                 <&audsys CLK_AUD_DAC>,
> -                 <&audsys CLK_AUD_DAC_PREDIS>,
> -                 <&infracfg CLK_INFRA_AUDIO>,
> -                 <&infracfg CLK_INFRA_AUDIO_26M_B>;
> -        clock-names = "aud_afe_clk",
> -                      "aud_dac_clk",
> -                      "aud_dac_predis_clk",
> -                      "aud_infra_clk",
> -                      "aud_infra_26m_clk";
> -        memory-region = <&afe_dma_mem>;
>      };
>  
>  ...

Re: [PATCH 1/4] dt-bindings: mtd: jedec,spi-nor: Add Winbond W25Q(32/64/128/256)JWM

[AngeloGioacchino Del Regno]

Il 15/01/26 14:16, Pratyush Yadav ha scritto:
> On Thu, Jan 15 2026, AngeloGioacchino Del Regno wrote:
> 
>> Add Winbond W25Q32JWM, W25Q64JWM, W25Q128JWM, W25Q256JWM to the
>> allowed compatible strings pattern.
>>
>> This also resolves a dtbs_check warning happening on all of the
>> MediaTek MT8192 Chromebooks devicetrees (for winbond,w25q64jwm).
> 
> We normally don't allow adding any more device-specific compatibles.
> This list here is only for legacy DTS. You should be using
> "jedec,spi-nor" in your device trees.
> 

Ah, okay, didn't know that.

That's actually making things easier for me honestly as removing the
model string is a 10 seconds change, so I'm totally happy with that.

Ignore this commit then.

Thanks!
Angelo

>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
>> index 587af4968255..2db446c9ca9b 100644
>> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
>> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
>> @@ -29,7 +29,7 @@ properties:
>>                 (sst,)?sst26wf016b|\
>>                 (sst,)?sst25wf(040b|080)|\
>>                 winbond,w25x(80|32)|\
>> -              (winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$"
>> +              (winbond,)?w25q(16|32(w|dw)?|64(dw|jwm)?|80bl|128(fw|jwm)?|256(jwm)?))$"
>>             - const: jedec,spi-nor
>>         - items:
>>             - enum:
> 

Re: [PATCH 1/4] dt-bindings: mtd: jedec,spi-nor: Add Winbond W25Q(32/64/128/256)JWM

[Pratyush Yadav]

On Thu, Jan 15 2026, AngeloGioacchino Del Regno wrote:

> Il 15/01/26 14:16, Pratyush Yadav ha scritto:
>> On Thu, Jan 15 2026, AngeloGioacchino Del Regno wrote:
>> 
>>> Add Winbond W25Q32JWM, W25Q64JWM, W25Q128JWM, W25Q256JWM to the
>>> allowed compatible strings pattern.
>>>
>>> This also resolves a dtbs_check warning happening on all of the
>>> MediaTek MT8192 Chromebooks devicetrees (for winbond,w25q64jwm).
>> We normally don't allow adding any more device-specific compatibles.
>> This list here is only for legacy DTS. You should be using
>> "jedec,spi-nor" in your device trees.
>> 
>
> Ah, okay, didn't know that.
>
> That's actually making things easier for me honestly as removing the
> model string is a 10 seconds change, so I'm totally happy with that.

Awesome! Thanks.

[...]

-- 
Regards,
Pratyush Yadav

Re: [PATCH 2/4] ASoC: dt-bindings: mt8192-afe-pcm: Fix clocks and clock-names

[AngeloGioacchino Del Regno]

Il 15/01/26 14:28, Eugen Hristev ha scritto:
> 
> 
> On 1/15/26 14:56, AngeloGioacchino Del Regno wrote:
>> Both clocks and clock-names are missing (a lot of) entries: add
>> all the used audio clocks and their description and also fix the
>> example node.
> 
> Hi Angelo,
> 
> This does not really look like a fix, if it was a fix I would expect a
> Fixes tag, otherwise, it looks like you are adding a lot of clocks which
> were not defined before
> 
> Eugen

Hey. Yes, right, that makes sense.

I wonder if the Fixes tag can be added while applying.

In case...


Fixes: c861af7861aa ("ASoC: dt-bindings: mediatek: mt8192: re-add audio afe document")

Cheers,
Angelo

>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   .../bindings/sound/mt8192-afe-pcm.yaml        | 176 ++++++++++++++++--
>>   1 file changed, 162 insertions(+), 14 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
>> index 8ddf49b0040d..16ae3328f70d 100644
>> --- a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
>> +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
>> @@ -47,16 +47,118 @@ properties:
>>         - description: AFE clock
>>         - description: ADDA DAC clock
>>         - description: ADDA DAC pre-distortion clock
>> -      - description: audio infra sys clock
>> -      - description: audio infra 26M clock
>> +      - description: ADDA ADC clock
>> +      - description: ADDA6 ADC clock
>> +      - description: Audio low-jitter 22.5792m clock
>> +      - description: Audio low-jitter 24.576m clock
>> +      - description: Audio PLL1 tuner clock
>> +      - description: Audio PLL2 tuner clock
>> +      - description: Audio Time-Division Multiplexing interface clock
>> +      - description: ADDA ADC Sine Generator clock
>> +      - description: audio Non-LE clock
>> +      - description: Audio DAC High-Resolution clock
>> +      - description: Audio High-Resolution ADC clock
>> +      - description: Audio High-Resolution ADC SineGen clock
>> +      - description: Audio ADDA6 High-Resolution ADC clock
>> +      - description: Tertiary ADDA DAC clock
>> +      - description: Tertiary ADDA DAC pre-distortion clock
>> +      - description: Tertiary ADDA DAC Sine Generator clock
>> +      - description: Tertiary ADDA DAC High-Resolution clock
>> +      - description: Audio infra sys clock
>> +      - description: Audio infra 26M clock
>> +      - description: Mux for audio clock
>> +      - description: Mux for audio internal bus clock
>> +      - description: Mux main divider by 4
>> +      - description: Primary audio mux
>> +      - description: Primary audio PLL
>> +      - description: Secondary audio mux
>> +      - description: Secondary audio PLL
>> +      - description: Primary audio en-generator clock
>> +      - description: Primary PLL divider by 4 for IEC
>> +      - description: Secondary audio en-generator clock
>> +      - description: Secondary PLL divider by 4 for IEC
>> +      - description: Mux selector for I2S port 0
>> +      - description: Mux selector for I2S port 1
>> +      - description: Mux selector for I2S port 2
>> +      - description: Mux selector for I2S port 3
>> +      - description: Mux selector for I2S port 4
>> +      - description: Mux selector for I2S port 5
>> +      - description: Mux selector for I2S port 6
>> +      - description: Mux selector for I2S port 7
>> +      - description: Mux selector for I2S port 8
>> +      - description: Mux selector for I2S port 9
>> +      - description: APLL1 and APLL2 divider for I2S port 0
>> +      - description: APLL1 and APLL2 divider for I2S port 1
>> +      - description: APLL1 and APLL2 divider for I2S port 2
>> +      - description: APLL1 and APLL2 divider for I2S port 3
>> +      - description: APLL1 and APLL2 divider for I2S port 4
>> +      - description: APLL1 and APLL2 divider for IEC
>> +      - description: APLL1 and APLL2 divider for I2S port 5
>> +      - description: APLL1 and APLL2 divider for I2S port 6
>> +      - description: APLL1 and APLL2 divider for I2S port 7
>> +      - description: APLL1 and APLL2 divider for I2S port 8
>> +      - description: APLL1 and APLL2 divider for I2S port 9
>> +      - description: Top mux for audio subsystem
>> +      - description: 26MHz clock for audio subsystem
>>   
>>     clock-names:
>>       items:
>>         - const: aud_afe_clk
>>         - const: aud_dac_clk
>>         - const: aud_dac_predis_clk
>> +      - const: aud_adc_clk
>> +      - const: aud_adda6_adc_clk
>> +      - const: aud_apll22m_clk
>> +      - const: aud_apll24m_clk
>> +      - const: aud_apll1_tuner_clk
>> +      - const: aud_apll2_tuner_clk
>> +      - const: aud_tdm_clk
>> +      - const: aud_tml_clk
>> +      - const: aud_nle
>> +      - const: aud_dac_hires_clk
>> +      - const: aud_adc_hires_clk
>> +      - const: aud_adc_hires_tml
>> +      - const: aud_adda6_adc_hires_clk
>> +      - const: aud_3rd_dac_clk
>> +      - const: aud_3rd_dac_predis_clk
>> +      - const: aud_3rd_dac_tml
>> +      - const: aud_3rd_dac_hires_clk
>>         - const: aud_infra_clk
>>         - const: aud_infra_26m_clk
>> +      - const: top_mux_audio
>> +      - const: top_mux_audio_int
>> +      - const: top_mainpll_d4_d4
>> +      - const: top_mux_aud_1
>> +      - const: top_apll1_ck
>> +      - const: top_mux_aud_2
>> +      - const: top_apll2_ck
>> +      - const: top_mux_aud_eng1
>> +      - const: top_apll1_d4
>> +      - const: top_mux_aud_eng2
>> +      - const: top_apll2_d4
>> +      - const: top_i2s0_m_sel
>> +      - const: top_i2s1_m_sel
>> +      - const: top_i2s2_m_sel
>> +      - const: top_i2s3_m_sel
>> +      - const: top_i2s4_m_sel
>> +      - const: top_i2s5_m_sel
>> +      - const: top_i2s6_m_sel
>> +      - const: top_i2s7_m_sel
>> +      - const: top_i2s8_m_sel
>> +      - const: top_i2s9_m_sel
>> +      - const: top_apll12_div0
>> +      - const: top_apll12_div1
>> +      - const: top_apll12_div2
>> +      - const: top_apll12_div3
>> +      - const: top_apll12_div4
>> +      - const: top_apll12_divb
>> +      - const: top_apll12_div5
>> +      - const: top_apll12_div6
>> +      - const: top_apll12_div7
>> +      - const: top_apll12_div8
>> +      - const: top_apll12_div9
>> +      - const: top_mux_audio_h
>> +      - const: top_clk26m_clk
>>   
>>   required:
>>     - compatible
>> @@ -83,23 +185,69 @@ examples:
>>       afe: mt8192-afe-pcm {
>>           compatible = "mediatek,mt8192-audio";
>>           interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
>> +        clocks = <&audsys CLK_AUD_AFE>, <&audsys CLK_AUD_DAC>,
>> +                 <&audsys CLK_AUD_DAC_PREDIS>, <&audsys CLK_AUD_ADC>,
>> +                 <&audsys CLK_AUD_ADDA6_ADC>, <&audsys CLK_AUD_22M>,
>> +                 <&audsys CLK_AUD_24M>, <&audsys CLK_AUD_APLL_TUNER>,
>> +                 <&audsys CLK_AUD_APLL2_TUNER>, <&audsys CLK_AUD_TDM>,
>> +                 <&audsys CLK_AUD_TML>, <&audsys CLK_AUD_NLE>,
>> +                 <&audsys CLK_AUD_DAC_HIRES>, <&audsys CLK_AUD_ADC_HIRES>,
>> +                 <&audsys CLK_AUD_ADC_HIRES_TML>, <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
>> +                 <&audsys CLK_AUD_3RD_DAC>, <&audsys CLK_AUD_3RD_DAC_PREDIS>,
>> +                 <&audsys CLK_AUD_3RD_DAC_TML>, <&audsys CLK_AUD_3RD_DAC_HIRES>,
>> +                 <&infracfg CLK_INFRA_AUDIO>, <&infracfg CLK_INFRA_AUDIO_26M_B>,
>> +                 <&topckgen CLK_TOP_AUDIO_SEL>, <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
>> +                 <&topckgen CLK_TOP_MAINPLL_D4_D4>, <&topckgen CLK_TOP_AUD_1_SEL>,
>> +                 <&topckgen CLK_TOP_APLL1>, <&topckgen CLK_TOP_AUD_2_SEL>,
>> +                 <&topckgen CLK_TOP_APLL2>, <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
>> +                 <&topckgen CLK_TOP_APLL1_D4>, <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
>> +                 <&topckgen CLK_TOP_APLL2_D4>, <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
>> +                 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
>> +                 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
>> +                 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
>> +                 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
>> +                 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, <&topckgen CLK_TOP_APLL12_DIV0>,
>> +                 <&topckgen CLK_TOP_APLL12_DIV1>, <&topckgen CLK_TOP_APLL12_DIV2>,
>> +                 <&topckgen CLK_TOP_APLL12_DIV3>, <&topckgen CLK_TOP_APLL12_DIV4>,
>> +                 <&topckgen CLK_TOP_APLL12_DIVB>, <&topckgen CLK_TOP_APLL12_DIV5>,
>> +                 <&topckgen CLK_TOP_APLL12_DIV6>, <&topckgen CLK_TOP_APLL12_DIV7>,
>> +                 <&topckgen CLK_TOP_APLL12_DIV8>, <&topckgen CLK_TOP_APLL12_DIV9>,
>> +                 <&topckgen CLK_TOP_AUDIO_H_SEL>, <&clk26m>;
>> +        clock-names = "aud_afe_clk", "aud_dac_clk",
>> +                      "aud_dac_predis_clk", "aud_adc_clk",
>> +                      "aud_adda6_adc_clk", "aud_apll22m_clk",
>> +                      "aud_apll24m_clk", "aud_apll1_tuner_clk",
>> +                      "aud_apll2_tuner_clk", "aud_tdm_clk",
>> +                      "aud_tml_clk", "aud_nle",
>> +                      "aud_dac_hires_clk", "aud_adc_hires_clk",
>> +                      "aud_adc_hires_tml", "aud_adda6_adc_hires_clk",
>> +                      "aud_3rd_dac_clk", "aud_3rd_dac_predis_clk",
>> +                      "aud_3rd_dac_tml", "aud_3rd_dac_hires_clk",
>> +                      "aud_infra_clk", "aud_infra_26m_clk",
>> +                      "top_mux_audio", "top_mux_audio_int",
>> +                      "top_mainpll_d4_d4", "top_mux_aud_1",
>> +                      "top_apll1_ck", "top_mux_aud_2",
>> +                      "top_apll2_ck", "top_mux_aud_eng1",
>> +                      "top_apll1_d4", "top_mux_aud_eng2",
>> +                      "top_apll2_d4", "top_i2s0_m_sel",
>> +                      "top_i2s1_m_sel", "top_i2s2_m_sel",
>> +                      "top_i2s3_m_sel", "top_i2s4_m_sel",
>> +                      "top_i2s5_m_sel", "top_i2s6_m_sel",
>> +                      "top_i2s7_m_sel", "top_i2s8_m_sel",
>> +                      "top_i2s9_m_sel", "top_apll12_div0",
>> +                      "top_apll12_div1", "top_apll12_div2",
>> +                      "top_apll12_div3", "top_apll12_div4",
>> +                      "top_apll12_divb", "top_apll12_div5",
>> +                      "top_apll12_div6", "top_apll12_div7",
>> +                      "top_apll12_div8", "top_apll12_div9",
>> +                      "top_mux_audio_h", "top_clk26m_clk";
>> +        memory-region = <&afe_dma_mem>;
>> +        power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
>>           resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>;
>>           reset-names = "audiosys";
>>           mediatek,apmixedsys = <&apmixedsys>;
>>           mediatek,infracfg = <&infracfg>;
>>           mediatek,topckgen = <&topckgen>;
>> -        power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
>> -        clocks = <&audsys CLK_AUD_AFE>,
>> -                 <&audsys CLK_AUD_DAC>,
>> -                 <&audsys CLK_AUD_DAC_PREDIS>,
>> -                 <&infracfg CLK_INFRA_AUDIO>,
>> -                 <&infracfg CLK_INFRA_AUDIO_26M_B>;
>> -        clock-names = "aud_afe_clk",
>> -                      "aud_dac_clk",
>> -                      "aud_dac_predis_clk",
>> -                      "aud_infra_clk",
>> -                      "aud_infra_26m_clk";
>> -        memory-region = <&afe_dma_mem>;
>>       };
>>   
>>   ...
> 


-- 
AngeloGioacchino Del Regno
Senior Software Engineer

Collabora Ltd.
Platinum Building, St John's Innovation Park, Cambridge CB4 0DS, UK
Registered in England & Wales, no. 5513718

Re: [PATCH 2/4] ASoC: dt-bindings: mt8192-afe-pcm: Fix clocks and clock-names

[Mark Brown]

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On Thu, Jan 15, 2026 at 03:46:18PM +0100, AngeloGioacchino Del Regno wrote:

> I wonder if the Fixes tag can be added while applying.

Yeah, b4 will DTRT by default there.

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Re: (subset) [PATCH 0/4] MediaTek MT8192 dtbs_check fixes

[Mark Brown]

On Thu, 15 Jan 2026 13:56:20 +0100, AngeloGioacchino Del Regno wrote:
> This series addresses most of the MediaTek MT8192 dtbs_check warnings
> by adding a missing SPI NOR flash compatible string and fixing both
> the audsys binding and devicetree node name.
> 
> AngeloGioacchino Del Regno (4):
>   dt-bindings: mtd: jedec,spi-nor: Add Winbond W25Q(32/64/128/256)JWM
>   ASoC: dt-bindings: mt8192-afe-pcm: Fix clocks and clock-names
>   dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant
>   arm64: dts: mediatek: mt8192: Rename mt8192-afe-pcm to
>     audio-controller
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[2/4] ASoC: dt-bindings: mt8192-afe-pcm: Fix clocks and clock-names
      commit: 60e8451be1f7af4b51540f2cfd65c9c85af752e9

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

Re: [PATCH 4/4] arm64: dts: mediatek: mt8192: Rename mt8192-afe-pcm to audio-controller

[Rob Herring]

On Thu, Jan 15, 2026 at 01:56:24PM +0100, AngeloGioacchino Del Regno wrote:
> Device tree nodes should have generic names, and this one doesn't.
> Rename the mt8192-afe-pcm subnode of audsys to `audio-controller`.
> 
> This commit brings no functional changes, but resolves dtbs_check
> warnings.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 3/4] dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant

[Rob Herring (Arm)]

On Thu, 15 Jan 2026 13:56:23 +0100, AngeloGioacchino Del Regno wrote:
> Add support for the mediatek,mt8192-audsys compatible, which uses
> a different audio controller (mt8192-afe-pcm) compared to mt8183
> and mt2701.
> 
> This resolves a dtbs_check warning on all MT8192 devicetrees.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  .../arm/mediatek/mediatek,audsys.yaml         | 46 +++++++++++++------
>  1 file changed, 33 insertions(+), 13 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 2/4] ASoC: dt-bindings: mt8192-afe-pcm: Fix clocks and clock-names

[Rob Herring (Arm)]

On Thu, 15 Jan 2026 13:56:22 +0100, AngeloGioacchino Del Regno wrote:
> Both clocks and clock-names are missing (a lot of) entries: add
> all the used audio clocks and their description and also fix the
> example node.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  .../bindings/sound/mt8192-afe-pcm.yaml        | 176 ++++++++++++++++--
>  1 file changed, 162 insertions(+), 14 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: (subset) [PATCH 0/4] MediaTek MT8192 dtbs_check fixes

[AngeloGioacchino Del Regno]

On Thu, 15 Jan 2026 13:56:20 +0100, AngeloGioacchino Del Regno wrote:
> This series addresses most of the MediaTek MT8192 dtbs_check warnings
> by adding a missing SPI NOR flash compatible string and fixing both
> the audsys binding and devicetree node name.
> 
> AngeloGioacchino Del Regno (4):
>   dt-bindings: mtd: jedec,spi-nor: Add Winbond W25Q(32/64/128/256)JWM
>   ASoC: dt-bindings: mt8192-afe-pcm: Fix clocks and clock-names
>   dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant
>   arm64: dts: mediatek: mt8192: Rename mt8192-afe-pcm to
>     audio-controller
> 
> [...]

Applied to v6.19-next/dts64, thanks!

[3/4] dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant
      commit: a8e3d66ff5c0c37e7c10b3e486d2c5047bf9cf2b
[4/4] arm64: dts: mediatek: mt8192: Rename mt8192-afe-pcm to audio-controller
      commit: 25556c12f4d3edc2f614f752f204c3941697b30a

Cheers,
Angelo

Re: [PATCH 3/4] dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant

[Rob Herring]

On Thu, Jan 15, 2026 at 6:56 AM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Add support for the mediatek,mt8192-audsys compatible, which uses
> a different audio controller (mt8192-afe-pcm) compared to mt8183
> and mt2701.
>
> This resolves a dtbs_check warning on all MT8192 devicetrees.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  .../arm/mediatek/mediatek,audsys.yaml         | 46 +++++++++++++------
>  1 file changed, 33 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml
> index f3a761cbd0fd..09a6c16e7e82 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml
> @@ -48,19 +48,39 @@ required:
>    - compatible
>    - '#clock-cells'
>
> -if:
> -  properties:
> -    compatible:
> -      contains:
> -        const: mediatek,mt8183-audiosys
> -then:
> -  properties:
> -    audio-controller:
> -      $ref: /schemas/sound/mediatek,mt8183-audio.yaml#
> -else:
> -  properties:
> -    audio-controller:
> -      $ref: /schemas/sound/mediatek,mt2701-audio.yaml#
> +allOf:
> + - if:

Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml:52:2:
[warning] wrong indentation: expected 2 but found 1 (indentation)


> +     properties:
> +       compatible:
> +         contains:
> +           enum:
> +             - mediatek,mt2701-audsys
> +             - mediatek,mt7622-audsys
> +   then:
> +     properties:
> +       audio-controller:
> +         $ref: /schemas/sound/mediatek,mt2701-audio.yaml#
> +
> + - if:
> +     properties:
> +       compatible:
> +         contains:
> +           const: mediatek,mt8183-audiosys
> +   then:
> +     properties:
> +       audio-controller:
> +         $ref: /schemas/sound/mediatek,mt8183-audio.yaml#
> +
> + - if:
> +     properties:
> +       compatible:
> +         contains:
> +           const: mediatek,mt8192-audsys
> +   then:
> +     properties:
> +       audio-controller:
> +         $ref: /schemas/sound/mt8192-afe-pcm.yaml#
> +
>

Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml:84:1:
[warning] too many blank lines (2 > 1) (empty-lines)

Please fix as these are warnings in linux-next now.


>  additionalProperties: false
>
> --
> 2.52.0
>

Re: [PATCH 3/4] dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant

[AngeloGioacchino Del Regno]

Il 10/02/26 14:41, Rob Herring ha scritto:
> On Thu, Jan 15, 2026 at 6:56 AM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> Add support for the mediatek,mt8192-audsys compatible, which uses
>> a different audio controller (mt8192-afe-pcm) compared to mt8183
>> and mt2701.
>>
>> This resolves a dtbs_check warning on all MT8192 devicetrees.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   .../arm/mediatek/mediatek,audsys.yaml         | 46 +++++++++++++------
>>   1 file changed, 33 insertions(+), 13 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml
>> index f3a761cbd0fd..09a6c16e7e82 100644
>> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml
>> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml
>> @@ -48,19 +48,39 @@ required:
>>     - compatible
>>     - '#clock-cells'
>>
>> -if:
>> -  properties:
>> -    compatible:
>> -      contains:
>> -        const: mediatek,mt8183-audiosys
>> -then:
>> -  properties:
>> -    audio-controller:
>> -      $ref: /schemas/sound/mediatek,mt8183-audio.yaml#
>> -else:
>> -  properties:
>> -    audio-controller:
>> -      $ref: /schemas/sound/mediatek,mt2701-audio.yaml#
>> +allOf:
>> + - if:
> 
> Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml:52:2:
> [warning] wrong indentation: expected 2 but found 1 (indentation)
> 
> 
>> +     properties:
>> +       compatible:
>> +         contains:
>> +           enum:
>> +             - mediatek,mt2701-audsys
>> +             - mediatek,mt7622-audsys
>> +   then:
>> +     properties:
>> +       audio-controller:
>> +         $ref: /schemas/sound/mediatek,mt2701-audio.yaml#
>> +
>> + - if:
>> +     properties:
>> +       compatible:
>> +         contains:
>> +           const: mediatek,mt8183-audiosys
>> +   then:
>> +     properties:
>> +       audio-controller:
>> +         $ref: /schemas/sound/mediatek,mt8183-audio.yaml#
>> +
>> + - if:
>> +     properties:
>> +       compatible:
>> +         contains:
>> +           const: mediatek,mt8192-audsys
>> +   then:
>> +     properties:
>> +       audio-controller:
>> +         $ref: /schemas/sound/mt8192-afe-pcm.yaml#
>> +
>>
> 
> Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml:84:1:
> [warning] too many blank lines (2 > 1) (empty-lines)
> 
> Please fix as these are warnings in linux-next now.
> 

Ack. Sorry for the mistakes. Not sure how this happened.

Let me see when I can get some minutes to get this addressed.

Cheers,
Angelo

> 
>>   additionalProperties: false
>>
>> --
>> 2.52.0
>>

Re: [PATCH 3/4] dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant

[Krzysztof Kozlowski]

On 10/02/2026 15:28, AngeloGioacchino Del Regno wrote:
>>> + - if:
>>> +     properties:
>>> +       compatible:
>>> +         contains:
>>> +           const: mediatek,mt8192-audsys
>>> +   then:
>>> +     properties:
>>> +       audio-controller:
>>> +         $ref: /schemas/sound/mt8192-afe-pcm.yaml#
>>> +
>>>
>>
>> Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml:84:1:
>> [warning] too many blank lines (2 > 1) (empty-lines)
>>
>> Please fix as these are warnings in linux-next now.
>>
> 
> Ack. Sorry for the mistakes. Not sure how this happened.
> 
> Let me see when I can get some minutes to get this addressed.
> 

This was 2 weeks ago.

Warning is still there in next. Please revert your patch or take the fix
from mailing list, but anyway this should not be broken for two weeks.

Best regards,
Krzysztof

Re: [PATCH 3/4] dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant

[AngeloGioacchino Del Regno]

Il 06/03/26 10:10, Krzysztof Kozlowski ha scritto:
> On 10/02/2026 15:28, AngeloGioacchino Del Regno wrote:
>>>> + - if:
>>>> +     properties:
>>>> +       compatible:
>>>> +         contains:
>>>> +           const: mediatek,mt8192-audsys
>>>> +   then:
>>>> +     properties:
>>>> +       audio-controller:
>>>> +         $ref: /schemas/sound/mt8192-afe-pcm.yaml#
>>>> +
>>>>
>>>
>>> Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml:84:1:
>>> [warning] too many blank lines (2 > 1) (empty-lines)
>>>
>>> Please fix as these are warnings in linux-next now.
>>>
>>
>> Ack. Sorry for the mistakes. Not sure how this happened.
>>
>> Let me see when I can get some minutes to get this addressed.
>>
> 
> This was 2 weeks ago.
> 
> Warning is still there in next. Please revert your patch or take the fix
> from mailing list, but anyway this should not be broken for two weeks.
> 
It's done. Sorry for the wait, but it's been extremely busy days around here.

Cheers,
Angelo