From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36B2E13F425; Mon, 8 Apr 2024 15:05:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712588725; cv=none; b=p52/rjkAHWmJT/4Qf/0IXmfLARAYG86rjnPq/e54q8f4leyTjyx4Spku4BR/FFHpCWacLvJXMT6Rp6aNKI82xY98oOkawhSUXEetbIsnxqjs5UtBujHDht0u0x18iUP0/RsBpK4EKc6r83tTTN/vq4suX0ZCVjDY5IW3VLENsi8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712588725; c=relaxed/simple; bh=JQQaCwBNLuDCVNbN4RvS+OFwumZuXU9MQIz0FYSG1zk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RWw7aE1No/P56GxbsarKgAPp6n8lduR/M+VdsHKr/2BLiYLSr+CunU483irALweFWAhE8VrkoQOdUu7OqdALEKid2TYYqmgfLHlmhmoh6VR79Cw+OxlhEVvTv0X7YAp649ki31SsnN5IFZ3Oli6z4ZE8ciei36beyT204qXs6ws= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Received: from i5e8616c3.versanet.de ([94.134.22.195] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rtqYK-0007Xz-Fd; Mon, 08 Apr 2024 17:04:56 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Chukun Pan , Jonas Karlman Cc: Conor Dooley , Krzysztof Kozlowski , Rob Herring , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 1/1] arm64: dts: rockchip: enable onboard spi flash for rock-3a Date: Mon, 08 Apr 2024 17:04:55 +0200 Message-ID: <3066222.xgJ6IN8ObU@diego> In-Reply-To: References: <20240408124005.182565-1-amadeus@jmu.edu.cn> <421ab43b-ff92-41c6-9904-3c7681c926be@kwiboo.se> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Am Montag, 8. April 2024, 16:56:59 CEST schrieb Jonas Karlman: > On 2024-04-08 16:44, Jonas Karlman wrote: > > On 2024-04-08 14:40, Chukun Pan wrote: > >> There is a mx25u12835f spi flash on this board, enable it. > >> > >> [ 2.525805] spi-nor spi4.0: mx25u12835f (16384 Kbytes) > >> > >> Signed-off-by: Chukun Pan > >> --- > >> arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 12 ++++++++++++ > >> 1 file changed, 12 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts > >> index a5e974ea659e..d8738cc47c73 100644 > >> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts > >> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts > >> @@ -757,6 +757,18 @@ &sdmmc2 { > >> status = "okay"; > >> }; > >> > >> +&sfc { > > > > This is missing: > > > > #address-cells = <1>; > > #size-cells = <0>; > > > >> + status = "okay"; > >> + > >> + flash@0 { > >> + compatible = "jedec,spi-nor"; > >> + reg = <0x0>; > >> + spi-max-frequency = <50000000>; > > > > At least in U-Boot the spi clock only support 24, 100 or 200 mhz and I > > am pretty sure the spi flash support 100mhz, so I would suggest you test > > with 100mhz, same as used on other rk356x boards. > > Sorry, looked at spi clock instead of sfc clock. > sfc clock support 24, 50, 75, 100, 125 and 150 mhz. I think in some previous discussion the agreement was that the node should specify the max frequency the flash supports and have the controller worry about its own clock ranges. Though in this case the 50MHz for the flash even matches the clock frequency supported by the sfc