From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0158C432BE for ; Tue, 3 Aug 2021 12:08:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A4D6460F35 for ; Tue, 3 Aug 2021 12:08:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236044AbhHCMIW (ORCPT ); Tue, 3 Aug 2021 08:08:22 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:52992 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S236008AbhHCMIM (ORCPT ); Tue, 3 Aug 2021 08:08:12 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 173C7ejp025603; Tue, 3 Aug 2021 14:07:42 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=subject : to : cc : references : from : message-id : date : mime-version : in-reply-to : content-type : content-transfer-encoding; s=selector1; bh=4QkwVgumgXO7AKtGcS+8ezOV3BVYGIgYxKjNSqHgcKM=; b=1rSb9uQGeP4FdleZwrpce2ZXy2h4h4iFS0Fa2YCrsvLbnEHO0MxOonf5h6hXeE/OnAM7 1MHOrAoPj+UeZ/MfZr1cANYAqCOtLI1TYheqt8eKm5FE6Vsz9/ehdoZIpes2qYE/MF+Z 8exMdI8UjHCB2Vub2BdEB9IGCbceb8K+qiqM6GMVRMjWu1wLw08omwD7mSxrh0qSJVgY pTRMTHewzaikqFZfySyaBmrnm4nvid+1sGJV3ymuhClAy0u5iK9j3QVG/OiUyfzGgQvJ 4jQEWWyIE7O4sNbpUclWwUkrMWQj4p3PmoBWJSzd1tnU5lnQaRYtkH/+TL+Z5xpMeTGB DQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 3a70js1p2s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 03 Aug 2021 14:07:42 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9D1D610002A; Tue, 3 Aug 2021 14:07:41 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 90B16220F3B; Tue, 3 Aug 2021 14:07:41 +0200 (CEST) Received: from lmecxl0573.lme.st.com (10.75.127.44) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 3 Aug 2021 14:07:41 +0200 Subject: Re: [PATCH v3 09/13] ARM: dts: sti: update clkgen-fsyn entries in stih418-clock To: Alain Volmat , Rob Herring CC: Arnd Bergmann , , , References: <20210331204228.26107-1-avolmat@me.com> <20210331204228.26107-10-avolmat@me.com> From: Patrice CHOTARD Message-ID: <309611a8-0e71-9683-c38e-afa435c8f89d@foss.st.com> Date: Tue, 3 Aug 2021 14:07:40 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210331204228.26107-10-avolmat@me.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG1NODE1.st.com (10.75.127.1) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.790 definitions=2021-08-03_02:2021-08-03,2021-08-03 signatures=0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Alain On 3/31/21 10:42 PM, Alain Volmat wrote: > The clkgen-fsyn driver now embed the clock names (assuming the > right compatible is used). Remove all clock-output-names property > and update when necessary the compatible. > > Signed-off-by: Alain Volmat > --- > arch/arm/boot/dts/stih418-clock.dtsi | 26 +++----------------------- > 1 file changed, 3 insertions(+), 23 deletions(-) > > diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi > index d628e656458d..e84c476b83ed 100644 > --- a/arch/arm/boot/dts/stih418-clock.dtsi > +++ b/arch/arm/boot/dts/stih418-clock.dtsi > @@ -94,11 +94,6 @@ > reg = <0x9103000 0x1000>; > > clocks = <&clk_sysin>; > - > - clock-output-names = "clk-s-c0-fs0-ch0", > - "clk-s-c0-fs0-ch1", > - "clk-s-c0-fs0-ch2", > - "clk-s-c0-fs0-ch3"; > }; > > clk_s_c0: clockgen-c@9103000 { > @@ -150,15 +145,10 @@ > > clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { > #clock-cells = <1>; > - compatible = "st,quadfs"; > + compatible = "st,quadfs-d0"; > reg = <0x9104000 0x1000>; > > clocks = <&clk_sysin>; > - > - clock-output-names = "clk-s-d0-fs0-ch0", > - "clk-s-d0-fs0-ch1", > - "clk-s-d0-fs0-ch2", > - "clk-s-d0-fs0-ch3"; > }; > > clockgen-d0@9104000 { > @@ -179,15 +169,10 @@ > > clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { > #clock-cells = <1>; > - compatible = "st,quadfs"; > + compatible = "st,quadfs-d2"; > reg = <0x9106000 0x1000>; > > clocks = <&clk_sysin>; > - > - clock-output-names = "clk-s-d2-fs0-ch0", > - "clk-s-d2-fs0-ch1", > - "clk-s-d2-fs0-ch2", > - "clk-s-d2-fs0-ch3"; > }; > > clockgen-d2@9106000 { > @@ -210,15 +195,10 @@ > > clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { > #clock-cells = <1>; > - compatible = "st,quadfs"; > + compatible = "st,quadfs-d3"; > reg = <0x9107000 0x1000>; > > clocks = <&clk_sysin>; > - > - clock-output-names = "clk-s-d3-fs0-ch0", > - "clk-s-d3-fs0-ch1", > - "clk-s-d3-fs0-ch2", > - "clk-s-d3-fs0-ch3"; > }; > > clockgen-d3@9107000 { > Reviewed-by: Patrice Chotard Thanks Patrice