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Mon, 29 Jul 2024 10:04:22 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46TA4Lu9020918 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 29 Jul 2024 10:04:21 GMT Received: from [10.239.132.204] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 29 Jul 2024 03:04:16 -0700 Message-ID: <309cfc01-affb-4d26-a5ff-fb73b924efcd@quicinc.com> Date: Mon, 29 Jul 2024 18:04:13 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/2] PCI: qcom: Add QCS9100 PCIe compatible To: "Aiqun Yu (Maria)" , Manivannan Sadhasivam CC: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , , , , , References: <20240709-add_qcs9100_pcie_compatible-v2-0-04f1e85c8a48@quicinc.com> <20240709175823.GB44420@thinkpad> <1fafb584-fc49-45be-a8a4-4027739eba32@quicinc.com> <20240710070908.GA3731@thinkpad> <239f408d-7bab-48c3-bf26-3880012d9098@quicinc.com> From: Tengfei Fan In-Reply-To: <239f408d-7bab-48c3-bf26-3880012d9098@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: PJ1b8dHwfVQXXyEIMt1j04LD1jinc_LO X-Proofpoint-ORIG-GUID: PJ1b8dHwfVQXXyEIMt1j04LD1jinc_LO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-29_08,2024-07-26_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1011 spamscore=0 mlxscore=0 bulkscore=0 suspectscore=0 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407290068 On 7/10/2024 6:25 PM, Aiqun Yu (Maria) wrote: > > > On 7/10/2024 3:09 PM, Manivannan Sadhasivam wrote: >> On Wed, Jul 10, 2024 at 09:47:47AM +0800, Aiqun Yu (Maria) wrote: >>> >>> >>> On 7/10/2024 1:58 AM, Manivannan Sadhasivam wrote: >>>> On Tue, Jul 09, 2024 at 10:59:28PM +0800, Tengfei Fan wrote: >>>>> Introduce support for the QCS9100 SoC device tree (DTSI) and the >>>>> QCS9100 RIDE board DTS. The QCS9100 is a variant of the SA8775p. >>>>> While the QCS9100 platform is still in the early design stage, the >>>>> QCS9100 RIDE board is identical to the SA8775p RIDE board, except it >>>>> mounts the QCS9100 SoC instead of the SA8775p SoC. >>>>> >>>>> The QCS9100 SoC DTSI is directly renamed from the SA8775p SoC DTSI, and >>>>> all the compatible strings will be updated from "SA8775p" to "QCS9100". >>>>> The QCS9100 device tree patches will be pushed after all the device tree >>>>> bindings and device driver patches are reviewed. >>>>> >>>> >>>> Are you going to remove SA8775p compatible from all drivers as well? >>> >>> SA8775p compatible and corresponding scmi solutions for the driver will >>> be taken care from auto team, currently IOT team is adding QCS9100 >>> support only. Auto team have a dependency on the current QCS9100(IOT >>> non-scmi solution) and SA8775p(AUTO SCMI solution) device tree splitting >>> effort. >>> >>> More background and information can be referenced from [1]. >>> [1] v1: >>> https://lore.kernel.org/linux-arm-msm/20240703025850.2172008-1-quic_tengfan@quicinc.com/ >> >> I'm aware of the background, but what I don't understand is, why do you want to >> keep the sa8775p compatible in both the driver and binding? Once you rename the >> DT, these compatibles become meaningless. >> >> Waiting for Auto team to remove the compatible is not ideal. They may anyway >> modify it based on SCMI design. > > Got it. Will remove sa8775p compatible in next patchset version after > discuss with Tengfei. > > PCIE driver have a very good shape of resources op api, and when SCMI > resource solution added, "sa8775p" compatible can be added at that time > with correct SCMI resource ops. After considering the feedback provided on the subject, We have decided to keep current SA8775p compatible and ABI compatibility in drivers. Let's close this session and ignore all the current patches here. Thank you for your input. >> >> - Mani >> >>>> >>>> - Mani >>>> >>>>> The final dtsi will like: >>>>> https://lore.kernel.org/linux-arm-msm/20240703025850.2172008-3-quic_tengfan@quicinc.com/ >>>>> >>>>> The detailed cover letter reference: >>>>> https://lore.kernel.org/linux-arm-msm/20240703025850.2172008-1-quic_tengfan@quicinc.com/ >>>>> >>>>> Signed-off-by: Tengfei Fan >>>>> --- >>>>> Changes in v2: >>>>> - Split huge patch series into different patch series according to >>>>> subsytems >>>>> - Update patch commit message >>>>> >>>>> prevous disscussion here: >>>>> [1] v1: https://lore.kernel.org/linux-arm-msm/20240703025850.2172008-1-quic_tengfan@quicinc.com/ >>>>> >>>>> --- >>>>> Tengfei Fan (2): >>>>> dt-bindings: PCI: Document compatible for QCS9100 >>>>> PCI: qcom: Add support for QCS9100 SoC >>>>> >>>>> Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 5 ++++- >>>>> drivers/pci/controller/dwc/pcie-qcom.c | 1 + >>>>> 2 files changed, 5 insertions(+), 1 deletion(-) >>>>> --- >>>>> base-commit: 0b58e108042b0ed28a71cd7edf5175999955b233 >>>>> change-id: 20240709-add_qcs9100_pcie_compatible-ceec013a335d >>>>> >>>>> Best regards, >>>>> -- >>>>> Tengfei Fan >>>>> >>>> >>> >>> -- >>> Thx and BRs, >>> Aiqun(Maria) Yu >> > -- Thx and BRs, Tengfei Fan