From: Alexandre TORGUE <alexandre.torgue@foss.st.com>
To: <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<linux@rempel-privat.de>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] ARM: dts: stm32: fix spi1 pin assignment on stm32mp15
Date: Tue, 28 Mar 2023 11:39:19 +0200 [thread overview]
Message-ID: <30a9f919-ff6b-57cf-de34-e145a4474643@foss.st.com> (raw)
In-Reply-To: <20230320171123.6263-1-alexandre.torgue@foss.st.com>
On 3/20/23 18:11, Alexandre Torgue wrote:
> Bank A and B IOs can't be handled by the pin controller 'Z'. This patch
> assign spi1 pin definition to the correct controller.
>
> Fixes: 9ad65d245b7b ("ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group")
>
> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
>
> diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
> index a9d2bec99014..e15a3b2a9b39 100644
> --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
> @@ -1880,6 +1880,21 @@
> };
> };
>
> + spi1_pins_b: spi1-1 {
> + pins1 {
> + pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
> + <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <1>;
> + };
> +
> + pins2 {
> + pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
> + bias-disable;
> + };
> + };
> +
> spi2_pins_a: spi2-0 {
> pins1 {
> pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
> @@ -2448,19 +2463,4 @@
> bias-disable;
> };
> };
> -
> - spi1_pins_b: spi1-1 {
> - pins1 {
> - pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
> - <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
> - bias-disable;
> - drive-push-pull;
> - slew-rate = <1>;
> - };
> -
> - pins2 {
> - pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
> - bias-disable;
> - };
> - };
> };
Applied on stm32-next.
Thanks.
Alex
prev parent reply other threads:[~2023-03-28 9:39 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-20 17:11 [PATCH] ARM: dts: stm32: fix spi1 pin assignment on stm32mp15 Alexandre Torgue
2023-03-28 9:39 ` Alexandre TORGUE [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=30a9f919-ff6b-57cf-de34-e145a4474643@foss.st.com \
--to=alexandre.torgue@foss.st.com \
--cc=devicetree@vger.kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-stm32@st-md-mailman.stormreply.com \
--cc=linux@rempel-privat.de \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).