From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: George Moussalem <george.moussalem@outlook.com>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Luo Jie <quic_luoj@quicinc.com>, Lee Jones <lee@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/6] clk: qcom: ipq5018: mark XO clock as critical
Date: Tue, 6 May 2025 02:59:56 +0200 [thread overview]
Message-ID: <31008c59-afed-405a-a330-e42d89a62790@oss.qualcomm.com> (raw)
In-Reply-To: <DS7PR19MB8883995CB86AE2784CAFF8AC9D8F2@DS7PR19MB8883.namprd19.prod.outlook.com>
On 5/4/25 8:59 AM, George Moussalem wrote:
>
>
> On 5/2/25 16:45, George Moussalem wrote:
>>
>>
>> On 5/2/25 14:29, Konrad Dybcio wrote:
>>> On 5/2/25 12:15 PM, George Moussalem via B4 Relay wrote:
>>>> From: George Moussalem <george.moussalem@outlook.com>
>>>>
>>>> The XO clock must not be disabled, so let's add the CLK_IS_CRITICAL
>>>> flag to avoid the kernel trying to disable the XO clock (when parenting
>>>> it under the CMN PLL reference clock), else the kernel will panic and
>>>> the following message will appear in the kernel logs:
>>>
>>> Remove the struct definition for this clock (and the assignment in
>>> blah_blah_clks[]) and replace it with:
>>>
>>> qcom_branch_set_clk_en(regmap, 0x30030); /* GCC_XO_CLK */
>>
>> understood, thanks for the quick turnaround!
>
> Tested it, but then then the issue is still there. This time fixable by setting the CLK_IS_CRITICAL flag on gcc_xo_clk_src. I was looking at removing the struct for gcc_xo_clk_src too and use qcom_branch_set_clk_en, but there are clocks that refer to the gcc_xo_clk_src as their parent. I'm a bit hesitant to tinker with the GCC driver without access to the datasheet. The downstream driver actually has the CLK_IS_CRITICAL flag set too on gcc_xo_clk as initially proposed in this patch:
>
> https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.5/drivers/clk/qcom/gcc-ipq5018.c#L1457
>
> Are you okay with this suggested approach?
Since turning off XO means the CPU (and nothing else on the soc for that
matter) clock will not tick, just unregister the RCG along with it
you can remove the .parent_hws (dont forget .num_parents along with it)
from the affected clocks, this is effectively cosmetic
Konrad
next prev parent reply other threads:[~2025-05-06 1:00 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-02 10:15 [PATCH 0/6] Add CMN PLL clock controller support for IPQ5018 George Moussalem via B4 Relay
2025-05-02 10:15 ` [PATCH 1/6] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC George Moussalem via B4 Relay
2025-05-02 11:35 ` Rob Herring (Arm)
2025-05-02 14:17 ` Rob Herring
2025-05-02 16:14 ` George Moussalem
2025-05-04 1:49 ` Jie Luo
2025-05-04 7:03 ` George Moussalem
2025-05-05 2:55 ` Jie Luo
2025-05-02 10:15 ` [PATCH 2/6] clk: qcom: ipq5018: mark XO clock as critical George Moussalem via B4 Relay
2025-05-02 10:29 ` Konrad Dybcio
2025-05-02 12:45 ` George Moussalem
[not found] ` <b05d9351-cc79-4e60-a6e0-de2fe698098f@outlook.com>
2025-05-04 6:59 ` George Moussalem
2025-05-06 0:59 ` Konrad Dybcio [this message]
2025-05-02 10:15 ` [PATCH 3/6] clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support George Moussalem via B4 Relay
2025-05-02 10:38 ` Konrad Dybcio
2025-05-02 13:04 ` George Moussalem
2025-05-02 10:15 ` [PATCH 4/6] dt-bindings: mfd: qcom,tcsr: Add compatible for IPQ5018 George Moussalem via B4 Relay
2025-05-09 22:05 ` Rob Herring (Arm)
2025-05-02 10:15 ` [PATCH 5/6] arm64: dts: ipq5018: Add CMN PLL node George Moussalem via B4 Relay
2025-05-04 1:53 ` Jie Luo
2025-05-04 7:10 ` George Moussalem
2025-05-02 10:15 ` [PATCH 6/6] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock George Moussalem via B4 Relay
2025-05-02 10:39 ` Konrad Dybcio
2025-05-02 14:45 ` Dmitry Baryshkov
2025-05-02 15:53 ` George Moussalem
2025-05-04 2:17 ` Jie Luo
2025-05-04 7:14 ` George Moussalem
2025-05-02 19:31 ` [PATCH 0/6] Add CMN PLL clock controller support for IPQ5018 Rob Herring (Arm)
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=31008c59-afed-405a-a330-e42d89a62790@oss.qualcomm.com \
--to=konrad.dybcio@oss.qualcomm.com \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=george.moussalem@outlook.com \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=lee@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=quic_luoj@quicinc.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox