From mboxrd@z Thu Jan 1 00:00:00 1970 From: Matthias Brugger Subject: Re: [PATCH v7 10/21] iommu/mediatek: Move reset_axi into plat_data Date: Mon, 17 Jun 2019 12:19:37 +0200 Message-ID: <314567ce-1569-8d78-08f3-3b8b7692e599@gmail.com> References: <1560169080-27134-1-git-send-email-yong.wu@mediatek.com> <1560169080-27134-11-git-send-email-yong.wu@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1560169080-27134-11-git-send-email-yong.wu@mediatek.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Yong Wu , Joerg Roedel , Robin Murphy , Rob Herring Cc: Evan Green , Tomasz Figa , Will Deacon , linux-mediatek@lists.infradead.org, srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, yingjoe.chen@mediatek.com, youlin.pei@mediatek.com, Nicolas Boichat , anan.sun@mediatek.com, Matthias Kaehlcke List-Id: devicetree@vger.kernel.org On 10/06/2019 14:17, Yong Wu wrote: > In mt8173 and mt8183, 0x48 is REG_MMU_STANDARD_AXI_MODE while it is > REG_MMU_CTRL in the other SoCs, and the bits meaning is completely > different with the REG_MMU_STANDARD_AXI_MODE. > > This patch moves this property to plat_data, it's also a preparing > patch for mt8183. > > Signed-off-by: Yong Wu > Reviewed-by: Nicolas Boichat > Reviewed-by: Evan Green Reviewed-by: Matthias Brugger > --- > drivers/iommu/mtk_iommu.c | 4 ++-- > drivers/iommu/mtk_iommu.h | 2 +- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index d38dfa2..8ac7034 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -557,8 +557,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > } > writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > > - /* It's MISC control register whose default value is ok except mt8173.*/ > - if (data->plat_data->m4u_plat == M4U_MT8173) > + if (data->plat_data->reset_axi) > writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE); > > if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, > @@ -752,6 +751,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) > .m4u_plat = M4U_MT8173, > .has_4gb_mode = true, > .has_bclk = true, > + .reset_axi = true, > .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ > }; > > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > index 61fd5d6..55d73c1 100644 > --- a/drivers/iommu/mtk_iommu.h > +++ b/drivers/iommu/mtk_iommu.h > @@ -46,7 +46,7 @@ struct mtk_iommu_plat_data { > > /* HW will use the EMI clock if there isn't the "bclk". */ > bool has_bclk; > - > + bool reset_axi; > unsigned char larbid_remap[MTK_LARB_NR_MAX]; > }; > >