From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB198C63797 for ; Tue, 17 Jan 2023 11:32:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236136AbjAQLcB (ORCPT ); Tue, 17 Jan 2023 06:32:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236863AbjAQLbm (ORCPT ); Tue, 17 Jan 2023 06:31:42 -0500 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3E5618A83 for ; Tue, 17 Jan 2023 03:31:12 -0800 (PST) Received: by mail-wm1-x329.google.com with SMTP id m5-20020a05600c4f4500b003db03b2559eso2127722wmq.5 for ; Tue, 17 Jan 2023 03:31:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=D3EkrOrIsoGEjlXNQEPTeW63ljQubkNcPYNJb7gZfuY=; b=QhBqq2ukGol8Dny+uxp1UtX3xOQ996K9vcPiDP5m3o5/CaC696MrNiK1LegSjSkp+n eYNR0oKhzdmtvHN21+skBAsHgJ9LmiHUG4xtsMBsuKcSHAM1taKiPK+O8in4qkYbnXQ0 jstWKCtRvJ4/8t2Z0LkfWY+yvqYahCXfCA1ZdaUAWnQO0GASOeBKkOdi6XXAxVB2HgZG //MZfaHKboeCfCP+V1YvO1mYNJPc39sNyv25GAWIbsuxj/3/R8JKvn38xKtbbzV4wj4d V16ijyQbZDpaKcFaPitLH3Ucoms/ssVKe9XzhJjsagdPW9tK5YsJ604wVDf88Nkorwwq uFPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=D3EkrOrIsoGEjlXNQEPTeW63ljQubkNcPYNJb7gZfuY=; b=BUHvY1eRyrHrEA49ZcMgFFs/hH9nzxXCzbb2h1CALcUJApROHHYgwz+HX0Q4IsHOuw zgGWTW+tRqZ9zcfctGgxD8JbgBQev5fY2/7m6zu3DJpS+TcgdCOwi/OhApolvhJePwH+ cwCbsBjO9aX/28JM+z5kguMnx513g+4Gbx3DTA/ACu2h1NTs8exk9/qxIFoWhEek9lus R0PG4IlkK9OBBrms57wHHeBQP1bkk0GC3PdwaZbRBBdUphaJX0uNiKNGnKt21kW1uFGI 2W5IQvsi/4K7HTfktYadc9TagfOgXOi0kTxSNpDAIJvEpIPO4ZNJkI16wgzKq/YdEvXC Sk6g== X-Gm-Message-State: AFqh2kognsrI4SL3G5inlM9xnB3ADKnRGPIKQZBFbm8gQG+DK/KWc1k7 S52PWeof142GoHOMIpdUF5IYzA2A5yadAn3s X-Google-Smtp-Source: AMrXdXsAZl1MLOjQo2d3qzzRlNy+HJn/RhgvDPfSZDlkj/nJewQUkMhVEVuNshej/DJMn5pYVRGtGg== X-Received: by 2002:a05:600c:3088:b0:3da:1bb0:4d8a with SMTP id g8-20020a05600c308800b003da1bb04d8amr2902593wmn.16.1673955071493; Tue, 17 Jan 2023 03:31:11 -0800 (PST) Received: from [192.168.1.109] ([178.197.216.144]) by smtp.gmail.com with ESMTPSA id k7-20020adfd227000000b002bdf3809f59sm8052618wrh.38.2023.01.17.03.31.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Jan 2023 03:31:10 -0800 (PST) Message-ID: <316ddb81-8d13-71dd-3396-412e31cfb880@linaro.org> Date: Tue, 17 Jan 2023 12:31:09 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v3 05/10] dt-bindings: soc: fsl: cpm_qe: Add QMC controller Content-Language: en-US To: Herve Codina , Li Yang , Rob Herring , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Christophe Leroy , Michael Ellerman , Nicholas Piggin , Qiang Zhao , Jaroslav Kysela , Takashi Iwai , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen Cc: linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni References: <20230113103759.327698-1-herve.codina@bootlin.com> <20230113103759.327698-6-herve.codina@bootlin.com> From: Krzysztof Kozlowski In-Reply-To: <20230113103759.327698-6-herve.codina@bootlin.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 13/01/2023 11:37, Herve Codina wrote: > Add support for the QMC (QUICC Multichannel Controller) > available in some PowerQUICC SoC such as MPC885 or MPC866. > > Signed-off-by: Herve Codina > --- > .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++ > 1 file changed, 164 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > new file mode 100644 > index 000000000000..3ec52f1635c8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > @@ -0,0 +1,164 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) > + > +maintainers: > + - Herve Codina > + > +description: | > + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within > + one serial controller using the same TDM physical interface routed from > + TSA. > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,mpc885-scc-qmc > + - fsl,mpc866-scc-qmc > + - const: fsl,cpm1-scc-qmc > + > + reg: > + items: > + - description: SCC (Serial communication controller) register base > + - description: SCC parameter ram base > + - description: Dual port ram base > + > + reg-names: > + items: > + - const: scc_regs > + - const: scc_pram > + - const: dpram > + > + interrupts: > + maxItems: 1 > + description: SCC interrupt line in the CPM interrupt controller > + > + fsl,tsa: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: phandle to the TSA > + > + fsl,tsa-cell-id: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [1, 2, 3] > + description: | > + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 Is this used as argument to tsa? If so, this should be part of fsl,tsa property, just like we do for all syscon-like phandles. > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + '#chan-cells': > + const: 1 > + > +patternProperties: > + '^channel@([0-9]|[1-5][0-9]|6[0-3])$': > + description: > + A channel managed by this controller > + type: object > + > + properties: > + reg: > + minimum: 0 > + maximum: 63 > + description: > + The channel number > + > + fsl,mode: > + $ref: /schemas/types.yaml#/definitions/string > + enum: [transparent, hdlc] > + default: transparent > + description: Operational mode You still need to explain what do transparent and hdlc mean. > + Best regards, Krzysztof