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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id b10-20020a2e988a000000b002ac7a25c001sm306894ljj.24.2023.06.09.01.53.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Jun 2023 01:53:47 -0700 (PDT) Message-ID: <316fd262-eeec-a2a4-cbc1-2c39935be87c@linaro.org> Date: Fri, 9 Jun 2023 10:53:45 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH 1/3] dt-bindings: arm-smmu: Add interconnect for qcom SMMUs Content-Language: en-US To: Parikshit Pareek , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Manivannan Sadhasivam , Dmitry Baryshkov , Marijn Suijten , Adam Skladowski , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, "linux-kernel @ vger . kernel . org Prasanna Kumar" , Shazad Hussain References: <20230609054141.18938-1-quic_ppareek@quicinc.com> <20230609054141.18938-2-quic_ppareek@quicinc.com> From: Konrad Dybcio In-Reply-To: <20230609054141.18938-2-quic_ppareek@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 9.06.2023 07:41, Parikshit Pareek wrote: > There are certain SMMUs on qcom SoCs, which need to set interconnect- > bandwidth, before accessing any MIMO mapped HW registers, and accessing > RAM during page table walk. Hence introduce the due bindings for > interconnects. > > Reported-by: Eric Chanudet > Signed-off-by: Parikshit Pareek > --- > .../devicetree/bindings/iommu/arm,smmu.yaml | 22 +++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index ba677d401e24..75e00789d8c2 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -327,6 +327,28 @@ allOf: > - description: interface clock required to access smmu's registers > through the TCU's programming interface. > > + - if: > + properties: > + compatible: > + contains: > + enum: > + qcom,sa8775p-smmu-500 > + then: > + properties: > + interconnects: This isn't specific to SA8775P.. I believe we could make it SMMU-generic.. > + minItems: 1 > + maxItems: 1 > + > + interconnect-names: > + minItems: 1 > + items: > + - const: tbu_mc > + > + icc_bw: No underscores in property names. > + $ref: /schemas/types.yaml#/definitions/int32 Can't we use OPP tables? They'd also allow for specifying required-opps. Konrad > + description: > + An integer expressing the interconnect bandwidth(MBps) to be set. > + > - if: > properties: > compatible: