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Wed, 29 Apr 2026 05:36:17 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: ApIjjO01HLYR Date: Wed, 29 Apr 2026 10:35:34 +0100 From: "Jiaxun Yang" To: "Icenowy Zheng" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Thomas Bogendoerfer" Cc: devicetree@vger.kernel.org, "linux-mips@vger.kernel.org" , linux-kernel@vger.kernel.org Message-Id: <3194da09-3bfc-4482-b179-04b6d5df4a00@app.fastmail.com> In-Reply-To: <20260411101744.4020216-1-zhengxingda@iscas.ac.cn> References: <20260411101744.4020216-1-zhengxingda@iscas.ac.cn> Subject: Re: [PATCH 0/2] Enable LPC interrupt controller on MIPS LS7A systems Content-Type: text/plain Content-Transfer-Encoding: 7bit On Sat, 11 Apr 2026, at 11:17 AM, Icenowy Zheng wrote: > This patchset tries to enable support for LPC interrupts on MIPS-based > Loongson systems with Loongson 7A1000 PCH chip. > > The corresponding irqchip support (along with the DT binding) is already > added to the tip tree. > > Tested on a Haier Boyue G51 system with legacy i8042 keyboard/mouse as > integrated ones. > > This patchset is splitted from the original patchset that contains both > driver part and DT part. For the series: Acked-by: Jiaxun Yang > > Icenowy Zheng (2): > MIPS: Loongson64: dts: Sort nodes > MIPS: Loongson64: dts: Add node for LS7A PCH LPC > > arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 17 +++++++++++++---- > 1 file changed, 13 insertions(+), 4 deletions(-) > > -- > 2.52.0 -- - Jiaxun