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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id bw3-20020a170906c1c300b006e88cdfbc32sm1547048ejb.45.2022.04.23.02.56.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 23 Apr 2022 02:56:43 -0700 (PDT) Message-ID: <31cb9af1-173d-bef5-64da-ccf5a01f2485@linaro.org> Date: Sat, 23 Apr 2022 11:56:42 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 4/7] dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller Content-Language: en-US To: =?UTF-8?Q?Jonathan_Neusch=c3=a4fer?= , linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck References: <20220422183012.444674-1-j.neuschaefer@gmx.net> <20220422183012.444674-5-j.neuschaefer@gmx.net> From: Krzysztof Kozlowski In-Reply-To: <20220422183012.444674-5-j.neuschaefer@gmx.net> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 22/04/2022 20:30, Jonathan Neuschäfer wrote: > The Nuvoton WPCM450 SoC has a combined clock and reset controller. > Add a devicetree binding for it, as well as definitions for the bit > numbers used by it. > > Signed-off-by: Jonathan Neuschäfer > --- Thank you for your patch. There is something to discuss/improve. > .../bindings/clock/nuvoton,wpcm450-clk.yaml | 74 +++++++++++++++++++ > .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++++++++++++++++ > 2 files changed, 141 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml > create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h > > diff --git a/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml > new file mode 100644 > index 0000000000000..0fffa8a68dee4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml > @@ -0,0 +1,74 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/nuvoton,wpcm450-clk.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Nuvoton WPCM450 clock controller binding s/binding// > + > +maintainers: > + - Jonathan Neuschäfer > + > +description: > + This binding describes the clock controller of the Nuvoton WPCM450 SoC, which > + supplies clocks and resets to the rest of the chip. s/This binding describes// Just describe the hardware. > + > +properties: > + compatible: > + const: nuvoton,wpcm450-clk > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: Reference clock oscillator (should be 48 MHz) > + > + clock-names: > + items: > + - const: refclk > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - '#clock-cells' > + > +examples: > + - | > + #include > + #include > + > + refclk: clock-48mhz { > + /* 48 MHz reference oscillator */ > + compatible = "fixed-clock"; > + clock-output-names = "refclk"; > + clock-frequency = <48000000>; > + #clock-cells = <0>; > + }; > + > + clk: clock-controller@b0000200 { > + reg = <0xb0000200 0x100>; > + compatible = "nuvoton,wpcm450-clk"; > + clocks = <&refclk>; > + clock-names = "refclk"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + serial@b8000000 { > + compatible = "nuvoton,wpcm450-uart"; > + reg = <0xb8000000 0x20>; > + reg-shift = <2>; > + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk WPCM450_CLK_UART0>; > + }; Skip the consumer example, it's obvious/trivial/duplicating. > diff --git a/include/dt-bindings/clock/nuvoton,wpcm450-clk.h b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h > new file mode 100644 > index 0000000000000..86e1c895921b7 > --- /dev/null > +++ b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h > @@ -0,0 +1,67 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H > +#define _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H > + > +/* Clocks based on CLKEN bits */ > +#define WPCM450_CLK_FIU 0 > +#define WPCM450_CLK_XBUS 1 > +#define WPCM450_CLK_KCS 2 > +#define WPCM450_CLK_SHM 4 > +#define WPCM450_CLK_USB1 5 > +#define WPCM450_CLK_EMC0 6 > +#define WPCM450_CLK_EMC1 7 > +#define WPCM450_CLK_USB0 8 > +#define WPCM450_CLK_PECI 9 > +#define WPCM450_CLK_AES 10 > +#define WPCM450_CLK_UART0 11 > +#define WPCM450_CLK_UART1 12 > +#define WPCM450_CLK_SMB2 13 > +#define WPCM450_CLK_SMB3 14 > +#define WPCM450_CLK_SMB4 15 > +#define WPCM450_CLK_SMB5 16 > +#define WPCM450_CLK_HUART 17 > +#define WPCM450_CLK_PWM 18 > +#define WPCM450_CLK_TIMER0 19 > +#define WPCM450_CLK_TIMER1 20 > +#define WPCM450_CLK_TIMER2 21 > +#define WPCM450_CLK_TIMER3 22 > +#define WPCM450_CLK_TIMER4 23 > +#define WPCM450_CLK_MFT0 24 > +#define WPCM450_CLK_MFT1 25 > +#define WPCM450_CLK_WDT 26 > +#define WPCM450_CLK_ADC 27 > +#define WPCM450_CLK_SDIO 28 > +#define WPCM450_CLK_SSPI 29 > +#define WPCM450_CLK_SMB0 30 > +#define WPCM450_CLK_SMB1 31 > + > +/* Other clocks */ > +#define WPCM450_CLK_USBPHY 32 > + > +#define WPCM450_NUM_CLKS 33 > + > +/* Resets based on IPSRST bits */ All these defines should be in second header in dt-bindings/reset/... > +#define WPCM450_RESET_FIU 0 Best regards, Krzysztof