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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA0MDA0MyBTYWx0ZWRfX7s42FFqy2qWI WyDbvG628smFK/JpA44dpUxuJ3a/8ymQHwVoCOxjtZGJoETdHoPr8lffLki6yBIZGTK12m3urF7 dxAYpLYMad8NPBOmxmtTeSLpwIxIFuY+6YekPSirmGhsop3l8DeODBgeuznJRVz6vi7sLW2czbU iJlWMKo6ii1Mo9LF6ckSMpe9lOUrxud0aJb0SJxJvs62AHrNlR864dV4Xv9sXE1KVKKb+VF3NpM 22c+RJrRErXAZos/2QNEvTl/AlvZIE+Jk+6We+Vh/HI/rhob+x+5CrTJhnkCZaPS9clfE441Enh bYU8QCZ7NT0z6jHlecu0wiH2ydcLvYIRCtYyjqdaqo5N3KsrtoWwCvWK4yQYYKtKVmqMA0dtB7a 6d+obhxADflEj0BT14QaQZkNdjF0jtHB7cxSe/EgahHoBCABoZT1kgNzcOXIc98WyOXLL88ppE5 6cOPfdyye21K+jrITDQ== X-Authority-Analysis: v=2.4 cv=TIt1jVla c=1 sm=1 tr=0 ts=6a717d22 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=Q/e3f29T3Hw2hnAEzBPF7w==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=G2glL8InyLvFS_YR_T0A:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-ORIG-GUID: _rkvBtRgfQGcn7AHEZ_EprxTkN2Cj1eM X-Proofpoint-Spam-Info: AW1haW4tMjYwODA0MDA0MyBTYWx0ZWRfXyDs/wrOIP4wJ tNxGnybJHpmpphA/tK2nr6/cSU/cbRfPstE1sdAvizd9JFWnV52kcHb+tW+tcG+T3RldVnBv2eI cc6+AagU6bLX5lU8yeaUrNYguXfSrkw= X-Proofpoint-GUID: _rkvBtRgfQGcn7AHEZ_EprxTkN2Cj1eM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-04_01,2026-08-03_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 phishscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 spamscore=0 suspectscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608040043 Hi Dmitry, On 8/3/2026 9:44 PM, Dmitry Baryshkov wrote: > On Thu, Jul 30, 2026 at 09:02:26PM +0300, Atanas Filipov wrote: >> On 7/30/2026 7:01 PM, Dmitry Baryshkov wrote: >>> On Thu, Jul 30, 2026 at 06:05:24PM +0300, Atanas Filipov wrote: >>>> Add the JPEG encoder hardware node to the SM8250 device tree so the >>>> qcom-jpeg V4L2 encoder driver can bind and operate on this platform. >>>> >>>> Signed-off-by: Atanas Filipov >>>> --- >>>> arch/arm64/boot/dts/qcom/sm8250.dtsi | 72 ++++++++++++++++++++++++++++ >>>> 1 file changed, 72 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi >>>> index f11da2ca4181..d42b29419320 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi >>>> @@ -13,6 +13,7 @@ >>>> #include >>>> #include >>>> #include >>>> +#include >>>> #include >>>> #include >>>> #include >>>> @@ -4486,6 +4487,77 @@ cci1_i2c1: i2c-bus@1 { >>>> }; >>>> }; >>>> + jpeg-encoder@ac53000 { >>>> + compatible = "qcom,sm8250-jpeg-enc"; >>>> + status = "disabled"; >>>> + >>>> + reg = <0x0 0x0ac53000 0x0 0x1000>; >>>> + >>>> + interrupts = ; >>>> + >>>> + power-domains = <&camcc TITAN_TOP_GDSC>, >>>> + <&rpmhpd RPMHPD_MMCX>, >>> >>> Is TITAN_TOP a part of the MMCX or CX domain? In the former case, >>> please drop separate mmcx vote here and let it come through the >>> titan_top (it might require camcc driver and node modifications). >>> >> >> The change was requested by Brian, most likely in connection with upcoming >> migrations. I think he would be able to explain the exact reasons. As far as >> the facts are concerned, this is not currently necessary for the driver to >> be functional. > > There is no word _driver_ in the _dt bindings_. What is the actual > hardware wrapping? What is being powered by which domain? Is MMCX > directly powering something? Or is it gated by TITAN_TOP_GDSC? I assume > that MX is powering on PLLs, correct? Yes i agree there is no word driver in the dt_bindings but you get my point, with only TITAN_TOP_GDSC hw is fully functional there is no need of additional MMCX power domain. > >>>> + >>>> + opp-100000000 { >>>> + opp-hz = /bits/ 64 <400000000>, >>>> + /bits/ 64 <100000000>; >>>> + required-opps = <&rpmhpd_opp_min_svs>; >>> >>> This looks a bit strange. Are you sure that PLL levels match the MMCX / >>> internal clock levels? I think you need to vote on both domains. > > This is not addressed / responded. Yes this need to be checked. I will get back when we get info for this... Regards, ~Gjorgji