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[88.112.131.206]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30ba4ac5f05sm10058081fa.22.2025.03.04.00.37.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Mar 2025 00:37:50 -0800 (PST) Message-ID: <3210a484-b9c3-4399-bee1-9f5bbc90034c@linaro.org> Date: Tue, 4 Mar 2025 10:37:48 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc Content-Language: ru-RU To: Dmitry Baryshkov Cc: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Michael Turquette , Stephen Boyd , Conor Dooley , Taniya Das , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org References: <20250303225521.1780611-1-vladimir.zapolskiy@linaro.org> <20250303225521.1780611-3-vladimir.zapolskiy@linaro.org> From: Vladimir Zapolskiy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 3/4/25 01:53, Dmitry Baryshkov wrote: > On Tue, Mar 04, 2025 at 12:55:21AM +0200, Vladimir Zapolskiy wrote: >> SM8550 Camera Clock Controller shall enable both MXC and MMCX power >> domains. > > Are those really required to access the registers of the cammcc? Or is > one of those (MXC?) required to setup PLLs? Also, is this applicable > only to sm8550 or to other similar clock controllers? Due to the described problem I experience a fatal CPU stall on SM8550-QRD, not on any SM8450 or SM8650 powered board for instance, however it does not exclude an option that the problem has to be fixed for other clock controllers, but it's Qualcomm to confirm any other touched platforms, for instance x1e80100-camcc has it resolved right at the beginning. To my understanding here 'required-opps' shall also be generalized, so the done copy from x1e80100-camcc was improper, and the latter dt-binding should be fixed. -- Best wishes, Vladimir