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Wed, 30 Sep 2026 04:56:19 -0700 (PDT) X-Received: by 2002:a05:620a:19a3:b0:93c:80d8:5802 with SMTP id af79cd13be357-93ca96ff8d2mr167961785a.4.1790769378891; Wed, 30 Sep 2026 04:56:18 -0700 (PDT) Received: from [192.168.202.12] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6ae158989f1sm675333a12.34.2026.09.30.04.56.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Sep 2026 04:56:18 -0700 (PDT) Message-ID: <3217e1a7-f463-4e7b-b213-91e59100dad7@oss.qualcomm.com> Date: Wed, 30 Sep 2026 13:56:15 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/4] clk: qcom: Add lpass clock controller driver for Glymur To: Srinivas Kandagatla , Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Abel Vesa , Abel Vesa , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260925084635.112399-1-srinivas.kandagatla@oss.qualcomm.com> <20260925084635.112399-5-srinivas.kandagatla@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260925084635.112399-5-srinivas.kandagatla@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTMwMDA0NyBTYWx0ZWRfX3SaPNsyWaG1T jHP2xN0HigbW+XKd1nellQeBH/QwBR1VD6D+MLKFSVyb7o1fBdjOm/fC7wNWdCZKhFwRA79za+B +dME8It+rO8LWAPJ2sAehtMK/5JuRR0= X-Proofpoint-GUID: O_mG7gblmTaOhFbXYCvqQn3YQYxZWgoa X-Authority-Analysis: v=2.4 cv=W9GtxhWk c=1 sm=1 tr=0 ts=6abcf8e4 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=H9QmddT51QaNM9ltfMQA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTMwMDA0NyBTYWx0ZWRfXwUw7T+ImAiaW ZS4R6SCgpxGX7KRq6XLfsR8HnA9aQLM4jZTqN3h23ugIm16Aq6KNGNJ2ePBWtyoXHo8Glu3ncqW uhjxYkkrbgVd+TD8xknPPYGCpEBy9pzKJFRLnUTYivwgOZ1LCyIIezX7SYLua++F0e/JmY9joE2 HUFTSVOfoXi+eXZQR48KMAv08+FuygN9O0IesB7tXtUgLziNUMdRu7ECYclQ3qZScyYWW2rcrZX o4pOShDYks6/3UMIyf5HqMxj6FsTn99QtpoUwM4MOhDC2kmvcSFidgTNieprKmV0bSAcByS9Wjd 0cyw9jdk2AAAzgZ9RxCqJbLjHCOHD7u1ojqvAvdFKaqMatDL/ttHbnK13VJnyDt8CAk2vE3nM7C GicwUubzEhotOSgdlv4QeIVm2A6zU0yOFSNDEcgZwITTL7f7BMfaqx58lUQsFkcg5T2YD8Atm4G zzUNSGIIKP20pfBBCZQ== X-Proofpoint-ORIG-GUID: O_mG7gblmTaOhFbXYCvqQn3YQYxZWgoa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-30_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609300047 On 9/25/26 10:46 AM, Srinivas Kandagatla wrote: > Add support for the lpass clock controller found on Glymur based devices. > This would allow lpass peripheral loader drivers to control the clocks and > bring the subsystems out of reset. > > Currently this patch only supports resets as the Q6DSP is in control of > LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg > channel. > > Signed-off-by: Srinivas Kandagatla > Reviewed-by: Abel Vesa > --- > drivers/clk/qcom/lpasscc-glymur.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/drivers/clk/qcom/lpasscc-glymur.c b/drivers/clk/qcom/lpasscc-glymur.c > index 356625dce99e..eda13686850c 100644 > --- a/drivers/clk/qcom/lpasscc-glymur.c > +++ b/drivers/clk/qcom/lpasscc-glymur.c > @@ -37,10 +37,31 @@ static const struct qcom_cc_desc lpass_audiocc_glymur_reset_desc = { > .num_resets = ARRAY_SIZE(lpass_audiocc_glymur_resets), > }; > > +static const struct qcom_reset_map lpasscc_glymur_resets[] = { > + [LPASS_AUDIO_SWR_TX_CGCR] = { 0xa028, 1 }, GPT says this register doesn't exist Konrad