From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 691132EB08; Tue, 7 May 2024 06:37:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715063859; cv=none; b=CP/xAHG1aG4sKypD423ECaZt82L0o+pWtMsodPjZRLZUZyIl2t+9iHOjpAnMvbsZFboZrg98HcG88JNLJQBErpSCN4xRi19E85uetwKEl+ZHt9bYFxCotvjPlKOAPFc2XreeX4u+Y7wkLv0g41xMp8YRmypf39nSDknABTXMUi4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715063859; c=relaxed/simple; bh=So5cWA9X/plmkFRBimltC9aU3la3EuxEVdH1kzJTYmE=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=rZSwyF+zS3R19osSsY0dQVeD2dVrXJR71l64ICAExBpOFhy0uwtP2942k/51gEMhKf7vgK1rkF44fg1bR0uyYEllWTXCSexRTQ3pez43p7KvgAcASZqw0/1ZcIot/vu6VPr+ADGnZwJVX9My0Ol/QgwRSZCNjjd2oOZu9t434VM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DdTY2SBZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DdTY2SBZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C91D5C4AF63; Tue, 7 May 2024 06:37:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715063858; bh=So5cWA9X/plmkFRBimltC9aU3la3EuxEVdH1kzJTYmE=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=DdTY2SBZ5TwZQSl3KEq39YQvqzELf14NOBJg+qVN3UILiefALRvquwFcp1oePXPVI XRZN8WUR3lUl87s0KT/rfwVzAxq9iSQJu67hfYTmjMprz3n+DZakLzXMsIEhEUuqD5 bWcexrvgfMLz0HWvep7i93EUsLDHKt0Z3W3bzy3mGKH2pM+1fRMXR8TbFMzL4mAxno 6B0lNUnQr70OisPBstXNqklz+3oCI9J/7WzYrbWpdzP4d6WoSw8E1nB9y3BX4p4NtL 2hvjunY3VFlp7VzwPGBu4vZRJbimIkM8/tHWeE5jqOEsvzgAoS4nUs6CPY9NU7XE4M ecaWtAvsGgWYQ== Message-ID: <321b9a79-e4d1-4cdc-80ba-c226a6b2cdb4@kernel.org> Date: Tue, 7 May 2024 08:37:30 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 09/11] sdhci: dt-bindings: configuration settings To: Krishna Yarlagadda , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-i2c@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: thierry.reding@gmail.com, jonathanh@nvidia.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, corbet@lwn.net, andi.shyti@kernel.org, wsa+renesas@sang-engineering.com, ulf.hansson@linaro.org, adrian.hunter@intel.com, digetx@gmail.com, ldewangan@nvidia.com, mkumard@nvidia.com References: <20240506225139.57647-1-kyarlagadda@nvidia.com> <20240506225139.57647-10-kyarlagadda@nvidia.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 07/05/2024 00:51, Krishna Yarlagadda wrote: > SDHCI vendor tuning registers are configured using config setting > framework. Document available config for Tegra SDHCI controllers. > > Signed-off-by: Krishna Yarlagadda > --- > .../bindings/mmc/nvidia,tegra20-sdhci.yaml | 36 +++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml > index 72987f0326a1..002bc1ffc156 100644 > --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml > +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml > @@ -177,6 +177,37 @@ properties: > operates at a 1.8 V fixed I/O voltage. > $ref: /schemas/types.yaml#/definitions/flag > > + config: No. This node does not re > + description: Config settings for SDHCI devices. > + Config setting is the configuration based on chip/board/system > + characterization on interface/controller settings. This is needed for > + - making the controller internal configuration to better perform > + - making the interface to work proper by setting drive strength, slew > + rates etc > + - making the low power leakage. > + SDHCI has configuration based on device speed modes. > + - common is set on all speeds and can be overridden by speed mode. > + - List of speed modes and their config name > + "default", /* MMC_TIMING_LEGACY */ > + "sd-mmc-highspeed", /* MMC_TIMING_MMC_HS */ > + "sd-mmc-highspeed", /* MMC_TIMING_SD_HS */ > + "uhs-sdr12", /* MMC_TIMING_UHS_SDR12 */ > + "uhs-sdr25", /* MMC_TIMING_UHS_SDR25 */ > + "uhs-sdr50", /* MMC_TIMING_UHS_SDR50 */ > + "uhs-sdr104", /* MMC_TIMING_UHS_SDR104 */ > + "uhs-ddr52", /* MMC_TIMING_UHS_DDR50 */ > + "uhs-ddr52", /* MMC_TIMING_MMC_DDR52 */ > + "mmc-hs200", /* MMC_TIMING_MMC_HS200 */ > + "mmc-hs400", /* MMC_TIMING_MMC_HS400 */ > + type: object > + unevaluatedProperties: true NAK. > + properties: > + nvidia,num-tuning-iter: > + description: Specify DQS trim value for HS400 timing. > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 0 > + maximum: 0xffff "iterations" is decimal value. How it can be 0? 0 tries to time? Best regards, Krzysztof