* [PATCH v2 1/4] arm64: dts: renesas: r8a77995: add FCPV nodes
[not found] ` <1518550237-16753-1-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
@ 2018-02-13 19:30 ` Kieran Bingham
2018-02-13 22:02 ` Laurent Pinchart
0 siblings, 1 reply; 9+ messages in thread
From: Kieran Bingham @ 2018-02-13 19:30 UTC (permalink / raw)
To: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Simon Horman,
Laurent Pinchart, Kieran Bingham
Cc: Kieran Bingham, Magnus Damm, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM64 PORT AARCH64 ARCHITECTURE, open list
From: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
The FCPVB handles the interface between the VSPB and memory, while the
FCPVD handles the interface between the VSPD and memory.
Signed-off-by: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index cd3c6a30fc47..196a917afea6 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -691,6 +691,33 @@
#phy-cells = <0>;
status = "disabled";
};
+
+ fcpvb0: fcp@fe96f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe96f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 607>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 607>;
+ iommus = <&ipmmu_vp0 5>;
+ };
+
+ fcpvd0: fcp@fea27000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea27000 0 0x200>;
+ clocks = <&cpg CPG_MOD 603>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 603>;
+ iommus = <&ipmmu_vi0 8>;
+ };
+
+ fcpvd1: fcp@fea2f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea2f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 602>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 602>;
+ iommus = <&ipmmu_vi0 9>;
+ };
};
timer {
--
2.7.4
--
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^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 1/4] arm64: dts: renesas: r8a77995: add FCPV nodes
2018-02-13 19:30 ` [PATCH v2 1/4] arm64: dts: renesas: r8a77995: add FCPV nodes Kieran Bingham
@ 2018-02-13 22:02 ` Laurent Pinchart
0 siblings, 0 replies; 9+ messages in thread
From: Laurent Pinchart @ 2018-02-13 22:02 UTC (permalink / raw)
To: Kieran Bingham
Cc: linux-renesas-soc, Simon Horman, Kieran Bingham, Kieran Bingham,
Magnus Damm, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM64 PORT (AARCH64 ARCHITECTURE), open list
Hi Kieran,
Thank you for the patch.
On Tuesday, 13 February 2018 21:30:34 EET Kieran Bingham wrote:
> From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
>
> The FCPVB handles the interface between the VSPB and memory, while the
> FCPVD handles the interface between the VSPD and memory.
>
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>
> arch/arm64/boot/dts/renesas/r8a77995.dtsi | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index
> cd3c6a30fc47..196a917afea6 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> @@ -691,6 +691,33 @@
> #phy-cells = <0>;
> status = "disabled";
> };
> +
> + fcpvb0: fcp@fe96f000 {
> + compatible = "renesas,fcpv";
> + reg = <0 0xfe96f000 0 0x200>;
> + clocks = <&cpg CPG_MOD 607>;
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 607>;
> + iommus = <&ipmmu_vp0 5>;
> + };
> +
> + fcpvd0: fcp@fea27000 {
> + compatible = "renesas,fcpv";
> + reg = <0 0xfea27000 0 0x200>;
> + clocks = <&cpg CPG_MOD 603>;
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 603>;
> + iommus = <&ipmmu_vi0 8>;
> + };
> +
> + fcpvd1: fcp@fea2f000 {
> + compatible = "renesas,fcpv";
> + reg = <0 0xfea2f000 0 0x200>;
> + clocks = <&cpg CPG_MOD 602>;
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 602>;
> + iommus = <&ipmmu_vi0 9>;
> + };
> };
>
> timer {
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/4] arm64: dts: renesas: r8a77995: add VSP instances
[not found] <1518550237-16753-1-git-send-email-kbingham@kernel.org>
[not found] ` <1518550237-16753-1-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
@ 2018-02-13 19:30 ` Kieran Bingham
2018-02-13 22:03 ` Laurent Pinchart
2018-02-13 19:30 ` [PATCH v2 3/4] arm64: dts: renesas: r8a7795: Fix register mappings on VSPs Kieran Bingham
2018-02-13 19:30 ` [PATCH v2 4/4] arm64: dts: renesas: r8a7796: " Kieran Bingham
3 siblings, 1 reply; 9+ messages in thread
From: Kieran Bingham @ 2018-02-13 19:30 UTC (permalink / raw)
To: linux-renesas-soc, Simon Horman, Laurent Pinchart, Kieran Bingham
Cc: Kieran Bingham, Magnus Damm, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM64 PORT AARCH64 ARCHITECTURE, open list
From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
The r8a77995 has a VSPBS to support image processing such as blending of
two input images, and has two VSPDs to handle display pipelines with a
DU.
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
---
v2:
- Fix VSPD register map size
- Squash VSPBS and VSPD patches together
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 196a917afea6..19bd8be9926a 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -692,6 +692,16 @@
status = "disabled";
};
+ vspbs: vsp@fe960000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfe960000 0 0x4000>;
+ interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 627>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 627>;
+ renesas,fcp = <&fcpvb0>;
+ };
+
fcpvb0: fcp@fe96f000 {
compatible = "renesas,fcpv";
reg = <0 0xfe96f000 0 0x200>;
@@ -701,6 +711,16 @@
iommus = <&ipmmu_vp0 5>;
};
+ vspd0: vsp@fea20000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea20000 0 0x8000>;
+ interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 623>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 623>;
+ renesas,fcp = <&fcpvd0>;
+ };
+
fcpvd0: fcp@fea27000 {
compatible = "renesas,fcpv";
reg = <0 0xfea27000 0 0x200>;
@@ -710,6 +730,16 @@
iommus = <&ipmmu_vi0 8>;
};
+ vspd1: vsp@fea80000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea28000 0 0x8000>;
+ interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 622>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 622>;
+ renesas,fcp = <&fcpvd1>;
+ };
+
fcpvd1: fcp@fea2f000 {
compatible = "renesas,fcpv";
reg = <0 0xfea2f000 0 0x200>;
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 2/4] arm64: dts: renesas: r8a77995: add VSP instances
2018-02-13 19:30 ` [PATCH v2 2/4] arm64: dts: renesas: r8a77995: add VSP instances Kieran Bingham
@ 2018-02-13 22:03 ` Laurent Pinchart
2018-02-14 8:39 ` Kieran Bingham
0 siblings, 1 reply; 9+ messages in thread
From: Laurent Pinchart @ 2018-02-13 22:03 UTC (permalink / raw)
To: Kieran Bingham
Cc: linux-renesas-soc, Simon Horman, Kieran Bingham, Kieran Bingham,
Magnus Damm, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM64 PORT (AARCH64 ARCHITECTURE), open list
Hi Kieran,
Thank you for the patch.
On Tuesday, 13 February 2018 21:30:35 EET Kieran Bingham wrote:
> From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
>
> The r8a77995 has a VSPBS to support image processing such as blending of
> two input images, and has two VSPDs to handle display pipelines with a
> DU.
>
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
>
> ---
> v2:
> - Fix VSPD register map size
> - Squash VSPBS and VSPD patches together
>
> arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 ++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index
> 196a917afea6..19bd8be9926a 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> @@ -692,6 +692,16 @@
> status = "disabled";
> };
>
> + vspbs: vsp@fe960000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xfe960000 0 0x4000>;
The VSPBS also has OSD-CLUT support in its RPFs, so you need to extend the
registers range too.
Apart from that,
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 627>;
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 627>;
> + renesas,fcp = <&fcpvb0>;
> + };
> +
> fcpvb0: fcp@fe96f000 {
> compatible = "renesas,fcpv";
> reg = <0 0xfe96f000 0 0x200>;
> @@ -701,6 +711,16 @@
> iommus = <&ipmmu_vp0 5>;
> };
>
> + vspd0: vsp@fea20000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xfea20000 0 0x8000>;
> + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 623>;
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 623>;
> + renesas,fcp = <&fcpvd0>;
> + };
> +
> fcpvd0: fcp@fea27000 {
> compatible = "renesas,fcpv";
> reg = <0 0xfea27000 0 0x200>;
> @@ -710,6 +730,16 @@
> iommus = <&ipmmu_vi0 8>;
> };
>
> + vspd1: vsp@fea80000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xfea28000 0 0x8000>;
> + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 622>;
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 622>;
> + renesas,fcp = <&fcpvd1>;
> + };
> +
> fcpvd1: fcp@fea2f000 {
> compatible = "renesas,fcpv";
> reg = <0 0xfea2f000 0 0x200>;
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2 2/4] arm64: dts: renesas: r8a77995: add VSP instances
2018-02-13 22:03 ` Laurent Pinchart
@ 2018-02-14 8:39 ` Kieran Bingham
0 siblings, 0 replies; 9+ messages in thread
From: Kieran Bingham @ 2018-02-14 8:39 UTC (permalink / raw)
To: Laurent Pinchart
Cc: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Simon Horman,
Kieran Bingham, Kieran Bingham, Magnus Damm, Rob Herring,
Mark Rutland, Catalin Marinas, Will Deacon,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM64 PORT (AARCH64 ARCHITECTURE), open list
Hi Laurent,
Thanks for the review,
On 13/02/18 22:03, Laurent Pinchart wrote:
> Hi Kieran,
>
> Thank you for the patch.
>
> On Tuesday, 13 February 2018 21:30:35 EET Kieran Bingham wrote:
>> From: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
>>
>> The r8a77995 has a VSPBS to support image processing such as blending of
>> two input images, and has two VSPDs to handle display pipelines with a
>> DU.
>>
>> Signed-off-by: Kieran Bingham <kieran.bingham+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
>>
>> ---
>> v2:
>> - Fix VSPD register map size
>> - Squash VSPBS and VSPD patches together
>>
>> arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 ++++++++++++++++++++++++++++
>> 1 file changed, 30 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
>> b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index
>> 196a917afea6..19bd8be9926a 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
>> @@ -692,6 +692,16 @@
>> status = "disabled";
>> };
>>
>> + vspbs: vsp@fe960000 {
>> + compatible = "renesas,vsp2";
>> + reg = <0 0xfe960000 0 0x4000>;
>
> The VSPBS also has OSD-CLUT support in its RPFs, so you need to extend the
> registers range too.
>
Wait, but I already changed this ...
</me checks tree>
Yup - this change is already in my tree ... which means I must have made the
change *after* calling git format-patch. Not helpful.
Orz
> Apart from that,
>
> Reviewed-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
I'll collect the tag and repost, this time with the correctly updated version.
(And I'll add in that missing vspd3 from the es1 tree too)
>> + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 627>;
>> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
>> + resets = <&cpg 627>;
>> + renesas,fcp = <&fcpvb0>;
>> + };
>> +
>> fcpvb0: fcp@fe96f000 {
>> compatible = "renesas,fcpv";
>> reg = <0 0xfe96f000 0 0x200>;
>> @@ -701,6 +711,16 @@
>> iommus = <&ipmmu_vp0 5>;
>> };
>>
>> + vspd0: vsp@fea20000 {
>> + compatible = "renesas,vsp2";
>> + reg = <0 0xfea20000 0 0x8000>;
>> + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 623>;
>> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
>> + resets = <&cpg 623>;
>> + renesas,fcp = <&fcpvd0>;
>> + };
>> +
>> fcpvd0: fcp@fea27000 {
>> compatible = "renesas,fcpv";
>> reg = <0 0xfea27000 0 0x200>;
>> @@ -710,6 +730,16 @@
>> iommus = <&ipmmu_vi0 8>;
>> };
>>
>> + vspd1: vsp@fea80000 {
>> + compatible = "renesas,vsp2";
>> + reg = <0 0xfea28000 0 0x8000>;
>> + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 622>;
>> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
>> + resets = <&cpg 622>;
>> + renesas,fcp = <&fcpvd1>;
>> + };
>> +
>> fcpvd1: fcp@fea2f000 {
>> compatible = "renesas,fcpv";
>> reg = <0 0xfea2f000 0 0x200>;
>
--
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/4] arm64: dts: renesas: r8a7795: Fix register mappings on VSPs
[not found] <1518550237-16753-1-git-send-email-kbingham@kernel.org>
[not found] ` <1518550237-16753-1-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
2018-02-13 19:30 ` [PATCH v2 2/4] arm64: dts: renesas: r8a77995: add VSP instances Kieran Bingham
@ 2018-02-13 19:30 ` Kieran Bingham
[not found] ` <1518550237-16753-4-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
2018-02-13 19:30 ` [PATCH v2 4/4] arm64: dts: renesas: r8a7796: " Kieran Bingham
3 siblings, 1 reply; 9+ messages in thread
From: Kieran Bingham @ 2018-02-13 19:30 UTC (permalink / raw)
To: linux-renesas-soc, Simon Horman, Laurent Pinchart, Kieran Bingham
Cc: Kieran Bingham, Magnus Damm, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM64 PORT AARCH64 ARCHITECTURE, open list
From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
The VSPD includes a CLUT on RPF2. Ensure that the register space is
mapped correctly to support this.
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 1f32340af2d1..772991db8820 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -2607,7 +2607,7 @@
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x4000>;
+ reg = <0 0xfea20000 0 0x8000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2627,7 +2627,7 @@
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x4000>;
+ reg = <0 0xfea28000 0 0x8000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2647,7 +2647,7 @@
vspd2: vsp@fea30000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea30000 0 0x4000>;
+ reg = <0 0xfea30000 0 0x8000>;
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 4/4] arm64: dts: renesas: r8a7796: Fix register mappings on VSPs
[not found] <1518550237-16753-1-git-send-email-kbingham@kernel.org>
` (2 preceding siblings ...)
2018-02-13 19:30 ` [PATCH v2 3/4] arm64: dts: renesas: r8a7795: Fix register mappings on VSPs Kieran Bingham
@ 2018-02-13 19:30 ` Kieran Bingham
2018-02-13 22:04 ` Laurent Pinchart
3 siblings, 1 reply; 9+ messages in thread
From: Kieran Bingham @ 2018-02-13 19:30 UTC (permalink / raw)
To: linux-renesas-soc, Simon Horman, Laurent Pinchart, Kieran Bingham
Cc: Kieran Bingham, Magnus Damm, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM64 PORT AARCH64 ARCHITECTURE, open list
From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
The VSPD includes a CLUT on RPF2. Ensure that the register space is
mapped correctly to support this.
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 60755117cba5..3fe5566e0630 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -2285,7 +2285,7 @@
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x4000>;
+ reg = <0 0xfea20000 0 0x8000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -2305,7 +2305,7 @@
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x4000>;
+ reg = <0 0xfea28000 0 0x8000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -2325,7 +2325,7 @@
vspd2: vsp@fea30000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea30000 0 0x4000>;
+ reg = <0 0xfea30000 0 0x8000>;
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 4/4] arm64: dts: renesas: r8a7796: Fix register mappings on VSPs
2018-02-13 19:30 ` [PATCH v2 4/4] arm64: dts: renesas: r8a7796: " Kieran Bingham
@ 2018-02-13 22:04 ` Laurent Pinchart
0 siblings, 0 replies; 9+ messages in thread
From: Laurent Pinchart @ 2018-02-13 22:04 UTC (permalink / raw)
To: Kieran Bingham
Cc: linux-renesas-soc, Simon Horman, Kieran Bingham, Kieran Bingham,
Magnus Damm, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM64 PORT (AARCH64 ARCHITECTURE), open list
Hi Kieran,
Thank you for the patch.
On Tuesday, 13 February 2018 21:30:37 EET Kieran Bingham wrote:
> From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
>
> The VSPD includes a CLUT on RPF2. Ensure that the register space is
> mapped correctly to support this.
>
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 60755117cba5..3fe5566e0630
> 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> @@ -2285,7 +2285,7 @@
>
> vspd0: vsp@fea20000 {
> compatible = "renesas,vsp2";
> - reg = <0 0xfea20000 0 0x4000>;
> + reg = <0 0xfea20000 0 0x8000>;
> interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpg CPG_MOD 623>;
> power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
> @@ -2305,7 +2305,7 @@
>
> vspd1: vsp@fea28000 {
> compatible = "renesas,vsp2";
> - reg = <0 0xfea28000 0 0x4000>;
> + reg = <0 0xfea28000 0 0x8000>;
> interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpg CPG_MOD 622>;
> power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
> @@ -2325,7 +2325,7 @@
>
> vspd2: vsp@fea30000 {
> compatible = "renesas,vsp2";
> - reg = <0 0xfea30000 0 0x4000>;
> + reg = <0 0xfea30000 0 0x8000>;
> interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpg CPG_MOD 621>;
> power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-02-14 8:39 UTC | newest]
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2018-02-13 19:30 ` [PATCH v2 1/4] arm64: dts: renesas: r8a77995: add FCPV nodes Kieran Bingham
2018-02-13 22:02 ` Laurent Pinchart
2018-02-13 19:30 ` [PATCH v2 2/4] arm64: dts: renesas: r8a77995: add VSP instances Kieran Bingham
2018-02-13 22:03 ` Laurent Pinchart
2018-02-14 8:39 ` Kieran Bingham
2018-02-13 19:30 ` [PATCH v2 3/4] arm64: dts: renesas: r8a7795: Fix register mappings on VSPs Kieran Bingham
[not found] ` <1518550237-16753-4-git-send-email-kbingham-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
2018-02-13 22:04 ` Laurent Pinchart
2018-02-13 19:30 ` [PATCH v2 4/4] arm64: dts: renesas: r8a7796: " Kieran Bingham
2018-02-13 22:04 ` Laurent Pinchart
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