* [PATCH v3 1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support
@ 2026-02-10 2:26 Fabio Estevam
2026-02-10 2:26 ` [PATCH v3 2/2] clk: rockchip: Add clock controller for the RV1103B Fabio Estevam
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Fabio Estevam @ 2026-02-10 2:26 UTC (permalink / raw)
To: sboyd
Cc: robh, krzk+dt, conor+dt, heiko, linux-clk, jonas, devicetree,
Fabio Estevam, Krzysztof Kozlowski
From: Fabio Estevam <festevam@nabladev.com>
Add support for the Rockchip RV1103B Clock and Reset Unit (CRU).
The RV1103B CRU is compatible with the existing RV1126B binding.
Add the compatible string to the schema and introduce the
corresponding clock ID definitions.
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
Changes since v2:
- None. Only added Krzysztof's RB tag.
.../bindings/clock/rockchip,rv1126b-cru.yaml | 1 +
.../dt-bindings/clock/rockchip,rv1103b-cru.h | 220 ++++++++++++++++++
2 files changed, 221 insertions(+)
create mode 100644 include/dt-bindings/clock/rockchip,rv1103b-cru.h
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
index 04b0a5c51e4e..b6d3a04be8f1 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
+++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
@@ -17,6 +17,7 @@ description:
properties:
compatible:
enum:
+ - rockchip,rv1103b-cru
- rockchip,rv1126b-cru
reg:
diff --git a/include/dt-bindings/clock/rockchip,rv1103b-cru.h b/include/dt-bindings/clock/rockchip,rv1103b-cru.h
new file mode 100644
index 000000000000..35afdee7e961
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rv1103b-cru.h
@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
+
+#define PLL_GPLL 0
+#define ARMCLK 1
+#define PLL_DPLL 2
+#define XIN_OSC0_HALF 3
+#define CLK_GPLL_DIV24 4
+#define CLK_GPLL_DIV12 5
+#define CLK_GPLL_DIV6 6
+#define CLK_GPLL_DIV4 7
+#define CLK_GPLL_DIV3 8
+#define CLK_GPLL_DIV2P5 9
+#define CLK_GPLL_DIV2 10
+#define CLK_UART0_SRC 11
+#define CLK_UART1_SRC 12
+#define CLK_UART2_SRC 13
+#define CLK_UART0_FRAC 14
+#define CLK_UART1_FRAC 15
+#define CLK_UART2_FRAC 16
+#define CLK_SAI_SRC 17
+#define CLK_SAI_FRAC 18
+#define LSCLK_NPU_SRC 19
+#define CLK_NPU_SRC 20
+#define ACLK_VEPU_SRC 21
+#define CLK_VEPU_SRC 22
+#define ACLK_VI_SRC 23
+#define CLK_ISP_SRC 24
+#define DCLK_VICAP 25
+#define CCLK_EMMC 26
+#define CCLK_SDMMC0 27
+#define SCLK_SFC_2X 28
+#define LSCLK_PERI_SRC 29
+#define ACLK_PERI_SRC 30
+#define HCLK_HPMCU 31
+#define SCLK_UART0 32
+#define SCLK_UART1 33
+#define SCLK_UART2 34
+#define CLK_I2C_PMU 35
+#define CLK_I2C_PERI 36
+#define CLK_SPI0 37
+#define CLK_PWM0_SRC 38
+#define CLK_PWM1 39
+#define CLK_PWM2 40
+#define DCLK_DECOM_SRC 41
+#define CCLK_SDMMC1 42
+#define CLK_CORE_CRYPTO 43
+#define CLK_PKA_CRYPTO 44
+#define CLK_CORE_RGA 45
+#define MCLK_SAI_SRC 46
+#define CLK_FREQ_PWM0_SRC 47
+#define CLK_COUNTER_PWM0_SRC 48
+#define PCLK_TOP_ROOT 49
+#define CLK_REF_MIPI0 50
+#define CLK_MIPI0_OUT2IO 51
+#define CLK_REF_MIPI1 52
+#define CLK_MIPI1_OUT2IO 53
+#define MCLK_SAI_OUT2IO 54
+#define ACLK_NPU_ROOT 55
+#define HCLK_RKNN 56
+#define ACLK_RKNN 57
+#define LSCLK_VEPU_ROOT 58
+#define HCLK_VEPU 59
+#define ACLK_VEPU 60
+#define CLK_CORE_VEPU 61
+#define PCLK_IOC_VCCIO3 62
+#define PCLK_ACODEC 63
+#define PCLK_USBPHY 64
+#define LSCLK_VI_100M 65
+#define LSCLK_VI_ROOT 66
+#define HCLK_ISP 67
+#define ACLK_ISP 68
+#define CLK_CORE_ISP 69
+#define ACLK_VICAP 70
+#define HCLK_VICAP 71
+#define ISP0CLK_VICAP 72
+#define PCLK_CSI2HOST0 73
+#define PCLK_CSI2HOST1 74
+#define HCLK_EMMC 75
+#define HCLK_SFC 76
+#define HCLK_SFC_XIP 77
+#define HCLK_SDMMC0 78
+#define PCLK_CSIPHY 79
+#define PCLK_GPIO1 80
+#define DBCLK_GPIO1 81
+#define PCLK_IOC_VCCIO47 82
+#define LSCLK_DDR_ROOT 83
+#define CLK_TIMER_DDRMON 84
+#define LSCLK_PMU_ROOT 85
+#define PCLK_PMU 86
+#define XIN_RC_DIV 87
+#define CLK_32K 88
+#define PCLK_PMU_GPIO0 89
+#define DBCLK_PMU_GPIO0 90
+#define CLK_DDR_FAIL_SAFE 91
+#define PCLK_PMU_HP_TIMER 92
+#define CLK_PMU_32K_HP_TIMER 93
+#define PCLK_PWM0 94
+#define CLK_PWM0 95
+#define CLK_OSC_PWM0 96
+#define CLK_RC_PWM0 97
+#define CLK_FREQ_PWM0 98
+#define CLK_COUNTER_PWM0 99
+#define PCLK_I2C0 100
+#define CLK_I2C0 101
+#define PCLK_UART0 102
+#define PCLK_IOC_PMUIO0 103
+#define CLK_REFOUT 104
+#define CLK_PREROLL 105
+#define CLK_PREROLL_32K 106
+#define CLK_LPMCU_PMU 107
+#define PCLK_SPI2AHB 108
+#define HCLK_SPI2AHB 109
+#define SCLK_SPI2AHB 110
+#define PCLK_WDT_LPMCU 111
+#define TCLK_WDT_LPMCU 112
+#define HCLK_SFC_PMU1 113
+#define HCLK_SFC_XIP_PMU1 114
+#define SCLK_SFC_2X_PMU1 115
+#define CLK_LPMCU 116
+#define CLK_LPMCU_RTC 117
+#define PCLK_LPMCU_MAILBOX 118
+#define PCLK_IOC_PMUIO1 119
+#define PCLK_CRU_PMU1 120
+#define PCLK_PERI_ROOT 121
+#define PCLK_RTC_ROOT 122
+#define CLK_TIMER_ROOT 123
+#define PCLK_TIMER 124
+#define CLK_TIMER0 125
+#define CLK_TIMER1 126
+#define CLK_TIMER2 127
+#define CLK_TIMER3 128
+#define CLK_TIMER4 129
+#define CLK_TIMER5 130
+#define PCLK_STIMER 131
+#define CLK_STIMER0 132
+#define CLK_STIMER1 133
+#define PCLK_WDT_NS 134
+#define TCLK_WDT_NS 135
+#define PCLK_WDT_S 136
+#define TCLK_WDT_S 137
+#define PCLK_WDT_HPMCU 138
+#define TCLK_WDT_HPMCU 139
+#define PCLK_I2C1 140
+#define CLK_I2C1 141
+#define PCLK_I2C2 142
+#define CLK_I2C2 143
+#define PCLK_I2C3 144
+#define CLK_I2C3 145
+#define PCLK_I2C4 146
+#define CLK_I2C4 147
+#define PCLK_SPI0 148
+#define PCLK_PWM1 149
+#define CLK_OSC_PWM1 150
+#define PCLK_PWM2 151
+#define CLK_OSC_PWM2 152
+#define PCLK_UART2 153
+#define PCLK_UART1 154
+#define ACLK_RKDMA 155
+#define PCLK_TSADC 156
+#define CLK_TSADC 157
+#define CLK_TSADC_TSEN 158
+#define PCLK_SARADC 159
+#define CLK_SARADC 160
+#define PCLK_GPIO2 161
+#define DBCLK_GPIO2 162
+#define PCLK_IOC_VCCIO6 163
+#define ACLK_USBOTG 164
+#define CLK_REF_USBOTG 165
+#define HCLK_SDMMC1 166
+#define HCLK_SAI 167
+#define MCLK_SAI 168
+#define ACLK_CRYPTO 169
+#define HCLK_CRYPTO 170
+#define HCLK_RK_RNG_NS 171
+#define HCLK_RK_RNG_S 172
+#define PCLK_OTPC_NS 173
+#define CLK_OTPC_ROOT_NS 174
+#define CLK_SBPI_OTPC_NS 175
+#define CLK_USER_OTPC_NS 176
+#define PCLK_OTPC_S 177
+#define CLK_OTPC_ROOT_S 178
+#define CLK_SBPI_OTPC_S 179
+#define CLK_USER_OTPC_S 180
+#define CLK_OTPC_ARB 181
+#define PCLK_OTP_MASK 182
+#define HCLK_RGA 183
+#define ACLK_RGA 184
+#define ACLK_MAC 185
+#define PCLK_MAC 186
+#define CLK_MACPHY 187
+#define ACLK_SPINLOCK 188
+#define HCLK_CACHE 189
+#define PCLK_HPMCU_MAILBOX 190
+#define PCLK_HPMCU_INTMUX 191
+#define CLK_HPMCU 192
+#define CLK_HPMCU_RTC 193
+#define DCLK_DECOM 194
+#define ACLK_DECOM 195
+#define PCLK_DECOM 196
+#define ACLK_SYS_SRAM 197
+#define PCLK_DMA2DDR 198
+#define ACLK_DMA2DDR 199
+#define PCLK_DCF 200
+#define ACLK_DCF 201
+#define MCLK_ACODEC_TX 202
+#define SCLK_UART0_SRC 203
+#define SCLK_UART1_SRC 204
+#define SCLK_UART2_SRC 205
+#define XIN_RC_SRC 206
+#define CLK_UTMI_USBOTG 207
+#define CLK_REF_USBPHY 208
+
+#endif // _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/2] clk: rockchip: Add clock controller for the RV1103B
2026-02-10 2:26 [PATCH v3 1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support Fabio Estevam
@ 2026-02-10 2:26 ` Fabio Estevam
2026-02-23 14:19 ` [PATCH v3 1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support Fabio Estevam
2026-03-02 12:01 ` Heiko Stuebner
2 siblings, 0 replies; 8+ messages in thread
From: Fabio Estevam @ 2026-02-10 2:26 UTC (permalink / raw)
To: sboyd
Cc: robh, krzk+dt, conor+dt, heiko, linux-clk, jonas, devicetree,
Fabio Estevam
From: Fabio Estevam <festevam@nabladev.com>
Add the clock and reset tree definitions for the RV1103B SoC.
Based on the 5.10 Rockchip vendor kernel driver.
Signed-off-by: Fabio Estevam <festevam@nabladev.com>
---
Changes since v2:
- Converted the CLK_RV1103B symbol to bool.
- Removed unneeded header files and definitions.
drivers/clk/rockchip/Kconfig | 7 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rv1103b.c | 658 +++++++++++++++++++++++++++++
drivers/clk/rockchip/clk.h | 49 +++
4 files changed, 715 insertions(+)
create mode 100644 drivers/clk/rockchip/clk-rv1103b.c
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index 5cf1e0fd6fb3..7e1433502061 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -16,6 +16,13 @@ config CLK_PX30
help
Build the driver for PX30 Clock Driver.
+config CLK_RV1103B
+ bool "Rockchip RV1103B clock controller support"
+ depends on ARM || COMPILE_TEST
+ default y
+ help
+ Build the driver for RV1103B Clock Driver.
+
config CLK_RV110X
bool "Rockchip RV110x clock controller support"
depends on ARM || COMPILE_TEST
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 4d8cbb2044c7..7c984ee006c6 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -18,6 +18,7 @@ clk-rockchip-y += gate-link.o
clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
obj-$(CONFIG_CLK_PX30) += clk-px30.o
+obj-$(CONFIG_CLK_RV1103B) += clk-rv1103b.o
obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o
obj-$(CONFIG_CLK_RV1126) += clk-rv1126.o
obj-$(CONFIG_CLK_RV1126B) += clk-rv1126b.o rst-rv1126b.o
diff --git a/drivers/clk/rockchip/clk-rv1103b.c b/drivers/clk/rockchip/clk-rv1103b.c
new file mode 100644
index 000000000000..7da1fda5e1b9
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rv1103b.c
@@ -0,0 +1,658 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <dt-bindings/clock/rockchip,rv1103b-cru.h>
+#include "clk.h"
+
+#define RV1103B_GRF_SOC_STATUS0 0x10
+#define RV1103B_FRAC_MAX_PRATE 1200000000
+#define PVTPLL_SRC_SEL_PVTPLL (BIT(0) | BIT(16))
+
+enum rv1103b_plls {
+ dpll,
+ gpll,
+};
+
+static struct rockchip_pll_rate_table rv1103b_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
+ { /* sentinel */ },
+};
+
+#define RV1103B_DIV_ACLK_CORE_MASK 0x1f
+#define RV1103B_DIV_ACLK_CORE_SHIFT 0
+#define RV1103B_DIV_PCLK_DBG_MASK 0x1f
+#define RV1103B_DIV_PCLK_DBG_SHIFT 8
+
+#define RV1103B_CLKSEL0(_aclk_core) \
+{ \
+ .reg = RV1103B_CORECLKSEL_CON(2), \
+ .val = HIWORD_UPDATE(_aclk_core - 1, RV1103B_DIV_ACLK_CORE_MASK, \
+ RV1103B_DIV_ACLK_CORE_SHIFT), \
+}
+
+#define RV1103B_CLKSEL1(_pclk_dbg) \
+{ \
+ .reg = RV1103B_CORECLKSEL_CON(2), \
+ .val = HIWORD_UPDATE(_pclk_dbg - 1, RV1103B_DIV_PCLK_DBG_MASK, \
+ RV1103B_DIV_PCLK_DBG_SHIFT), \
+}
+
+#define RV1103B_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
+{ \
+ .prate = _prate, \
+ .divs = { \
+ RV1103B_CLKSEL0(_aclk_core), \
+ RV1103B_CLKSEL1(_pclk_dbg), \
+ }, \
+}
+
+static struct rockchip_cpuclk_rate_table rv1103b_cpuclk_rates[] __initdata = {
+ RV1103B_CPUCLK_RATE(1608000000, 4, 10),
+ RV1103B_CPUCLK_RATE(1512000000, 4, 10),
+ RV1103B_CPUCLK_RATE(1416000000, 4, 10),
+ RV1103B_CPUCLK_RATE(1296000000, 3, 10),
+ RV1103B_CPUCLK_RATE(1200000000, 3, 10),
+ RV1103B_CPUCLK_RATE(1188000000, 3, 8),
+ RV1103B_CPUCLK_RATE(1104000000, 2, 8),
+ RV1103B_CPUCLK_RATE(1008000000, 2, 8),
+ RV1103B_CPUCLK_RATE(816000000, 2, 6),
+ RV1103B_CPUCLK_RATE(600000000, 2, 4),
+ RV1103B_CPUCLK_RATE(594000000, 2, 4),
+ RV1103B_CPUCLK_RATE(408000000, 1, 3),
+ RV1103B_CPUCLK_RATE(396000000, 1, 3),
+};
+
+PNAME(mux_pll_p) = { "xin24m" };
+PNAME(mux_200m_100m_p) = { "clk_gpll_div6", "clk_gpll_div12" };
+PNAME(mux_gpll_24m_p) = { "gpll", "xin24m" };
+PNAME(mux_480m_400m_300m_200m_p) = { "clk_gpll_div2p5", "clk_gpll_div3", "clk_gpll_div4", "clk_gpll_div6" };
+PNAME(mux_480m_400m_300m_p) = { "clk_gpll_div2p5", "clk_gpll_div3", "clk_gpll_div4" };
+PNAME(mux_300m_200m_p) = { "clk_gpll_div4", "clk_gpll_div6" };
+PNAME(mux_600m_480m_400m_p) = { "clk_gpll_div2", "clk_gpll_div2p5", "clk_gpll_div3" };
+PNAME(mux_400m_300m_p) = { "clk_gpll_div3", "clk_gpll_div4" };
+PNAME(mux_100m_24m_p) = { "clk_gpll_div12", "xin24m" };
+PNAME(mux_200m_24m_p) = { "clk_gpll_div6", "xin24m" };
+PNAME(mux_200m_100m_50m_24m_p) = { "clk_gpll_div6", "clk_gpll_div12", "clk_gpll_div24", "xin24m" };
+PNAME(mux_300m_200m_100m_p) = { "clk_gpll_div4", "clk_gpll_div6", "clk_gpll_div12" };
+PNAME(sclk_uart0_src_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
+PNAME(sclk_uart1_src_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
+PNAME(sclk_uart2_src_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
+PNAME(mclk_sai_src_p) = { "clk_sai_src", "clk_sai_frac", "mclk_sai_from_io", "xin_osc0_half" };
+PNAME(clk_freq_pwm0_src_p) = { "sclk_sai_from_io", "mclk_sai_from_io", "clk_testout_out" };
+PNAME(clk_counter_pwm0_src_p) = { "sclk_sai_from_io", "mclk_sai_from_io", "clk_testout_out" };
+PNAME(clk_mipi0_out2io_p) = { "clk_ref_mipi0", "xin24m" };
+PNAME(clk_mipi1_out2io_p) = { "clk_ref_mipi1", "xin24m" };
+PNAME(mclk_sai_out2io_p) = { "mclk_sai_src", "xin_osc0_half" };
+PNAME(aclk_npu_root_p) = { "clk_npu_src", "clk_npu_pvtpll" };
+PNAME(clk_core_vepu_p) = { "clk_vepu_src", "clk_vepu_pvtpll" };
+PNAME(lsclk_vi_root_p) = { "clk_gpll_div6", "lsclk_vi_100m" };
+PNAME(clk_core_isp_p) = { "clk_isp_src", "clk_isp_pvtpll_src" };
+PNAME(lsclk_pmu_root_p) = { "xin24m", "clk_rc_osc_io" };
+PNAME(xin_rc_div_p) = { "xin24m", "clk_rc_osc_io" };
+PNAME(clk_32k_p) = { "xin_rc_div", "clk_32k_rtc", "clk_32k_io" };
+PNAME(dbclk_pmu_gpio0_p) = { "xin24m", "clk_32k" };
+PNAME(sclk_sfc_2x_pmu1_p) = { "clk_gpll_div12", "clk_rc_osc_io" };
+PNAME(mux_armclk_p) = { "armclk_gpll", "clk_core_pvtpll" };
+
+static struct rockchip_pll_clock rv1103b_pll_clks[] __initdata = {
+ [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
+ CLK_IS_CRITICAL, RV1103B_PLL_CON(16),
+ RV1103B_MODE_CON, 0, 10, 0, rv1103b_pll_rates),
+ [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
+ CLK_IS_CRITICAL, RV1103B_PLL_CON(24),
+ RV1103B_MODE_CON, 0, 10, 0, rv1103b_pll_rates),
+};
+
+#define MFLAGS CLK_MUX_HIWORD_MASK
+#define DFLAGS CLK_DIVIDER_HIWORD_MASK
+#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
+
+static struct rockchip_clk_branch rv1103b_clk_uart0_fracmux __initdata =
+ MUX(SCLK_UART0_SRC, "sclk_uart0_src", sclk_uart0_src_p, CLK_SET_RATE_PARENT,
+ RV1103B_CLKSEL_CON(32), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1103b_clk_uart1_fracmux __initdata =
+ MUX(SCLK_UART1_SRC, "sclk_uart1_src", sclk_uart1_src_p, CLK_SET_RATE_PARENT,
+ RV1103B_CLKSEL_CON(32), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1103b_clk_uart2_fracmux __initdata =
+ MUX(SCLK_UART2_SRC, "sclk_uart2_src", sclk_uart2_src_p, CLK_SET_RATE_PARENT,
+ RV1103B_CLKSEL_CON(32), 12, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1103b_rcdiv_pmu_fracmux __initdata =
+ MUX(CLK_32K, "clk_32k", clk_32k_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ RK3568_PMU_CLKSEL_CON(0), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1103b_clk_branches[] __initdata = {
+
+ /* Clock Definition */
+ FACTOR(XIN_OSC0_HALF, "xin_osc0_half", "xin24m", 0, 1, 2),
+
+ COMPOSITE_NOGATE(0, "armclk_gpll", mux_gpll_24m_p, CLK_IS_CRITICAL,
+ RV1103B_CLKSEL_CON(37), 12, 1, MFLAGS, 13, 3, DFLAGS),
+
+ /* pd_top */
+ COMPOSITE_NOMUX(CLK_GPLL_DIV24, "clk_gpll_div24", "gpll", 0,
+ RV1103B_CLKSEL_CON(0), 0, 5, DFLAGS,
+ RV1103B_CLKGATE_CON(0), 0, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GPLL_DIV12, "clk_gpll_div12", "gpll", 0,
+ RV1103B_CLKSEL_CON(0), 5, 5, DFLAGS,
+ RV1103B_CLKGATE_CON(0), 1, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GPLL_DIV6, "clk_gpll_div6", "gpll", 0,
+ RV1103B_CLKSEL_CON(1), 0, 5, DFLAGS,
+ RV1103B_CLKGATE_CON(0), 3, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GPLL_DIV4, "clk_gpll_div4", "gpll", 0,
+ RV1103B_CLKSEL_CON(1), 10, 5, DFLAGS,
+ RV1103B_CLKGATE_CON(0), 5, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GPLL_DIV3, "clk_gpll_div3", "gpll", 0,
+ RV1103B_CLKSEL_CON(2), 0, 5, DFLAGS,
+ RV1103B_CLKGATE_CON(0), 7, GFLAGS),
+ COMPOSITE_NOMUX_HALFDIV(CLK_GPLL_DIV2P5, "clk_gpll_div2p5", "gpll", 0,
+ RV1103B_CLKSEL_CON(2), 5, 5, DFLAGS,
+ RV1103B_CLKGATE_CON(0), 8, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GPLL_DIV2, "clk_gpll_div2", "gpll", 0,
+ RV1103B_CLKSEL_CON(2), 10, 5, DFLAGS,
+ RV1103B_CLKGATE_CON(0), 9, GFLAGS),
+ COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "gpll", 0,
+ RV1103B_CLKSEL_CON(5), 0, 5, DFLAGS,
+ RV1103B_CLKGATE_CON(1), 0, GFLAGS),
+ COMPOSITE_NOMUX(CLK_UART1_SRC, "clk_uart1_src", "gpll", 0,
+ RV1103B_CLKSEL_CON(5), 5, 5, DFLAGS,
+ RV1103B_CLKGATE_CON(1), 1, GFLAGS),
+ COMPOSITE_NOMUX(CLK_UART2_SRC, "clk_uart2_src", "gpll", 0,
+ RV1103B_CLKSEL_CON(5), 10, 5, DFLAGS,
+ RV1103B_CLKGATE_CON(1), 2, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", 0,
+ RV1103B_CLKSEL_CON(10), 0,
+ RV1103B_CLKGATE_CON(1), 6, GFLAGS,
+ &rv1103b_clk_uart0_fracmux),
+ COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", 0,
+ RV1103B_CLKSEL_CON(11), 0,
+ RV1103B_CLKGATE_CON(1), 7, GFLAGS,
+ &rv1103b_clk_uart1_fracmux),
+ COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", 0,
+ RV1103B_CLKSEL_CON(12), 0,
+ RV1103B_CLKGATE_CON(1), 8, GFLAGS,
+ &rv1103b_clk_uart2_fracmux),
+ GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_src", 0,
+ RV1103B_CLKGATE_CON(3), 3, GFLAGS),
+ GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_src", 0,
+ RV1103B_CLKGATE_CON(3), 4, GFLAGS),
+ GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_src", 0,
+ RV1103B_CLKGATE_CON(3), 8, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_SAI_SRC, "clk_sai_src", "gpll", 0,
+ RV1103B_CLKSEL_CON(20), 0, 5, DFLAGS,
+ RV1103B_CLKGATE_CON(1), 12, GFLAGS),
+ MUX(MCLK_SAI_SRC, "mclk_sai_src", mclk_sai_src_p, CLK_SET_RATE_PARENT,
+ RV1103B_CLKSEL_CON(35), 10, 2, MFLAGS),
+ GATE(MCLK_SAI, "mclk_sai", "mclk_sai_src", 0,
+ RV1103B_CLKGATE_CON(5), 5, GFLAGS),
+
+ COMPOSITE_NODIV(LSCLK_NPU_SRC, "lsclk_npu_src", mux_200m_100m_p, CLK_IS_CRITICAL,
+ RV1103B_CLKSEL_CON(30), 0, 1, MFLAGS,
+ RV1103B_CLKGATE_CON(2), 0, GFLAGS),
+ COMPOSITE(CLK_NPU_SRC, "clk_npu_src", mux_gpll_24m_p, 0,
+ RV1103B_CLKSEL_CON(37), 0, 1, MFLAGS, 1, 2, DFLAGS,
+ RV1103B_CLKGATE_CON(5), 12, GFLAGS),
+ COMPOSITE_NODIV(ACLK_VEPU_SRC, "aclk_vepu_src", mux_480m_400m_300m_200m_p, 0,
+ RV1103B_CLKSEL_CON(30), 8, 2, MFLAGS,
+ RV1103B_CLKGATE_CON(2), 4, GFLAGS),
+ COMPOSITE(CLK_VEPU_SRC, "clk_vepu_src", mux_gpll_24m_p, 0,
+ RV1103B_CLKSEL_CON(37), 4, 1, MFLAGS, 5, 2, DFLAGS,
+ RV1103B_CLKGATE_CON(5), 13, GFLAGS),
+ COMPOSITE_NODIV(ACLK_VI_SRC, "aclk_vi_src", mux_480m_400m_300m_p, CLK_IS_CRITICAL,
+ RV1103B_CLKSEL_CON(30), 12, 2, MFLAGS,
+ RV1103B_CLKGATE_CON(2), 8, GFLAGS),
+ COMPOSITE(CLK_ISP_SRC, "clk_isp_src", mux_gpll_24m_p, 0,
+ RV1103B_CLKSEL_CON(37), 8, 1, MFLAGS, 9, 2, DFLAGS,
+ RV1103B_CLKGATE_CON(5), 14, GFLAGS),
+ COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", mux_300m_200m_p, 0,
+ RV1103B_CLKSEL_CON(30), 14, 1, MFLAGS,
+ RV1103B_CLKGATE_CON(2), 9, GFLAGS),
+ COMPOSITE(CCLK_EMMC, "cclk_emmc", mux_gpll_24m_p, 0,
+ RV1103B_CLKSEL_CON(31), 15, 1, MFLAGS, 0, 8, DFLAGS,
+ RV1103B_CLKGATE_CON(2), 10, GFLAGS),
+ COMPOSITE(CCLK_SDMMC0, "cclk_sdmmc0", mux_gpll_24m_p, 0,
+ RV1103B_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 8, DFLAGS,
+ RV1103B_CLKGATE_CON(2), 11, GFLAGS),
+ COMPOSITE(SCLK_SFC_2X, "sclk_sfc_2x", mux_gpll_24m_p, 0,
+ RV1103B_CLKSEL_CON(33), 15, 1, MFLAGS, 0, 8, DFLAGS,
+ RV1103B_CLKGATE_CON(2), 12, GFLAGS),
+ COMPOSITE_NODIV(LSCLK_PERI_SRC, "lsclk_peri_src", mux_300m_200m_p, CLK_IS_CRITICAL,
+ RV1103B_CLKSEL_CON(31), 9, 1, MFLAGS,
+ RV1103B_CLKGATE_CON(3), 0, GFLAGS),
+ COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_600m_480m_400m_p, CLK_IS_CRITICAL,
+ RV1103B_CLKSEL_CON(31), 10, 2, MFLAGS,
+ RV1103B_CLKGATE_CON(3), 1, GFLAGS),
+ COMPOSITE_NODIV(HCLK_HPMCU, "hclk_hpmcu", mux_400m_300m_p, 0,
+ RV1103B_CLKSEL_CON(31), 12, 1, MFLAGS,
+ RV1103B_CLKGATE_CON(3), 2, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C_PMU, "clk_i2c_pmu", mux_100m_24m_p, 0,
+ RV1103B_CLKSEL_CON(34), 0, 1, MFLAGS,
+ RV1103B_CLKGATE_CON(4), 0, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C_PERI, "clk_i2c_peri", mux_200m_24m_p, 0,
+ RV1103B_CLKSEL_CON(34), 1, 1, MFLAGS,
+ RV1103B_CLKGATE_CON(4), 4, GFLAGS),
+ COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
+ RV1103B_CLKSEL_CON(34), 2, 2, MFLAGS,
+ RV1103B_CLKGATE_CON(4), 5, GFLAGS),
+ COMPOSITE_NODIV(CLK_PWM0_SRC, "clk_pwm0_src", mux_100m_24m_p, 0,
+ RV1103B_CLKSEL_CON(34), 12, 1, MFLAGS,
+ RV1103B_CLKGATE_CON(4), 10, GFLAGS),
+ COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_24m_p, 0,
+ RV1103B_CLKSEL_CON(34), 13, 1, MFLAGS,
+ RV1103B_CLKGATE_CON(4), 11, GFLAGS),
+ COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_24m_p, 0,
+ RV1103B_CLKSEL_CON(34), 14, 1, MFLAGS,
+ RV1103B_CLKGATE_CON(4), 12, GFLAGS),
+ COMPOSITE_NODIV(DCLK_DECOM_SRC, "dclk_decom_src", mux_480m_400m_300m_p, 0,
+ RV1103B_CLKSEL_CON(35), 0, 2, MFLAGS,
+ RV1103B_CLKGATE_CON(5), 0, GFLAGS),
+ COMPOSITE(CCLK_SDMMC1, "cclk_sdmmc1", mux_gpll_24m_p, 0,
+ RV1103B_CLKSEL_CON(36), 15, 1, MFLAGS, 0, 8, DFLAGS,
+ RV1103B_CLKGATE_CON(5), 1, GFLAGS),
+ COMPOSITE_NODIV(CLK_CORE_CRYPTO, "clk_core_crypto", mux_300m_200m_100m_p, 0,
+ RV1103B_CLKSEL_CON(35), 2, 2, MFLAGS,
+ RV1103B_CLKGATE_CON(5), 2, GFLAGS),
+ COMPOSITE_NODIV(CLK_PKA_CRYPTO, "clk_pka_crypto", mux_300m_200m_100m_p, 0,
+ RV1103B_CLKSEL_CON(35), 4, 2, MFLAGS,
+ RV1103B_CLKGATE_CON(5), 3, GFLAGS),
+ COMPOSITE_NODIV(CLK_CORE_RGA, "clk_core_rga", mux_400m_300m_p, 0,
+ RV1103B_CLKSEL_CON(35), 8, 1, MFLAGS,
+ RV1103B_CLKGATE_CON(5), 4, GFLAGS),
+
+ GATE(PCLK_TOP_ROOT, "pclk_top_root", "clk_gpll_div12", CLK_IS_CRITICAL,
+ RV1103B_CLKGATE_CON(6), 0, GFLAGS),
+ COMPOSITE_NOMUX(CLK_REF_MIPI0, "clk_ref_mipi0", "clk_gpll_div2", 0,
+ RV1103B_CLKSEL_CON(40), 0, 5, DFLAGS,
+ RV1103B_CLKGATE_CON(6), 3, GFLAGS),
+ COMPOSITE_NODIV(CLK_MIPI0_OUT2IO, "clk_mipi0_out2io", clk_mipi0_out2io_p, CLK_SET_RATE_PARENT,
+ RV1103B_CLKSEL_CON(40), 6, 1, MFLAGS,
+ RV1103B_CLKGATE_CON(6), 4, GFLAGS),
+ COMPOSITE_NOMUX(CLK_REF_MIPI1, "clk_ref_mipi1", "clk_gpll_div2", 0,
+ RV1103B_CLKSEL_CON(40), 8, 5, DFLAGS,
+ RV1103B_CLKGATE_CON(6), 5, GFLAGS),
+ COMPOSITE_NODIV(CLK_MIPI1_OUT2IO, "clk_mipi1_out2io", clk_mipi1_out2io_p, CLK_SET_RATE_PARENT,
+ RV1103B_CLKSEL_CON(40), 14, 1, MFLAGS,
+ RV1103B_CLKGATE_CON(6), 6, GFLAGS),
+ COMPOSITE(MCLK_SAI_OUT2IO, "mclk_sai_out2io", mclk_sai_out2io_p, 0,
+ RV1103B_CLKSEL_CON(41), 7, 1, MFLAGS, 13, 3, DFLAGS,
+ RV1103B_CLKGATE_CON(6), 9, GFLAGS),
+
+ /* pd_vpu */
+ COMPOSITE_NODIV(ACLK_NPU_ROOT, "aclk_npu_root", aclk_npu_root_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+ RV1103B_NPUCLKSEL_CON(0), 1, 1, MFLAGS,
+ RV1103B_NPUCLKGATE_CON(0), 1, GFLAGS),
+ GATE(HCLK_RKNN, "hclk_rknn", "lsclk_npu_src", 0,
+ RV1103B_NPUCLKGATE_CON(0), 4, GFLAGS),
+ GATE(ACLK_RKNN, "aclk_rknn", "aclk_npu_root", 0,
+ RV1103B_NPUCLKGATE_CON(0), 5, GFLAGS),
+
+ /* pd_vepu */
+ COMPOSITE_NOMUX(LSCLK_VEPU_ROOT, "lsclk_vepu_root", "aclk_vepu_src", CLK_IS_CRITICAL,
+ RV1103B_VEPUCLKSEL_CON(0), 2, 2, DFLAGS,
+ RV1103B_VEPUCLKGATE_CON(0), 0, GFLAGS),
+ GATE(HCLK_VEPU, "hclk_vepu", "lsclk_vepu_root", 0,
+ RV1103B_VEPUCLKGATE_CON(0), 4, GFLAGS),
+ GATE(ACLK_VEPU, "aclk_vepu", "aclk_vepu_src", 0,
+ RV1103B_VEPUCLKGATE_CON(0), 5, GFLAGS),
+ COMPOSITE_NODIV(CLK_CORE_VEPU, "clk_core_vepu", clk_core_vepu_p, 0,
+ RV1103B_VEPUCLKSEL_CON(0), 1, 1, MFLAGS,
+ RV1103B_VEPUCLKGATE_CON(0), 6, GFLAGS),
+ GATE(PCLK_ACODEC, "pclk_acodec", "lsclk_vepu_root", 0,
+ RV1103B_VEPUCLKGATE_CON(0), 13, GFLAGS),
+ GATE(PCLK_USBPHY, "pclk_usbphy", "lsclk_vepu_root", 0,
+ RV1103B_VEPUCLKGATE_CON(0), 14, GFLAGS),
+
+ /* pd_vi */
+ FACTOR(LSCLK_VI_100M, "lsclk_vi_100m", "clk_gpll_div6", 0, 1, 2),
+ COMPOSITE_NODIV(LSCLK_VI_ROOT, "lsclk_vi_root", lsclk_vi_root_p, CLK_IS_CRITICAL,
+ RV1103B_VICLKSEL_CON(0), 3, 1, MFLAGS,
+ RV1103B_VICLKGATE_CON(0), 0, GFLAGS),
+ GATE(HCLK_ISP, "hclk_isp", "lsclk_vi_root", 0,
+ RV1103B_VICLKGATE_CON(0), 4, GFLAGS),
+ GATE(ACLK_ISP, "aclk_isp", "aclk_vi_src", 0,
+ RV1103B_VICLKGATE_CON(0), 5, GFLAGS),
+ COMPOSITE_NODIV(CLK_CORE_ISP, "clk_core_isp", clk_core_isp_p, 0,
+ RV1103B_VICLKSEL_CON(0), 1, 1, MFLAGS,
+ RV1103B_VICLKGATE_CON(0), 6, GFLAGS),
+ GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_src", 0,
+ RV1103B_VICLKGATE_CON(1), 2, GFLAGS),
+ GATE(HCLK_VICAP, "hclk_vicap", "lsclk_vi_root", 0,
+ RV1103B_VICLKGATE_CON(1), 3, GFLAGS),
+ GATE(ISP0CLK_VICAP, "isp0clk_vicap", "clk_core_isp", 0,
+ RV1103B_VICLKGATE_CON(1), 8, GFLAGS),
+ GATE(PCLK_CSI2HOST0, "pclk_csi2host0", "lsclk_vi_root", 0,
+ RV1103B_VICLKGATE_CON(1), 9, GFLAGS),
+ GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "lsclk_vi_root", 0,
+ RV1103B_VICLKGATE_CON(1), 11, GFLAGS),
+ GATE(HCLK_EMMC, "hclk_emmc", "lsclk_vi_root", 0,
+ RV1103B_VICLKGATE_CON(1), 13, GFLAGS),
+ GATE(HCLK_SFC, "hclk_sfc", "lsclk_vi_root", 0,
+ RV1103B_VICLKGATE_CON(1), 14, GFLAGS),
+ GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "lsclk_vi_root", 0,
+ RV1103B_VICLKGATE_CON(1), 15, GFLAGS),
+ GATE(HCLK_SDMMC0, "hclk_sdmmc0", "lsclk_vi_root", 0,
+ RV1103B_VICLKGATE_CON(2), 0, GFLAGS),
+ GATE(PCLK_CSIPHY, "pclk_csiphy", "lsclk_vi_root", 0,
+ RV1103B_VICLKGATE_CON(2), 2, GFLAGS),
+ GATE(PCLK_GPIO1, "pclk_gpio1", "lsclk_vi_root", 0,
+ RV1103B_VICLKGATE_CON(2), 3, GFLAGS),
+ GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
+ RV1103B_VICLKGATE_CON(2), 4, GFLAGS),
+
+ /* pd_ddr */
+ GATE(LSCLK_DDR_ROOT, "lsclk_ddr_root", "clk_gpll_div12", CLK_IS_CRITICAL,
+ RV1103B_DDRCLKGATE_CON(0), 0, GFLAGS),
+ GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0,
+ RV1103B_DDRCLKGATE_CON(0), 4, GFLAGS),
+ FACTOR(0, "sclk_ddr", "dpll", 0, 1, 2),
+
+ /* pd_pmu */
+ COMPOSITE(LSCLK_PMU_ROOT, "lsclk_pmu_root", lsclk_pmu_root_p, CLK_IS_CRITICAL,
+ RV1103B_PMUCLKSEL_CON(2), 4, 1, MFLAGS, 0, 2, DFLAGS,
+ RV1103B_PMUCLKGATE_CON(0), 0, GFLAGS),
+ GATE(PCLK_PMU, "pclk_pmu", "lsclk_pmu_root", CLK_IS_CRITICAL,
+ RV1103B_PMUCLKGATE_CON(0), 2, GFLAGS),
+ MUX(XIN_RC_SRC, "xin_rc_src", xin_rc_div_p, 0,
+ RV1103B_PMUCLKSEL_CON(0), 2, 1, MFLAGS),
+ COMPOSITE_FRACMUX(XIN_RC_DIV, "xin_rc_div", "xin_rc_src", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ RV1103B_PMUCLKSEL_CON(1), 0,
+ RV1103B_PMUCLKGATE_CON(0), 3, GFLAGS,
+ &rv1103b_rcdiv_pmu_fracmux),
+ GATE(PCLK_PMU_GPIO0, "pclk_pmu_gpio0", "lsclk_pmu_root", 0,
+ RV1103B_PMUCLKGATE_CON(0), 4, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_PMU_GPIO0, "dbclk_pmu_gpio0", dbclk_pmu_gpio0_p, 0,
+ RK3568_PMU_CLKSEL_CON(0), 3, 1, MFLAGS,
+ RV1103B_PMUCLKGATE_CON(0), 5, GFLAGS),
+ GATE(PCLK_PWM0, "pclk_pwm0", "lsclk_pmu_root", 0,
+ RV1103B_PMUCLKGATE_CON(2), 0, GFLAGS),
+ GATE(CLK_PWM0, "clk_pwm0", "clk_pwm0_src", 0,
+ RV1103B_PMUCLKGATE_CON(2), 1, GFLAGS),
+ GATE(CLK_OSC_PWM0, "clk_osc_pwm0", "xin24m", 0,
+ RV1103B_PMUCLKGATE_CON(2), 2, GFLAGS),
+ GATE(CLK_RC_PWM0, "clk_rc_pwm0", "clk_32k", 0,
+ RV1103B_PMUCLKGATE_CON(2), 3, GFLAGS),
+ GATE(PCLK_I2C0, "pclk_i2c0", "lsclk_pmu_root", 0,
+ RV1103B_PMUCLKGATE_CON(0), 12, GFLAGS),
+ GATE(CLK_I2C0, "clk_i2c0", "clk_i2c_pmu", 0,
+ RV1103B_PMUCLKGATE_CON(0), 13, GFLAGS),
+ GATE(PCLK_UART0, "pclk_uart0", "lsclk_pmu_root", 0,
+ RV1103B_PMUCLKGATE_CON(0), 14, GFLAGS),
+ GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
+ RV1103B_PMUCLKGATE_CON(1), 4, GFLAGS),
+ GATE(CLK_PREROLL, "clk_preroll", "lsclk_pmu_root", 0,
+ RV1103B_PMUCLKGATE_CON(1), 6, GFLAGS),
+ GATE(CLK_PREROLL_32K, "clk_preroll_32k", "clk_32k", 0,
+ RV1103B_PMUCLKGATE_CON(1), 7, GFLAGS),
+ GATE(CLK_LPMCU_PMU, "clk_lpmcu_pmu", "lsclk_pmu_root", 0,
+ RV1103B_PMUCLKGATE_CON(2), 12, GFLAGS),
+
+ /* pd_pmu1 */
+ GATE(PCLK_SPI2AHB, "pclk_spi2ahb", "lsclk_pmu_root", 0,
+ RV1103B_PMU1CLKGATE_CON(0), 0, GFLAGS),
+ GATE(HCLK_SPI2AHB, "hclk_spi2ahb", "lsclk_pmu_root", 0,
+ RV1103B_PMU1CLKGATE_CON(0), 1, GFLAGS),
+ GATE(PCLK_WDT_LPMCU, "pclk_wdt_lpmcu", "lsclk_pmu_root", 0,
+ RV1103B_PMU1CLKGATE_CON(0), 9, GFLAGS),
+ GATE(TCLK_WDT_LPMCU, "tclk_wdt_lpmcu", "xin24m", 0,
+ RV1103B_PMU1CLKGATE_CON(0), 10, GFLAGS),
+ GATE(HCLK_SFC_PMU1, "hclk_sfc_pmu1", "lsclk_pmu_root", 0,
+ RV1103B_PMU1CLKGATE_CON(0), 12, GFLAGS),
+ GATE(HCLK_SFC_XIP_PMU1, "hclk_sfc_xip_pmu1", "lsclk_pmu_root", 0,
+ RV1103B_PMU1CLKGATE_CON(0), 13, GFLAGS),
+ COMPOSITE_NODIV(SCLK_SFC_2X_PMU1, "sclk_sfc_2x_pmu1", sclk_sfc_2x_pmu1_p, 0,
+ RV1103B_PMU1CLKSEL_CON(0), 8, 1, MFLAGS,
+ RV1103B_PMU1CLKGATE_CON(0), 14, GFLAGS),
+ GATE(CLK_LPMCU, "clk_lpmcu", "lsclk_pmu_root", 0,
+ RV1103B_PMU1CLKGATE_CON(1), 0, GFLAGS),
+ GATE(CLK_LPMCU_RTC, "clk_lpmcu_rtc", "xin24m", 0,
+ RV1103B_PMU1CLKGATE_CON(1), 4, GFLAGS),
+ GATE(PCLK_LPMCU_MAILBOX, "pclk_lpmcu_mailbox", "lsclk_pmu_root", 0,
+ RV1103B_PMU1CLKGATE_CON(1), 8, GFLAGS),
+
+ /* pd_peri */
+ COMPOSITE_NOMUX(PCLK_PERI_ROOT, "pclk_peri_root", "lsclk_peri_src", CLK_IS_CRITICAL,
+ RV1103B_PERICLKSEL_CON(0), 0, 2, DFLAGS,
+ RV1103B_PERICLKGATE_CON(0), 0, GFLAGS),
+ COMPOSITE_NOMUX(PCLK_RTC_ROOT, "pclk_rtc_root", "lsclk_peri_src", CLK_IS_CRITICAL,
+ RV1103B_PERICLKSEL_CON(2), 12, 4, DFLAGS,
+ RV1103B_PERICLKGATE_CON(0), 8, GFLAGS),
+ GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
+ RV1103B_PERICLKGATE_CON(0), 1, GFLAGS),
+ GATE(PCLK_TIMER, "pclk_timer", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(1), 0, GFLAGS),
+ GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
+ RV1103B_PERICLKGATE_CON(1), 1, GFLAGS),
+ GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
+ RV1103B_PERICLKGATE_CON(1), 2, GFLAGS),
+ GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0,
+ RV1103B_PERICLKGATE_CON(1), 3, GFLAGS),
+ GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0,
+ RV1103B_PERICLKGATE_CON(1), 4, GFLAGS),
+ GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0,
+ RV1103B_PERICLKGATE_CON(1), 5, GFLAGS),
+ GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
+ RV1103B_PERICLKGATE_CON(1), 6, GFLAGS),
+ GATE(PCLK_STIMER, "pclk_stimer", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(1), 7, GFLAGS),
+ GATE(CLK_STIMER0, "clk_stimer0", "clk_timer_root", 0,
+ RV1103B_PERICLKGATE_CON(1), 8, GFLAGS),
+ GATE(CLK_STIMER1, "clk_stimer1", "clk_timer_root", 0,
+ RV1103B_PERICLKGATE_CON(1), 9, GFLAGS),
+ GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(2), 0, GFLAGS),
+ GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
+ RV1103B_PERICLKGATE_CON(2), 1, GFLAGS),
+ GATE(PCLK_WDT_S, "pclk_wdt_s", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(2), 2, GFLAGS),
+ GATE(TCLK_WDT_S, "tclk_wdt_s", "xin24m", 0,
+ RV1103B_PERICLKGATE_CON(2), 3, GFLAGS),
+ GATE(PCLK_WDT_HPMCU, "pclk_wdt_hpmcu", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(2), 4, GFLAGS),
+ GATE(TCLK_WDT_HPMCU, "tclk_wdt_hpmcu", "xin24m", 0,
+ RV1103B_PERICLKGATE_CON(2), 5, GFLAGS),
+ GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(2), 6, GFLAGS),
+ GATE(CLK_I2C1, "clk_i2c1", "clk_i2c_peri", 0,
+ RV1103B_PERICLKGATE_CON(2), 7, GFLAGS),
+ GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(2), 8, GFLAGS),
+ GATE(CLK_I2C2, "clk_i2c2", "clk_i2c_peri", 0,
+ RV1103B_PERICLKGATE_CON(2), 9, GFLAGS),
+ GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(2), 10, GFLAGS),
+ GATE(CLK_I2C3, "clk_i2c3", "clk_i2c_peri", 0,
+ RV1103B_PERICLKGATE_CON(2), 11, GFLAGS),
+ GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(2), 12, GFLAGS),
+ GATE(CLK_I2C4, "clk_i2c4", "clk_i2c_peri", 0,
+ RV1103B_PERICLKGATE_CON(2), 13, GFLAGS),
+ GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(3), 10, GFLAGS),
+ GATE(PCLK_PWM1, "pclk_pwm1", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(4), 6, GFLAGS),
+ GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0,
+ RV1103B_PERICLKGATE_CON(4), 8, GFLAGS),
+ GATE(PCLK_PWM2, "pclk_pwm2", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(4), 12, GFLAGS),
+ GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0,
+ RV1103B_PERICLKGATE_CON(4), 13, GFLAGS),
+ GATE(PCLK_UART2, "pclk_uart2", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(3), 0, GFLAGS),
+ GATE(PCLK_UART1, "pclk_uart1", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(3), 2, GFLAGS),
+ GATE(ACLK_RKDMA, "aclk_rkdma", "lsclk_peri_src", 0,
+ RV1103B_PERICLKGATE_CON(5), 8, GFLAGS),
+ GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(5), 9, GFLAGS),
+ COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
+ RV1103B_PERICLKSEL_CON(0), 4, 5, DFLAGS,
+ RV1103B_PERICLKGATE_CON(5), 10, GFLAGS),
+ COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
+ RV1103B_PERICLKSEL_CON(0), 10, 5, DFLAGS,
+ RV1103B_PERICLKGATE_CON(5), 11, GFLAGS),
+ GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(5), 12, GFLAGS),
+ COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
+ RV1103B_PERICLKSEL_CON(1), 0, 3, DFLAGS,
+ RV1103B_PERICLKGATE_CON(5), 13, GFLAGS),
+ GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(6), 3, GFLAGS),
+ GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
+ RV1103B_PERICLKGATE_CON(6), 4, GFLAGS),
+ GATE(ACLK_USBOTG, "aclk_usbotg", "lsclk_peri_src", 0,
+ RV1103B_PERICLKGATE_CON(6), 9, GFLAGS),
+ GATE(CLK_REF_USBOTG, "clk_ref_usbotg", "xin24m", 0,
+ RV1103B_PERICLKGATE_CON(6), 10, GFLAGS),
+ GATE(HCLK_SDMMC1, "hclk_sdmmc1", "lsclk_peri_src", 0,
+ RV1103B_PERICLKGATE_CON(7), 0, GFLAGS),
+ GATE(HCLK_SAI, "hclk_sai", "lsclk_peri_src", 0,
+ RV1103B_PERICLKGATE_CON(7), 1, GFLAGS),
+ GATE(ACLK_CRYPTO, "aclk_crypto", "lsclk_peri_src", 0,
+ RV1103B_PERICLKGATE_CON(8), 2, GFLAGS),
+ GATE(HCLK_CRYPTO, "hclk_crypto", "lsclk_peri_src", 0,
+ RV1103B_PERICLKGATE_CON(8), 3, GFLAGS),
+ GATE(HCLK_RK_RNG_S, "hclk_rk_rng_s", "lsclk_peri_src", 0,
+ RV1103B_PERICLKGATE_CON(8), 5, GFLAGS),
+ GATE(HCLK_RK_RNG_NS, "hclk_rk_rng_ns", "hclk_rk_rng_s", 0,
+ RV1103B_PERICLKGATE_CON(8), 4, GFLAGS),
+ GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(8), 6, GFLAGS),
+ GATE(CLK_OTPC_ROOT_NS, "clk_otpc_root_ns", "xin24m", 0,
+ RV1103B_PERICLKGATE_CON(8), 7, GFLAGS),
+ GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "clk_otpc_root_ns", 0,
+ RV1103B_PERICLKGATE_CON(8), 8, GFLAGS),
+ COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_otpc_root_ns", 0,
+ RV1103B_PERICLKSEL_CON(1), 4, 3, DFLAGS,
+ RV1103B_PERICLKGATE_CON(8), 9, GFLAGS),
+ GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(8), 10, GFLAGS),
+ GATE(CLK_OTPC_ROOT_S, "clk_otpc_root_s", "xin24m", 0,
+ RV1103B_PERICLKGATE_CON(8), 11, GFLAGS),
+ GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "clk_otpc_root_s", 0,
+ RV1103B_PERICLKGATE_CON(8), 12, GFLAGS),
+ COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "clk_otpc_root_s", 0,
+ RV1103B_PERICLKSEL_CON(1), 8, 3, DFLAGS,
+ RV1103B_PERICLKGATE_CON(8), 13, GFLAGS),
+ GATE(PCLK_OTP_MASK, "pclk_otp_mask", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(8), 15, GFLAGS),
+ GATE(HCLK_RGA, "hclk_rga", "lsclk_peri_src", 0,
+ RV1103B_PERICLKGATE_CON(9), 0, GFLAGS),
+ GATE(ACLK_RGA, "aclk_rga", "aclk_peri_src", 0,
+ RV1103B_PERICLKGATE_CON(9), 1, GFLAGS),
+ GATE(ACLK_MAC, "aclk_mac", "lsclk_peri_src", 0,
+ RV1103B_PERICLKGATE_CON(9), 3, GFLAGS),
+ GATE(PCLK_MAC, "pclk_mac", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(9), 4, GFLAGS),
+ GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
+ RV1103B_PERICLKGATE_CON(9), 11, GFLAGS),
+ GATE(ACLK_SPINLOCK, "aclk_spinlock", "lsclk_peri_src", 0,
+ RV1103B_PERICLKGATE_CON(10), 0, GFLAGS),
+ GATE(HCLK_CACHE, "hclk_cache", "hclk_hpmcu", 0,
+ RV1103B_PERICLKGATE_CON(10), 1, GFLAGS),
+ GATE(PCLK_HPMCU_MAILBOX, "pclk_hpmcu_mailbox", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(10), 2, GFLAGS),
+ GATE(PCLK_HPMCU_INTMUX, "pclk_hpmcu_intmux", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(10), 3, GFLAGS),
+ GATE(CLK_HPMCU, "clk_hpmcu", "hclk_hpmcu", 0,
+ RV1103B_PERICLKGATE_CON(10), 4, GFLAGS),
+ GATE(CLK_HPMCU_RTC, "clk_hpmcu_rtc", "xin24m", 0,
+ RV1103B_PERICLKGATE_CON(10), 8, GFLAGS),
+ GATE(DCLK_DECOM, "dclk_decom", "dclk_decom_src", 0,
+ RV1103B_PERICLKGATE_CON(11), 0, GFLAGS),
+ GATE(ACLK_DECOM, "aclk_decom", "aclk_peri_src", 0,
+ RV1103B_PERICLKGATE_CON(11), 1, GFLAGS),
+ GATE(PCLK_DECOM, "pclk_decom", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(11), 2, GFLAGS),
+ GATE(ACLK_SYS_SRAM, "aclk_sys_sram", "lsclk_peri_src", CLK_IS_CRITICAL,
+ RV1103B_PERICLKGATE_CON(11), 3, GFLAGS),
+ GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(11), 4, GFLAGS),
+ GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_peri_src", 0,
+ RV1103B_PERICLKGATE_CON(11), 5, GFLAGS),
+ GATE(PCLK_DCF, "pclk_dcf", "pclk_peri_root", 0,
+ RV1103B_PERICLKGATE_CON(11), 6, GFLAGS),
+ GATE(ACLK_DCF, "aclk_dcf", "lsclk_peri_src", 0,
+ RV1103B_PERICLKGATE_CON(11), 7, GFLAGS),
+ COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_sai_src", 0,
+ RV1103B_PERICLKSEL_CON(2), 0, 3, DFLAGS,
+ RV1103B_PERICLKGATE_CON(11), 9, GFLAGS),
+ GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
+ RV1103B_PERICLKGATE_CON(11), 12, GFLAGS),
+
+ /* io */
+ COMPOSITE_NODIV(CLK_FREQ_PWM0_SRC, "clk_freq_pwm0_src", clk_freq_pwm0_src_p, 0,
+ RV1103B_CLKSEL_CON(35), 12, 2, MFLAGS,
+ RV1103B_CLKGATE_CON(5), 6, GFLAGS),
+ GATE(CLK_FREQ_PWM0, "clk_freq_pwm0", "clk_freq_pwm0_src", 0,
+ RV1103B_PMUCLKGATE_CON(2), 4, GFLAGS),
+ COMPOSITE_NODIV(CLK_COUNTER_PWM0_SRC, "clk_counter_pwm0_src", clk_counter_pwm0_src_p, 0,
+ RV1103B_CLKSEL_CON(35), 14, 2, MFLAGS,
+ RV1103B_CLKGATE_CON(5), 7, GFLAGS),
+ GATE(CLK_COUNTER_PWM0, "clk_counter_pwm0", "clk_counter_pwm0_src", 0,
+ RV1103B_PMUCLKGATE_CON(2), 5, GFLAGS),
+ GATE(SCLK_SPI2AHB, "sclk_spi2ahb", "sclk_spi2ahb_io", 0,
+ RV1103B_PMU1CLKGATE_CON(0), 2, GFLAGS),
+ GATE(CLK_UTMI_USBOTG, "clk_utmi_usbotg", "clk_utmi_usbotg_io", 0,
+ RV1103B_PERICRU_IP_CON, 14, GFLAGS),
+};
+
+static struct rockchip_clk_branch rv1103b_armclk __initdata =
+ MUX(ARMCLK, "armclk", mux_armclk_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ RV1103B_CORECLKSEL_CON(0), 1, 1, MFLAGS);
+
+static void __init rv1103b_clk_init(struct device_node *np)
+{
+ struct rockchip_clk_provider *ctx;
+ unsigned long clk_nr;
+ void __iomem *reg_base;
+
+ clk_nr = rockchip_clk_find_max_clk_id(rv1103b_clk_branches,
+ ARRAY_SIZE(rv1103b_clk_branches)) + 1;
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru region\n", __func__);
+ return;
+ }
+
+ ctx = rockchip_clk_init(np, reg_base, clk_nr);
+ if (IS_ERR(ctx)) {
+ pr_err("%s: rockchip clk init failed\n", __func__);
+ iounmap(reg_base);
+ return;
+ }
+
+ rockchip_clk_register_plls(ctx, rv1103b_pll_clks,
+ ARRAY_SIZE(rv1103b_pll_clks),
+ RV1103B_GRF_SOC_STATUS0);
+
+ rockchip_clk_register_branches(ctx, rv1103b_clk_branches,
+ ARRAY_SIZE(rv1103b_clk_branches));
+
+ rockchip_clk_register_armclk_multi_pll(ctx, &rv1103b_armclk,
+ rv1103b_cpuclk_rates,
+ ARRAY_SIZE(rv1103b_cpuclk_rates));
+
+ rockchip_register_restart_notifier(ctx, RV1103B_GLB_SRST_FST, NULL);
+
+ rockchip_clk_of_add_provider(np, ctx);
+
+ /* pvtpll src init */
+ writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_CORECLKSEL_CON(0));
+ writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_NPUCLKSEL_CON(0));
+ writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_VICLKSEL_CON(0));
+ writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_VEPUCLKSEL_CON(0));
+}
+
+CLK_OF_DECLARE(rv1103b_cru, "rockchip,rv1103b-cru", rv1103b_clk_init);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index b2fff1d13a4a..cf0f5f11c34b 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -66,6 +66,55 @@ struct clk;
#define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
#define PX30_PMU_MODE 0x0020
+#define RV1103B_TOPCRU_BASE 0x60000
+#define RV1103B_PERICRU_BASE 0x0
+#define RV1103B_VICRU_BASE 0x30000
+#define RV1103B_NPUCRU_BASE 0x20000
+#define RV1103B_CORECRU_BASE 0x40000
+#define RV1103B_VEPUCRU_BASE 0x10000
+#define RV1103B_DDRCRU_BASE 0x50000
+#define RV1103B_SUBDDRCRU_BASE 0x58000
+#define RV1103B_PMUCRU_BASE 0x70000
+#define RV1103B_PMU1CRU_BASE 0x80000
+
+#define RV1103B_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PMUCRU_BASE)
+#define RV1103B_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_PMUCRU_BASE)
+#define RV1103B_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_PMUCRU_BASE)
+#define RV1103B_PMU1CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PMU1CRU_BASE)
+#define RV1103B_PMU1CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_PMU1CRU_BASE)
+#define RV1103B_PMU1SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_PMU1CRU_BASE)
+#define RV1103B_PLL_CON(x) ((x) * 0x4 + RV1103B_TOPCRU_BASE)
+#define RV1103B_MODE_CON (0x280 + RV1103B_TOPCRU_BASE)
+#define RV1103B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_TOPCRU_BASE)
+#define RV1103B_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_TOPCRU_BASE)
+#define RV1103B_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_TOPCRU_BASE)
+#define RV1103B_GLB_SRST_FST (0xc08 + RV1103B_TOPCRU_BASE)
+#define RV1103B_GLB_SRST_SND (0xc0c + RV1103B_TOPCRU_BASE)
+#define RV1103B_CLK_SAI_FRAC_DIV_HIGH (0xcc0 + RV1103B_TOPCRU_BASE)
+#define RV1103B_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PERICRU_BASE)
+#define RV1103B_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_PERICRU_BASE)
+#define RV1103B_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_PERICRU_BASE)
+#define RV1103B_PERICRU_IP_CON (0xc08 + RV1103B_PERICRU_BASE)
+#define RV1103B_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_VICRU_BASE)
+#define RV1103B_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_VICRU_BASE)
+#define RV1103B_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_VICRU_BASE)
+#define RV1103B_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_NPUCRU_BASE)
+#define RV1103B_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_NPUCRU_BASE)
+#define RV1103B_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_NPUCRU_BASE)
+#define RV1103B_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_CORECRU_BASE)
+#define RV1103B_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_CORECRU_BASE)
+#define RV1103B_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_CORECRU_BASE)
+#define RV1103B_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_VEPUCRU_BASE)
+#define RV1103B_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_VEPUCRU_BASE)
+#define RV1103B_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_VEPUCRU_BASE)
+#define RV1103B_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_DDRCRU_BASE)
+#define RV1103B_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_DDRCRU_BASE)
+#define RV1103B_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_DDRCRU_BASE)
+#define RV1103B_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_SUBDDRCRU_BASE)
+#define RV1103B_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_SUBDDRCRU_BASE)
+#define RV1103B_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_SUBDDRCRU_BASE)
+#define RV1103B_SUBDDRMODE_CON (0x280 + RV1103B_SUBDDRCRU_BASE)
+
#define RV1108_PLL_CON(x) ((x) * 0x4)
#define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
#define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support
2026-02-10 2:26 [PATCH v3 1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support Fabio Estevam
2026-02-10 2:26 ` [PATCH v3 2/2] clk: rockchip: Add clock controller for the RV1103B Fabio Estevam
@ 2026-02-23 14:19 ` Fabio Estevam
2026-02-23 14:21 ` Heiko Stübner
2026-03-02 12:01 ` Heiko Stuebner
2 siblings, 1 reply; 8+ messages in thread
From: Fabio Estevam @ 2026-02-23 14:19 UTC (permalink / raw)
To: sboyd
Cc: robh, krzk+dt, conor+dt, heiko, linux-clk, jonas, devicetree,
Fabio Estevam, Krzysztof Kozlowski
Hi Stephen,
On Mon, Feb 9, 2026 at 11:26 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> From: Fabio Estevam <festevam@nabladev.com>
>
> Add support for the Rockchip RV1103B Clock and Reset Unit (CRU).
>
> The RV1103B CRU is compatible with the existing RV1126B binding.
> Add the compatible string to the schema and introduce the
> corresponding clock ID definitions.
>
> Signed-off-by: Fabio Estevam <festevam@nabladev.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
> Changes since v2:
> - None. Only added Krzysztof's RB tag.
>
> .../bindings/clock/rockchip,rv1126b-cru.yaml | 1 +
> .../dt-bindings/clock/rockchip,rv1103b-cru.h | 220 ++++++++++++++++++
> 2 files changed, 221 insertions(+)
> create mode 100644 include/dt-bindings/clock/rockchip,rv1103b-cru.h
As rockchip,rv1103b-cru.h is also used by the dts file, I think it
would be better if this series could go via Heiko's tree.
Would this work for you?
Thanks
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support
2026-02-23 14:19 ` [PATCH v3 1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support Fabio Estevam
@ 2026-02-23 14:21 ` Heiko Stübner
2026-02-23 14:34 ` Fabio Estevam
2026-03-02 11:46 ` Fabio Estevam
0 siblings, 2 replies; 8+ messages in thread
From: Heiko Stübner @ 2026-02-23 14:21 UTC (permalink / raw)
To: sboyd, Fabio Estevam
Cc: robh, krzk+dt, conor+dt, linux-clk, jonas, devicetree,
Fabio Estevam, Krzysztof Kozlowski
Hi Fabio,
Am Montag, 23. Februar 2026, 15:19:35 Mitteleuropäische Normalzeit schrieb Fabio Estevam:
> On Mon, Feb 9, 2026 at 11:26 PM Fabio Estevam <festevam@gmail.com> wrote:
> >
> > From: Fabio Estevam <festevam@nabladev.com>
> >
> > Add support for the Rockchip RV1103B Clock and Reset Unit (CRU).
> >
> > The RV1103B CRU is compatible with the existing RV1126B binding.
> > Add the compatible string to the schema and introduce the
> > corresponding clock ID definitions.
> >
> > Signed-off-by: Fabio Estevam <festevam@nabladev.com>
> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> > ---
> > Changes since v2:
> > - None. Only added Krzysztof's RB tag.
> >
> > .../bindings/clock/rockchip,rv1126b-cru.yaml | 1 +
> > .../dt-bindings/clock/rockchip,rv1103b-cru.h | 220 ++++++++++++++++++
> > 2 files changed, 221 insertions(+)
> > create mode 100644 include/dt-bindings/clock/rockchip,rv1103b-cru.h
>
> As rockchip,rv1103b-cru.h is also used by the dts file, I think it
> would be better if this series could go via Heiko's tree.
I generally pick up Rockchip clock changes anyway and then
send PRs to the clock maintainers, so that'll work as always :-) .
Heiko
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support
2026-02-23 14:21 ` Heiko Stübner
@ 2026-02-23 14:34 ` Fabio Estevam
2026-03-02 11:46 ` Fabio Estevam
1 sibling, 0 replies; 8+ messages in thread
From: Fabio Estevam @ 2026-02-23 14:34 UTC (permalink / raw)
To: Heiko Stübner
Cc: sboyd, robh, krzk+dt, conor+dt, linux-clk, jonas, devicetree,
Fabio Estevam, Krzysztof Kozlowski
Hi Heiko,
On Mon, Feb 23, 2026 at 11:21 AM Heiko Stübner <heiko@sntech.de> wrote:
> I generally pick up Rockchip clock changes anyway and then
> send PRs to the clock maintainers, so that'll work as always :-) .
Excellent! Thanks for letting me know.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support
2026-02-23 14:21 ` Heiko Stübner
2026-02-23 14:34 ` Fabio Estevam
@ 2026-03-02 11:46 ` Fabio Estevam
2026-03-02 12:01 ` Heiko Stuebner
1 sibling, 1 reply; 8+ messages in thread
From: Fabio Estevam @ 2026-03-02 11:46 UTC (permalink / raw)
To: Heiko Stübner
Cc: sboyd, robh, krzk+dt, conor+dt, linux-clk, jonas, devicetree,
Fabio Estevam, Krzysztof Kozlowski
Hi Heiko,
On Mon, Feb 23, 2026 at 11:21 AM Heiko Stübner <heiko@sntech.de> wrote:
> I generally pick up Rockchip clock changes anyway and then
> send PRs to the clock maintainers, so that'll work as always :-) .
Please let me know if you are OK with the RV1103B clock and dts series.
Thanks
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support
2026-02-10 2:26 [PATCH v3 1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support Fabio Estevam
2026-02-10 2:26 ` [PATCH v3 2/2] clk: rockchip: Add clock controller for the RV1103B Fabio Estevam
2026-02-23 14:19 ` [PATCH v3 1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support Fabio Estevam
@ 2026-03-02 12:01 ` Heiko Stuebner
2 siblings, 0 replies; 8+ messages in thread
From: Heiko Stuebner @ 2026-03-02 12:01 UTC (permalink / raw)
To: sboyd, Fabio Estevam
Cc: Heiko Stuebner, robh, krzk+dt, conor+dt, linux-clk, jonas,
devicetree, Fabio Estevam, Krzysztof Kozlowski
On Mon, 09 Feb 2026 23:26:19 -0300, Fabio Estevam wrote:
> Add support for the Rockchip RV1103B Clock and Reset Unit (CRU).
>
> The RV1103B CRU is compatible with the existing RV1126B binding.
> Add the compatible string to the schema and introduce the
> corresponding clock ID definitions.
>
>
> [...]
Applied, thanks!
[1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support
commit: 75d627e5571a5ef313f6f553b7749b124c923c3d
[2/2] clk: rockchip: Add clock controller for the RV1103B
commit: 3e65e426d4575a66a82928eb41b6d83f36e5ce9c
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support
2026-03-02 11:46 ` Fabio Estevam
@ 2026-03-02 12:01 ` Heiko Stuebner
0 siblings, 0 replies; 8+ messages in thread
From: Heiko Stuebner @ 2026-03-02 12:01 UTC (permalink / raw)
To: Fabio Estevam
Cc: sboyd, robh, krzk+dt, conor+dt, linux-clk, jonas, devicetree,
Fabio Estevam, Krzysztof Kozlowski
Hey Fabio,
Am Montag, 2. März 2026, 12:46:25 Mitteleuropäische Normalzeit schrieb Fabio Estevam:
> On Mon, Feb 23, 2026 at 11:21 AM Heiko Stübner <heiko@sntech.de> wrote:
>
> > I generally pick up Rockchip clock changes anyway and then
> > send PRs to the clock maintainers, so that'll work as always :-) .
>
> Please let me know if you are OK with the RV1103B clock and dts series.
just didn't get that in the list yet, but applied now :-)
Heiko
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-03-02 12:02 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-02-10 2:26 [PATCH v3 1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support Fabio Estevam
2026-02-10 2:26 ` [PATCH v3 2/2] clk: rockchip: Add clock controller for the RV1103B Fabio Estevam
2026-02-23 14:19 ` [PATCH v3 1/2] dt-bindings: clock: rockchip: Add RV1103B CRU support Fabio Estevam
2026-02-23 14:21 ` Heiko Stübner
2026-02-23 14:34 ` Fabio Estevam
2026-03-02 11:46 ` Fabio Estevam
2026-03-02 12:01 ` Heiko Stuebner
2026-03-02 12:01 ` Heiko Stuebner
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