From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C564C2459C9; Sun, 23 Nov 2025 13:23:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763904231; cv=none; b=mSDgEqNl4y0/R3ci+i1PkFlU5WN9i9E3kr5AbmoH4d4uDzRpbIMUX/XXVnyufmpc28oDF9y/O3HU+1cW0dXfIC/ht0fmCsJW5fVDf4RgY8N6iGYwe33MtlVIFQl9+EQouZra/GdDn5k1dQLLpD1t56jU5uU2NFGHjlDSeFy19XY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763904231; c=relaxed/simple; bh=ruU2XqxYr9I0zzUJNsj0Y8eMYouD+DIo4YNd1RLIF64=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=UreKaYhKnKDxoPHDrstIvv4ifKklpmTqPJfRx44jPVXqnVsHkmoJeuRASLyGHJccku56MPVp9bx5mu+9Mkq8JIEeZ7OkmSfrvcIdOq8IPvRytncEO7ZckP0UG8+93hSX0aJpGdRWV87qyxcUszrocPJHlKyqqAE6rflWI6lfVK8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=F+g+kpji; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F+g+kpji" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EEE2DC113D0; Sun, 23 Nov 2025 13:23:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763904230; bh=ruU2XqxYr9I0zzUJNsj0Y8eMYouD+DIo4YNd1RLIF64=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=F+g+kpjiIzs/pKfcDd/wvffApgKNWCiGXctGzQc9nd/gltexZuutgSyniL3D/wy5z u3o8EZuBT98dM48LkODmPq9zVQpFc9SMhmm9cV2te55EBgo3D+f9p6R4YGEQznBr0p s/rcJMDE85K6y2+76DRxM21ufU4TTPydLu1x9UqHJ7NYiMriotBHlaS+gy59kpIo/k 3230B/3/pyZBgYhS3eCzq+n9RUXlkLwz9xgXc6yD+Ov5RncTQoiKpZZ99UQJbJifKC std8XTYPUm2wVvz+54aiYceywrRq0Y5quR5/OHG7NsYOsuLH35e2eqe5U8n2lJwzsX zTs0IlFN8uYPA== Message-ID: <32ffb736-d060-4ae9-b4fb-b836a6c869e9@kernel.org> Date: Sun, 23 Nov 2025 14:23:45 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] dt-bindings: interrupt-controller: document RZ/{T2H,N2H} ICU To: Cosmin Tanislav , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org References: <20251121111423.1379395-1-cosmin-gabriel.tanislav.xa@renesas.com> <20251121111423.1379395-2-cosmin-gabriel.tanislav.xa@renesas.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 21/11/2025 12:14, Cosmin Tanislav wrote: > +properties: > + compatible: > + oneOf: > + - const: renesas,r9a09g077-icu # RZ/T2H > + > + - items: > + - enum: > + - renesas,r9a09g087-icu # RZ/N2H > + - const: renesas,r9a09g077-icu > + > + '#interrupt-cells': > + description: The first cell is the SPI number of the interrupt, as per user > + manual. The second cell is used to specify the flag. > + const: 2 > + > + '#address-cells': > + const: 0 > + > + interrupt-controller: true > + > + reg: > + items: > + - description: Non-safety registers (INTCPU0-13, IRQ0-13) > + - description: Safety registers (INTCPU14-15, IRQ14-15, SEI) reg is always the second property. Please follow DTS coding style. > + > + interrupts: > + items: > + - description: Software interrupt 0 > + - description: Software interrupt 1 > + - description: Software interrupt 2 > + - description: Software interrupt 3 > + - description: Software interrupt 4 > + - description: Software interrupt 5 > + - description: Software interrupt 6 > + - description: Software interrupt 7 > + - description: Software interrupt 8 > + - description: Software interrupt 9 > + - description: Software interrupt 10 > + - description: Software interrupt 11 > + - description: Software interrupt 12 > + - description: Software interrupt 13 > + - description: Software interrupt 14 > + - description: Software interrupt 15 > + - description: External pin interrupt 0 > + - description: External pin interrupt 1 > + - description: External pin interrupt 2 > + - description: External pin interrupt 3 > + - description: External pin interrupt 4 > + - description: External pin interrupt 5 > + - description: External pin interrupt 6 > + - description: External pin interrupt 7 > + - description: External pin interrupt 8 > + - description: External pin interrupt 9 > + - description: External pin interrupt 10 > + - description: External pin interrupt 11 > + - description: External pin interrupt 12 > + - description: External pin interrupt 13 > + - description: External pin interrupt 14 > + - description: External pin interrupt 15 > + - description: System error interrupt > + - description: Cortex-A55 error event 0 > + - description: Cortex-A55 error event 1 > + - description: Cortex-R52 CPU 0 error event 0 > + - description: Cortex-R52 CPU 0 error event 1 > + - description: Cortex-R52 CPU 1 error event 0 > + - description: Cortex-R52 CPU 1 error event 1 > + - description: Peripherals error event 0 > + - description: Peripherals error event 1 > + - description: DSMIF error event 0 > + - description: DSMIF error event 1 > + - description: ENCIF error event 0 > + - description: ENCIF error event 1 > + > + interrupt-names: > + items: > + - const: intcpu0 > + - const: intcpu1 > + - const: intcpu2 > + - const: intcpu3 > + - const: intcpu4 > + - const: intcpu5 > + - const: intcpu6 > + - const: intcpu7 > + - const: intcpu8 > + - const: intcpu9 > + - const: intcpu10 > + - const: intcpu11 > + - const: intcpu12 > + - const: intcpu13 > + - const: intcpu14 > + - const: intcpu15 > + - const: irq0 > + - const: irq1 > + - const: irq2 > + - const: irq3 > + - const: irq4 > + - const: irq5 > + - const: irq6 > + - const: irq7 > + - const: irq8 > + - const: irq9 > + - const: irq10 > + - const: irq11 > + - const: irq12 > + - const: irq13 > + - const: irq14 > + - const: irq15 > + - const: sei > + - const: ca55-err0 > + - const: ca55-err1 > + - const: cr520-err0 > + - const: cr520-err1 > + - const: cr521-err0 > + - const: cr521-err1 > + - const: peri-err0 > + - const: peri-err1 > + - const: dsmif-err0 > + - const: dsmif-err1 > + - const: encif-err0 > + - const: encif-err1 Why all the interrupt names have nothing in common with previous ICU (renesas,rzv2h-icu.yaml)? These names are supposed to share, not re-invent every time the name. Isn't external interrupt the same as GPIO interrupt? How do they differ for this particular device? And "Error interrupt to CA55" is "icu-error-ca55", but here THE SAME is called "ca55-err0"? No, please start using unified naming, not re-inventing this every time. Order also is supposed to follow older generation, so bindings share common parts. > + > + clocks: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - '#interrupt-cells' > + - '#address-cells' > + - interrupt-controller > + - interrupts > + - interrupt-names > + - clocks > + - power-domains Best regards, Krzysztof