From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: horms@verge.net.au, linux-renesas-soc@vger.kernel.org,
robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
devicetree@vger.kernel.org
Cc: magnus.damm@gmail.com, linux@arm.linux.org.uk,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 3/6] ARM: dts: r8a7794: add MSTP10 clocks
Date: Thu, 12 May 2016 23:46:30 +0300 [thread overview]
Message-ID: <3321354.LNTkVAhXvF@wasted.cogentembedded.com> (raw)
In-Reply-To: <2378837.cigT3tNQPe@wasted.cogentembedded.com>
Add MSTP10 clocks to the R8A7794 device tree.
This patch is based on the commit ee9141522dcf ("ARM: shmobile: r8a7791:
add MSTP10 support on DTSI").
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
Changes in version 3:
- refreshed the patch.
Changes in version 2:
- fixed the SoC model in the change log;
- added "the" article to the change log.
arch/arm/boot/dts/r8a7794.dtsi | 53 ++++++++++++++++++++++++++++++
include/dt-bindings/clock/r8a7794-clock.h | 28 +++++++++++++++
2 files changed, 81 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7794.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7794.dtsi
+++ renesas/arch/arm/boot/dts/r8a7794.dtsi
@@ -1235,6 +1235,59 @@
"gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
"i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
};
+ mstp10_clks: mstp10_clks@e6150998 {
+ compatible = "renesas,r8a7794-mstp-clocks",
+ "renesas,cpg-mstp-clocks";
+ reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+ clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+ <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+ <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+ <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7794_CLK_SCU_ALL>,
+ <&mstp10_clks R8A7794_CLK_SCU_ALL>;
+ #clock-cells = <1>;
+ clock-indices = <R8A7794_CLK_SSI_ALL
+ R8A7794_CLK_SSI9 R8A7794_CLK_SSI8
+ R8A7794_CLK_SSI7 R8A7794_CLK_SSI6
+ R8A7794_CLK_SSI5 R8A7794_CLK_SSI4
+ R8A7794_CLK_SSI3 R8A7794_CLK_SSI2
+ R8A7794_CLK_SSI1 R8A7794_CLK_SSI0
+ R8A7794_CLK_SCU_ALL
+ R8A7794_CLK_SCU_DVC1
+ R8A7794_CLK_SCU_DVC0
+ R8A7794_CLK_SCU_CTU1_MIX1
+ R8A7794_CLK_SCU_CTU0_MIX0
+ R8A7794_CLK_SCU_SRC9
+ R8A7794_CLK_SCU_SRC8
+ R8A7794_CLK_SCU_SRC7
+ R8A7794_CLK_SCU_SRC6
+ R8A7794_CLK_SCU_SRC5
+ R8A7794_CLK_SCU_SRC4
+ R8A7794_CLK_SCU_SRC3
+ R8A7794_CLK_SCU_SRC2
+ R8A7794_CLK_SCU_SRC1
+ R8A7794_CLK_SCU_SRC0>;
+ clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7",
+ "ssi6", "ssi5", "ssi4", "ssi3",
+ "ssi2", "ssi1", "ssi0",
+ "scu-all", "scu-dvc1", "scu-dvc0",
+ "scu-ctu1-mix1", "scu-ctu0-mix0",
+ "scu-src9", "scu-src8", "scu-src7",
+ "scu-src6", "scu-src5", "scu-src4",
+ "scu-src3", "scu-src2", "scu-src1",
+ "scu-src0";
+ };
mstp11_clks: mstp11_clks@e615099c {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
Index: renesas/include/dt-bindings/clock/r8a7794-clock.h
===================================================================
--- renesas.orig/include/dt-bindings/clock/r8a7794-clock.h
+++ renesas/include/dt-bindings/clock/r8a7794-clock.h
@@ -109,6 +109,34 @@
#define R8A7794_CLK_I2C1 30
#define R8A7794_CLK_I2C0 31
+/* MSTP10 */
+#define R8A7794_CLK_SSI_ALL 5
+#define R8A7794_CLK_SSI9 6
+#define R8A7794_CLK_SSI8 7
+#define R8A7794_CLK_SSI7 8
+#define R8A7794_CLK_SSI6 9
+#define R8A7794_CLK_SSI5 10
+#define R8A7794_CLK_SSI4 11
+#define R8A7794_CLK_SSI3 12
+#define R8A7794_CLK_SSI2 13
+#define R8A7794_CLK_SSI1 14
+#define R8A7794_CLK_SSI0 15
+#define R8A7794_CLK_SCU_ALL 17
+#define R8A7794_CLK_SCU_DVC1 18
+#define R8A7794_CLK_SCU_DVC0 19
+#define R8A7794_CLK_SCU_CTU1_MIX1 20
+#define R8A7794_CLK_SCU_CTU0_MIX0 21
+#define R8A7794_CLK_SCU_SRC9 22
+#define R8A7794_CLK_SCU_SRC8 23
+#define R8A7794_CLK_SCU_SRC7 24
+#define R8A7794_CLK_SCU_SRC6 25
+#define R8A7794_CLK_SCU_SRC5 26
+#define R8A7794_CLK_SCU_SRC4 27
+#define R8A7794_CLK_SCU_SRC3 28
+#define R8A7794_CLK_SCU_SRC2 29
+#define R8A7794_CLK_SCU_SRC1 30
+#define R8A7794_CLK_SCU_SRC0 31
+
/* MSTP11 */
#define R8A7794_CLK_SCIFA3 6
#define R8A7794_CLK_SCIFA4 7
next prev parent reply other threads:[~2016-05-12 20:46 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-12 20:38 [PATCH v3 0/6] Add R8A7794/SILK sound DT support Sergei Shtylyov
2016-05-12 20:40 ` [PATCH v3 1/6] ARM: dts: r8a7794: add audio clocks Sergei Shtylyov
2016-05-12 20:45 ` [PATCH v3 2/6] ARM: dts: r8a7794: add MSTP5 clocks Sergei Shtylyov
[not found] ` <1576909.nm8MtQ2Ln5-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org>
2016-05-19 16:25 ` Geert Uytterhoeven
2016-05-19 17:30 ` Sergei Shtylyov
2016-05-20 4:20 ` Simon Horman
2016-05-12 20:46 ` Sergei Shtylyov [this message]
2016-05-19 16:44 ` [PATCH v3 3/6] ARM: dts: r8a7794: add MSTP10 clocks Geert Uytterhoeven
2016-05-19 17:37 ` Sergei Shtylyov
2016-05-19 17:41 ` Geert Uytterhoeven
2016-05-19 18:36 ` Sergei Shtylyov
2016-05-20 4:22 ` Simon Horman
2016-05-12 20:49 ` [PATCH v3 5/6] ARM: dts: r8a7794: add sound support Sergei Shtylyov
2016-05-13 6:13 ` Geert Uytterhoeven
[not found] ` <2378837.cigT3tNQPe-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org>
2016-05-12 20:47 ` [PATCH v3 4/6] ARM: dts: r8a7794: add Audio-DMAC support Sergei Shtylyov
2016-05-13 6:12 ` Geert Uytterhoeven
2016-05-12 20:51 ` [PATCH v3 6/6] ARM: dts: silk: add sound support Sergei Shtylyov
2016-05-12 21:16 ` [PATCH v3 0/6] Add R8A7794/SILK sound DT support Sergei Shtylyov
2016-06-06 18:11 ` Sergei Shtylyov
[not found] ` <b77ad169-c9d1-4d67-0973-fc9639ddb613-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
2016-06-07 0:37 ` Simon Horman
2016-06-07 10:31 ` Sergei Shtylyov
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