From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tomasz Figa Subject: Re: [PATCH 6/7] clk/samsung: add support for pll2650xx Date: Wed, 08 Jan 2014 01:37:27 +0100 Message-ID: <3338407.XGYaxCsdnx@flatron> References: <1386345391-23482-1-git-send-email-rahul.sharma@samsung.com> <1419145.DZQg0ZkHVU@amdc1227> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Return-path: In-Reply-To: Sender: linux-samsung-soc-owner@vger.kernel.org To: Rahul Sharma Cc: Tomasz Figa , Rahul Sharma , linux-samsung-soc , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Mike Turquette , Kukjin Kim , Thomas Abraham , sunil joshi , PANKAJ KUMAR DUBEY , Young-Gun Jang , Arun Kumar List-Id: devicetree@vger.kernel.org On Monday 06 of January 2014 17:14:48 Rahul Sharma wrote: > Hi Tomasz, > > On 19 December 2013 17:15, Tomasz Figa wrote: > > Hi Rahul, > > > > On Friday 06 of December 2013 21:26:30 Rahul Sharma wrote: > >> Add support for pll2650xx in samsung pll file. This pll variant > >> is close to pll36xx but uses CON2 registers instead of CON1. > > > > If the ops are otherwise idential, why not reuse the ops for pll36xx > > and use CON1 or CON2 register conditionally based on pll->type field? > > (Just as it is already done for pll4600, 4650 and 4650c.) > > > > I verified the difference and found that pll2650xx is fairly > different in terms of > Bit Fields, Con2 register, and additional PLL config bits than pll36xx. Due to > this, I have to add lot of if-else code based on pll type which > doesn't looks clean. Fair enough. Best regards, Tomasz