* [PATCH v15 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC
2020-11-05 5:49 [PATCH v15 0/2] pwm: intel: Add PWM driver for a new SoC Rahul Tanwar
@ 2020-11-05 5:49 ` Rahul Tanwar
2020-11-05 5:49 ` [PATCH v15 2/2] Add PWM fan controller driver for " Rahul Tanwar
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Rahul Tanwar @ 2020-11-05 5:49 UTC (permalink / raw)
To: u.kleine-koenig, linux-pwm, lee.jones
Cc: thierry.reding, p.zabel, robh+dt, linux-kernel, devicetree,
andriy.shevchenko, songjun.Wu, cheol.yong.kim, qi-ming.wu,
rahul.tanwar.linux, Rahul Tanwar
Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
which is only used to control the fan attached to the system. This
PWM controller does not have any other consumer other than fan.
Add DT bindings documentation for this PWM fan controller.
Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 44 ++++++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index 000000000000..11a606536169
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+ - Rahul Tanwar <rtanwar@maxlinear.com>
+
+properties:
+ compatible:
+ const: intel,lgm-pwm
+
+ reg:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ pwm: pwm@e0d00000 {
+ compatible = "intel,lgm-pwm";
+ reg = <0xe0d00000 0x30>;
+ #pwm-cells = <2>;
+ clocks = <&cgu0 126>;
+ resets = <&rcu0 0x30 21>;
+ };
--
2.11.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v15 2/2] Add PWM fan controller driver for LGM SoC
2020-11-05 5:49 [PATCH v15 0/2] pwm: intel: Add PWM driver for a new SoC Rahul Tanwar
2020-11-05 5:49 ` [PATCH v15 1/2] Add DT bindings YAML schema for PWM fan controller of LGM SoC Rahul Tanwar
@ 2020-11-05 5:49 ` Rahul Tanwar
2020-11-11 21:01 ` Uwe Kleine-König
2020-11-11 20:40 ` [PATCH v15 0/2] pwm: intel: Add PWM driver for a new SoC Thierry Reding
2020-11-11 21:14 ` Thierry Reding
3 siblings, 1 reply; 6+ messages in thread
From: Rahul Tanwar @ 2020-11-05 5:49 UTC (permalink / raw)
To: u.kleine-koenig, linux-pwm, lee.jones
Cc: thierry.reding, p.zabel, robh+dt, linux-kernel, devicetree,
andriy.shevchenko, songjun.Wu, cheol.yong.kim, qi-ming.wu,
rahul.tanwar.linux, Rahul Tanwar
Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
This PWM controller does not have any other consumer, it is a
dedicated PWM controller for fan attached to the system. Add
driver for this PWM fan controller.
Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
---
drivers/pwm/Kconfig | 11 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-intel-lgm.c | 244 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 256 insertions(+)
create mode 100644 drivers/pwm/pwm-intel-lgm.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 63be5362fd3a..7218bf3665bc 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -232,6 +232,17 @@ config PWM_IMX_TPM
To compile this driver as a module, choose M here: the module
will be called pwm-imx-tpm.
+config PWM_INTEL_LGM
+ tristate "Intel LGM PWM support"
+ depends on HAS_IOMEM
+ depends on (OF && X86) || COMPILE_TEST
+ select REGMAP_MMIO
+ help
+ Generic PWM fan controller driver for LGM SoC.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-intel-lgm.
+
config PWM_IQS620A
tristate "Azoteq IQS620A PWM support"
depends on MFD_IQS62X || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index cbdcd55d69ee..71beaff894c1 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_IMG) += pwm-img.o
obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
obj-$(CONFIG_PWM_IMX27) += pwm-imx27.o
obj-$(CONFIG_PWM_IMX_TPM) += pwm-imx-tpm.o
+obj-$(CONFIG_PWM_INTEL_LGM) += pwm-intel-lgm.o
obj-$(CONFIG_PWM_IQS620A) += pwm-iqs620a.o
obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
obj-$(CONFIG_PWM_LP3943) += pwm-lp3943.o
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
new file mode 100644
index 000000000000..e9e54dda07aa
--- /dev/null
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * Limitations:
+ * - The hardware supports fixed period & configures only 2-wire mode.
+ * - Supports normal polarity. Does not support changing polarity.
+ * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
+ * keep track of running period.
+ * - When duty cycle is changed, PWM output may be a mix of previous setting
+ * and new setting for the first period. From second period, the output is
+ * based on new setting.
+ * - It is a dedicated PWM fan controller. There are no other consumers for
+ * this PWM controller.
+ */
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/mod_devicetable.h>
+#include <linux/pwm.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define LGM_PWM_FAN_CON0 0x0
+#define LGM_PWM_FAN_EN_EN BIT(0)
+#define LGM_PWM_FAN_EN_DIS 0x0
+#define LGM_PWM_FAN_EN_MSK BIT(0)
+#define LGM_PWM_FAN_MODE_2WIRE 0x0
+#define LGM_PWM_FAN_MODE_MSK BIT(1)
+#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
+
+#define LGM_PWM_FAN_CON1 0x4
+#define LGM_PWM_FAN_MAX_RPM_MSK GENMASK(15, 0)
+
+#define LGM_PWM_MAX_RPM (BIT(16) - 1)
+#define LGM_PWM_DEFAULT_RPM 4000
+#define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
+
+#define LGM_PWM_DC_BITS 8
+
+#define LGM_PWM_PERIOD_2WIRE_NS (40 * NSEC_PER_MSEC)
+
+struct lgm_pwm_chip {
+ struct pwm_chip chip;
+ struct regmap *regmap;
+ u32 period;
+};
+
+static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
+{
+ return container_of(chip, struct lgm_pwm_chip, chip);
+}
+
+static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
+{
+ struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+ struct regmap *regmap = pc->regmap;
+
+ return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
+ enable ? LGM_PWM_FAN_EN_EN : LGM_PWM_FAN_EN_DIS);
+}
+
+static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+ u32 duty_cycle, val;
+ int ret;
+
+ /* The hardware only supports normal polarity and fixed period. */
+ if (state->polarity != PWM_POLARITY_NORMAL || state->period < pc->period)
+ return -EINVAL;
+
+ if (!state->enabled)
+ return lgm_pwm_enable(chip, 0);
+
+ duty_cycle = min_t(u64, state->duty_cycle, pc->period);
+ val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;
+
+ ret = regmap_update_bits(pc->regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_DC_MSK,
+ FIELD_PREP(LGM_PWM_FAN_DC_MSK, val));
+ if (ret)
+ return ret;
+
+ return lgm_pwm_enable(chip, 1);
+}
+
+static void lgm_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
+ u32 duty, val;
+
+ state->enabled = regmap_test_bits(pc->regmap, LGM_PWM_FAN_CON0,
+ LGM_PWM_FAN_EN_EN);
+ state->polarity = PWM_POLARITY_NORMAL;
+ state->period = pc->period; /* fixed period */
+
+ regmap_read(pc->regmap, LGM_PWM_FAN_CON0, &val);
+ duty = FIELD_GET(LGM_PWM_FAN_DC_MSK, val);
+ state->duty_cycle = DIV_ROUND_UP(duty * pc->period, LGM_PWM_MAX_DUTY_CYCLE);
+}
+
+static const struct pwm_ops lgm_pwm_ops = {
+ .get_state = lgm_pwm_get_state,
+ .apply = lgm_pwm_apply,
+ .owner = THIS_MODULE,
+};
+
+static void lgm_pwm_init(struct lgm_pwm_chip *pc)
+{
+ struct regmap *regmap = pc->regmap;
+ u32 con0_val;
+
+ con0_val = FIELD_PREP(LGM_PWM_FAN_MODE_MSK, LGM_PWM_FAN_MODE_2WIRE);
+ pc->period = LGM_PWM_PERIOD_2WIRE_NS;
+ regmap_update_bits(regmap, LGM_PWM_FAN_CON1, LGM_PWM_FAN_MAX_RPM_MSK,
+ LGM_PWM_DEFAULT_RPM);
+ regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_MODE_MSK,
+ con0_val);
+}
+
+static const struct regmap_config lgm_pwm_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+};
+
+static void lgm_clk_release(void *data)
+{
+ struct clk *clk = data;
+
+ clk_disable_unprepare(clk);
+}
+
+static int lgm_clk_enable(struct device *dev, struct clk *clk)
+{
+ int ret;
+
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ return ret;
+
+ return devm_add_action_or_reset(dev, lgm_clk_release, clk);
+}
+
+static void lgm_reset_control_release(void *data)
+{
+ struct reset_control *rst = data;
+
+ reset_control_assert(rst);
+}
+
+static int lgm_reset_control_deassert(struct device *dev, struct reset_control *rst)
+{
+ int ret;
+
+ ret = reset_control_deassert(rst);
+ if (ret)
+ return ret;
+
+ return devm_add_action_or_reset(dev, lgm_reset_control_release, rst);
+}
+
+static int lgm_pwm_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct reset_control *rst;
+ struct lgm_pwm_chip *pc;
+ void __iomem *io_base;
+ struct clk *clk;
+ int ret;
+
+ pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
+ if (!pc)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, pc);
+
+ io_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(io_base))
+ return PTR_ERR(io_base);
+
+ pc->regmap = devm_regmap_init_mmio(dev, io_base, &lgm_pwm_regmap_config);
+ if (IS_ERR(pc->regmap))
+ return dev_err_probe(dev, PTR_ERR(pc->regmap),
+ "failed to init register map\n");
+
+ clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n");
+
+ ret = lgm_clk_enable(dev, clk);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to enable clock\n");
+
+ rst = devm_reset_control_get_exclusive(dev, NULL);
+ if (IS_ERR(rst))
+ return dev_err_probe(dev, PTR_ERR(rst),
+ "failed to get reset control\n");
+
+ ret = lgm_reset_control_deassert(dev, rst);
+ if (ret)
+ return dev_err_probe(dev, ret, "cannot deassert reset control\n");
+
+ pc->chip.dev = dev;
+ pc->chip.ops = &lgm_pwm_ops;
+ pc->chip.npwm = 1;
+ pc->chip.base = -1;
+
+ lgm_pwm_init(pc);
+
+ ret = pwmchip_add(&pc->chip);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to add PWM chip\n");
+
+ return 0;
+}
+
+static int lgm_pwm_remove(struct platform_device *pdev)
+{
+ struct lgm_pwm_chip *pc = platform_get_drvdata(pdev);
+
+ return pwmchip_remove(&pc->chip);
+}
+
+static const struct of_device_id lgm_pwm_of_match[] = {
+ { .compatible = "intel,lgm-pwm" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, lgm_pwm_of_match);
+
+static struct platform_driver lgm_pwm_driver = {
+ .driver = {
+ .name = "intel-pwm",
+ .of_match_table = lgm_pwm_of_match,
+ },
+ .probe = lgm_pwm_probe,
+ .remove = lgm_pwm_remove,
+};
+module_platform_driver(lgm_pwm_driver);
+
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v15 0/2] pwm: intel: Add PWM driver for a new SoC
2020-11-05 5:49 [PATCH v15 0/2] pwm: intel: Add PWM driver for a new SoC Rahul Tanwar
` (2 preceding siblings ...)
2020-11-11 20:40 ` [PATCH v15 0/2] pwm: intel: Add PWM driver for a new SoC Thierry Reding
@ 2020-11-11 21:14 ` Thierry Reding
3 siblings, 0 replies; 6+ messages in thread
From: Thierry Reding @ 2020-11-11 21:14 UTC (permalink / raw)
To: Rahul Tanwar
Cc: u.kleine-koenig, linux-pwm, lee.jones, p.zabel, robh+dt,
linux-kernel, devicetree, andriy.shevchenko, songjun.Wu,
cheol.yong.kim, qi-ming.wu, rahul.tanwar.linux
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On Thu, Nov 05, 2020 at 01:49:38PM +0800, Rahul Tanwar wrote:
> Patch 1 adds dt binding document in YAML format.
> Patch 2 add PWM fan controller driver for LGM SoC.
>
> v15:
> - Rebase to latest linux 5.10-rc2
>
> v14:
> - Address below review concerns from Uwe Kleine-K?nig.
> * Add limitations info about fixed 2-wire mode support.
> * Rename clk/reset _disable function names to _release.
> * Remove clk & rst from driver data structure. Instead
> use them as arguments.
> * Add pwm_chip.base = -1.
> - Resolve missing MODULE_LICENSE warning.
>
> v13:
> - Address below review concerns (Philipp Zabel)
> * Make unnecessary 2 line comment as 1 line comment.
> * Move reset_deassert at the last after clk_enable.
> * Remove unnecessary return ret statement from .remove()
> - Move platform_set_drvdata() at the top of probe.
>
> v12:
> - Rebase to linux 5.9-rc4
> - Add Reviewed-by tags from Andy Shevchenko & Rob Herring.
>
> v11:
> - Address below review concerns (Andy Shevchenko)
> * Fix a issue with dev_err_probe() usage & improve the usage.
> * Fix & improve a ordering issue with clk_enable/disable &
> reset_control assert/deassert.
>
> v10:
> - Removed unused of_device.h and added platform_device.h
> & mod_devicetable.h
>
> v9:
> - Address code quality related review concerns (Andy Shevchenko)
> - Use devm_add_action_or_reset() instead of explicit unwind calls.
>
> v8:
> - Remove fan related optional properties usage, keep
> them as default. If needed, change pwm-fan driver
> separately in future to add them as generic properties.
>
> v7:
> - Address code quality related review concerns.
> - Rename fan related property to pwm-*.
> - Fix one make dt_binding_check reported error.
>
> v6:
> - Readjust .apply op as per review feedback.
> - Add back pwm-cells property to resolve make dt_binding_check error.
> pwm-cells is a required property for PWM driver.
> - Add back fan related optional properties.
>
> v5:
> - Address below review concerns from Uwe Kleine-K?nig.
> * Improve comments about Limitations.
> * Use return value of regmap_update_bits if container function returns
> error code.
> * Modify .apply op to have strict checking for fixed period supported
> by PWM HW.
> * Use u64 as type when use min_t for duty_cycle.
> * Add reset_control_assert() in failure case in probe where it was missing
> earlier.
> - Remove fan specific optional properties from pwm dt binding document (Rob Herring)
>
> v4:
> - Address below review concerns from Uwe Kleine-K?nig.
> * Improve notes and limitations comments.
> * Add common prefixes for all #defines.
> * Modify/Improve logic in .apply & .get_state ops as advised.
> * Skip error messages in probe when error is -EPROBE_DEFER.
> * Add dependencies in Kconfig (OF & HAS_IOMEM) and add select REGMAP_MMIO.
> * Address other code quality related review concerns.
> - Fix make dt_binding_check reported error in YAML file.
>
> v3:
> - Address below review concerns from Uwe Kleine-K?nig.
> * Remove fan rpm calibration task from the driver.
> * Modify apply op as per the review feedback.
> * Add roundup & round down where necessary.
> * Address other misc code quality related review concerns.
> * Use devm_reset_control_get_exclusive(). (Philipp Zabel)
> * Improve dt binding document.
>
> v2:
> - Address below review concerns from Uwe Kleine-K?nig.
> * Add notes and limitations about PWM HW.
> * Rename all functions and structure to lgm_pwm_*
> * Readjust space aligninment in structure fields to single space.
> * Switch to using apply instead of config/enable/disable.
> * Address other code quality related concerns.
> * Rebase to 5.8-rc1.
> - Address review concerns in dt binding YAML from Rob Herring.
>
> v1:
> - Initial version.
>
>
> Rahul Tanwar (2):
> Add DT bindings YAML schema for PWM fan controller of LGM SoC
> Add PWM fan controller driver for LGM SoC
>
> .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 44 ++++
> drivers/pwm/Kconfig | 11 +
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-intel-lgm.c | 244 +++++++++++++++++++++
> 4 files changed, 300 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml
> create mode 100644 drivers/pwm/pwm-intel-lgm.c
Both patches applied, thanks.
Thierry
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^ permalink raw reply [flat|nested] 6+ messages in thread