* [PATCH 1/6] arm64: dts: rockchip: move cpu_thermal node to the correct position
2025-09-25 9:29 [PATCH 0/6] Some cleanups and addition of another Qnap TSx33 device Heiko Stuebner
@ 2025-09-25 9:29 ` Heiko Stuebner
2025-09-25 9:29 ` [PATCH 2/6] arm64: dts: rockchip: Fix the 1Ghz ethernet on Qnap TS433 Heiko Stuebner
` (4 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Heiko Stuebner @ 2025-09-25 9:29 UTC (permalink / raw)
To: heiko
Cc: robh, krzk+dt, conor+dt, ukleinek, devicetree, linux-kernel,
linux-arm-kernel, linux-rockchip
The &cpu_thermal node was added at the wrong position, move it to
the correctly sorted one.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
.../boot/dts/rockchip/rk3568-qnap-ts433.dts | 96 +++++++++----------
1 file changed, 48 insertions(+), 48 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
index 6ae4316761c4..5656554ca284 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
@@ -196,6 +196,54 @@ &cpu3 {
cpu-supply = <&vdd_cpu>;
};
+/*
+ * The MCU can provide system temperature too, but only by polling and of
+ * course also cannot set trip points. So attach to the cpu thermal-zone
+ * instead to control the fan.
+ */
+&cpu_thermal {
+ trips {
+ case_fan0: case-fan0 {
+ hysteresis = <2000>;
+ temperature = <35000>;
+ type = "active";
+ };
+
+ case_fan1: case-fan1 {
+ hysteresis = <2000>;
+ temperature = <45000>;
+ type = "active";
+ };
+
+ case_fan2: case-fan2 {
+ hysteresis = <2000>;
+ temperature = <65000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ /*
+ * Always provide some air movement, due to small case
+ * full of harddrives.
+ */
+ map1 {
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ trip = <&case_fan0>;
+ };
+
+ map2 {
+ cooling-device = <&fan 2 3>;
+ trip = <&case_fan1>;
+ };
+
+ map3 {
+ cooling-device = <&fan 4 THERMAL_NO_LIMIT>;
+ trip = <&case_fan2>;
+ };
+ };
+};
+
&gmac0 {
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
@@ -492,54 +540,6 @@ rgmii_phy0: ethernet-phy@3 {
};
};
-/*
- * The MCU can provide system temperature too, but only by polling and of
- * course also cannot set trip points. So attach to the cpu thermal-zone
- * instead to control the fan.
- */
-&cpu_thermal {
- trips {
- case_fan0: case-fan0 {
- hysteresis = <2000>;
- temperature = <35000>;
- type = "active";
- };
-
- case_fan1: case-fan1 {
- hysteresis = <2000>;
- temperature = <45000>;
- type = "active";
- };
-
- case_fan2: case-fan2 {
- hysteresis = <2000>;
- temperature = <65000>;
- type = "active";
- };
- };
-
- cooling-maps {
- /*
- * Always provide some air movement, due to small case
- * full of harddrives.
- */
- map1 {
- cooling-device = <&fan THERMAL_NO_LIMIT 1>;
- trip = <&case_fan0>;
- };
-
- map2 {
- cooling-device = <&fan 2 3>;
- trip = <&case_fan1>;
- };
-
- map3 {
- cooling-device = <&fan 4 THERMAL_NO_LIMIT>;
- trip = <&case_fan2>;
- };
- };
-};
-
&pcie30phy {
data-lanes = <1 2>;
status = "okay";
--
2.47.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 2/6] arm64: dts: rockchip: Fix the 1Ghz ethernet on Qnap TS433
2025-09-25 9:29 [PATCH 0/6] Some cleanups and addition of another Qnap TSx33 device Heiko Stuebner
2025-09-25 9:29 ` [PATCH 1/6] arm64: dts: rockchip: move cpu_thermal node to the correct position Heiko Stuebner
@ 2025-09-25 9:29 ` Heiko Stuebner
2025-09-25 16:58 ` Jonas Karlman
2025-09-25 9:29 ` [PATCH 3/6] arm64: dts: rockchip: describe mcu eeprom cells on rk3568-ts433 Heiko Stuebner
` (3 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Heiko Stuebner @ 2025-09-25 9:29 UTC (permalink / raw)
To: heiko
Cc: robh, krzk+dt, conor+dt, ukleinek, devicetree, linux-kernel,
linux-arm-kernel, linux-rockchip, Andrew Lunn
While I want to remember that the dwmac on the TS433 was working at some
point, it seems I had my network always connected to the 2.5G nic after
that "point". And testing now revealed that the gmac does not actually
manages to transfer data.
Currently the gmac is set to rgmii-id with no rx-/tx-delay values set
which makes the driver use default values. Setting the delays to 0
also does not provide a working interface.
The vendor kernel is running with phy-mode set to rgmii and delays of
tx_delay = 0x3c, rx_delay = 0x2f
As Andrew points out often, those delay values "are magic" and rgmii-id
should definitly be used "with small values" for delays, if really needed.
The Rockchip vendor-kernel actually contains additional code in the dwmac
driver to use the loopback function of a phy to find a window of usable
delay values. Code can be found for example on [0] and the process is
described in a document called "Rockchip GMAC RGMII Delayline Guide"
which has made its way onto the internet in a lot of places [1].
So I used this process, with the interface set to rgmii-id to get values
for this mode, which are in face lower than the ones for rgmii with
tx_delay = 0x21, rx_delay = 0x15
and results in a working interface on the dwmac.
[0] https://github.com/armbian/linux-rockchip/blob/rk-6.1-rkr6.1/drivers/net/ethernet/stmicro/stmmac/dwmac-rk-tool.c
[1] https://gitlab.com/firefly-linux/docs/-/blob/rk356x/firefly/Common/GMAC/Rockchip_Developer_Guide_Linux_GMAC_RGMII_Delayline_EN.pdf
Cc: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
index 5656554ca284..e8af92a011d6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
@@ -257,6 +257,8 @@ &gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
+ rx_delay = <0x15>;
+ tx_delay = <0x21>;
status = "okay";
};
--
2.47.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 2/6] arm64: dts: rockchip: Fix the 1Ghz ethernet on Qnap TS433
2025-09-25 9:29 ` [PATCH 2/6] arm64: dts: rockchip: Fix the 1Ghz ethernet on Qnap TS433 Heiko Stuebner
@ 2025-09-25 16:58 ` Jonas Karlman
2025-09-25 17:11 ` Andrew Lunn
0 siblings, 1 reply; 11+ messages in thread
From: Jonas Karlman @ 2025-09-25 16:58 UTC (permalink / raw)
To: Heiko Stuebner, Andrew Lunn
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
ukleinek@debian.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
Hi Heiko,
On 9/25/2025 11:29 AM, Heiko Stuebner wrote:
> While I want to remember that the dwmac on the TS433 was working at some
> point, it seems I had my network always connected to the 2.5G nic after
> that "point". And testing now revealed that the gmac does not actually
> manages to transfer data.
>
> Currently the gmac is set to rgmii-id with no rx-/tx-delay values set
> which makes the driver use default values. Setting the delays to 0
> also does not provide a working interface.
>
> The vendor kernel is running with phy-mode set to rgmii and delays of
> tx_delay = 0x3c, rx_delay = 0x2f
>
> As Andrew points out often, those delay values "are magic" and rgmii-id
> should definitly be used "with small values" for delays, if really needed.
>
> The Rockchip vendor-kernel actually contains additional code in the dwmac
> driver to use the loopback function of a phy to find a window of usable
> delay values. Code can be found for example on [0] and the process is
> described in a document called "Rockchip GMAC RGMII Delayline Guide"
> which has made its way onto the internet in a lot of places [1].
>
> So I used this process, with the interface set to rgmii-id to get values
> for this mode, which are in face lower than the ones for rgmii with
> tx_delay = 0x21, rx_delay = 0x15
> and results in a working interface on the dwmac.
>
> [0] https://github.com/armbian/linux-rockchip/blob/rk-6.1-rkr6.1/drivers/net/ethernet/stmicro/stmmac/dwmac-rk-tool.c
> [1] https://gitlab.com/firefly-linux/docs/-/blob/rk356x/firefly/Common/GMAC/Rockchip_Developer_Guide_Linux_GMAC_RGMII_Delayline_EN.pdf
>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
> index 5656554ca284..e8af92a011d6 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
> @@ -257,6 +257,8 @@ &gmac0_tx_bus2
> &gmac0_rx_bus2
> &gmac0_rgmii_clk
> &gmac0_rgmii_bus>;
> + rx_delay = <0x15>;
> + tx_delay = <0x21>;
I do not understand why defining rx/tx_delay would change anything.
Setting these should currently not have any effect on the driver code
when phy-mode=rgmii-id is used, see below (next-20250924, dwmac-rk.c):
switch (bsp_priv->phy_iface) {
case PHY_INTERFACE_MODE_RGMII:
dev_info(dev, "init for RGMII\n");
bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
bsp_priv->rx_delay);
break;
case PHY_INTERFACE_MODE_RGMII_ID:
dev_info(dev, "init for RGMII_ID\n");
bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
break;
I have played around with a few patches that changes this and apply the
rx/tx_delay for rgmii-id modes (both Linux and U-Boot), see top of [2]
for Linux patches. Will try to get them on ML in a few days.
Currently, rk3588-firefly-itx-3588j.dts is the only RK board that define
rx/tx_delay and use rgmii-id mode, would be good to not define any more
rgmii-id + rx/tx_delay combo to reduce impact of a possible future
driver change.
[2] https://github.com/Kwiboo/linux-rockchip/commits/next-20250924-rk3528/
Regards,
Jonas
> status = "okay";
> };
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 2/6] arm64: dts: rockchip: Fix the 1Ghz ethernet on Qnap TS433
2025-09-25 16:58 ` Jonas Karlman
@ 2025-09-25 17:11 ` Andrew Lunn
2025-11-12 21:33 ` Heiko Stübner
0 siblings, 1 reply; 11+ messages in thread
From: Andrew Lunn @ 2025-09-25 17:11 UTC (permalink / raw)
To: Jonas Karlman
Cc: Heiko Stuebner, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, ukleinek@debian.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
On Thu, Sep 25, 2025 at 06:58:06PM +0200, Jonas Karlman wrote:
> Hi Heiko,
>
> On 9/25/2025 11:29 AM, Heiko Stuebner wrote:
> > While I want to remember that the dwmac on the TS433 was working at some
> > point, it seems I had my network always connected to the 2.5G nic after
> > that "point". And testing now revealed that the gmac does not actually
> > manages to transfer data.
> >
> > Currently the gmac is set to rgmii-id with no rx-/tx-delay values set
> > which makes the driver use default values. Setting the delays to 0
> > also does not provide a working interface.
> >
> > The vendor kernel is running with phy-mode set to rgmii and delays of
> > tx_delay = 0x3c, rx_delay = 0x2f
> >
> > As Andrew points out often, those delay values "are magic" and rgmii-id
> > should definitly be used "with small values" for delays, if really needed.
> >
> > The Rockchip vendor-kernel actually contains additional code in the dwmac
> > driver to use the loopback function of a phy to find a window of usable
> > delay values. Code can be found for example on [0] and the process is
> > described in a document called "Rockchip GMAC RGMII Delayline Guide"
> > which has made its way onto the internet in a lot of places [1].
> >
> > So I used this process, with the interface set to rgmii-id to get values
> > for this mode, which are in face lower than the ones for rgmii with
> > tx_delay = 0x21, rx_delay = 0x15
> > and results in a working interface on the dwmac.
> >
> > [0] https://github.com/armbian/linux-rockchip/blob/rk-6.1-rkr6.1/drivers/net/ethernet/stmicro/stmmac/dwmac-rk-tool.c
> > [1] https://gitlab.com/firefly-linux/docs/-/blob/rk356x/firefly/Common/GMAC/Rockchip_Developer_Guide_Linux_GMAC_RGMII_Delayline_EN.pdf
> >
> > Cc: Andrew Lunn <andrew@lunn.ch>
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > ---
> > arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
> > index 5656554ca284..e8af92a011d6 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
> > @@ -257,6 +257,8 @@ &gmac0_tx_bus2
> > &gmac0_rx_bus2
> > &gmac0_rgmii_clk
> > &gmac0_rgmii_bus>;
> > + rx_delay = <0x15>;
> > + tx_delay = <0x21>;
>
> I do not understand why defining rx/tx_delay would change anything.
I was also wondering why these two properties are added but no change
to phy-mode.
>
> Setting these should currently not have any effect on the driver code
> when phy-mode=rgmii-id is used, see below (next-20250924, dwmac-rk.c):
>
>
> switch (bsp_priv->phy_iface) {
> case PHY_INTERFACE_MODE_RGMII:
> dev_info(dev, "init for RGMII\n");
> bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
> bsp_priv->rx_delay);
> break;
> case PHY_INTERFACE_MODE_RGMII_ID:
> dev_info(dev, "init for RGMII_ID\n");
> bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
> break;
And this explains it, thanks.
> I have played around with a few patches that changes this and apply the
> rx/tx_delay for rgmii-id modes (both Linux and U-Boot), see top of [2]
> for Linux patches. Will try to get them on ML in a few days.
We should not really be expanding the use of rx_delay and
tx_delay. The standardized properties {tx|rx}-internal-delay-ps should
be used.
Andrew
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 2/6] arm64: dts: rockchip: Fix the 1Ghz ethernet on Qnap TS433
2025-09-25 17:11 ` Andrew Lunn
@ 2025-11-12 21:33 ` Heiko Stübner
0 siblings, 0 replies; 11+ messages in thread
From: Heiko Stübner @ 2025-11-12 21:33 UTC (permalink / raw)
To: Jonas Karlman, Andrew Lunn
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
ukleinek@debian.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
Am Donnerstag, 25. September 2025, 19:11:29 Mitteleuropäische Normalzeit schrieb Andrew Lunn:
> On Thu, Sep 25, 2025 at 06:58:06PM +0200, Jonas Karlman wrote:
> > Hi Heiko,
> >
> > On 9/25/2025 11:29 AM, Heiko Stuebner wrote:
> > > While I want to remember that the dwmac on the TS433 was working at some
> > > point, it seems I had my network always connected to the 2.5G nic after
> > > that "point". And testing now revealed that the gmac does not actually
> > > manages to transfer data.
> > >
> > > Currently the gmac is set to rgmii-id with no rx-/tx-delay values set
> > > which makes the driver use default values. Setting the delays to 0
> > > also does not provide a working interface.
> > >
> > > The vendor kernel is running with phy-mode set to rgmii and delays of
> > > tx_delay = 0x3c, rx_delay = 0x2f
> > >
> > > As Andrew points out often, those delay values "are magic" and rgmii-id
> > > should definitly be used "with small values" for delays, if really needed.
> > >
> > > The Rockchip vendor-kernel actually contains additional code in the dwmac
> > > driver to use the loopback function of a phy to find a window of usable
> > > delay values. Code can be found for example on [0] and the process is
> > > described in a document called "Rockchip GMAC RGMII Delayline Guide"
> > > which has made its way onto the internet in a lot of places [1].
> > >
> > > So I used this process, with the interface set to rgmii-id to get values
> > > for this mode, which are in face lower than the ones for rgmii with
> > > tx_delay = 0x21, rx_delay = 0x15
> > > and results in a working interface on the dwmac.
> > >
> > > [0] https://github.com/armbian/linux-rockchip/blob/rk-6.1-rkr6.1/drivers/net/ethernet/stmicro/stmmac/dwmac-rk-tool.c
> > > [1] https://gitlab.com/firefly-linux/docs/-/blob/rk356x/firefly/Common/GMAC/Rockchip_Developer_Guide_Linux_GMAC_RGMII_Delayline_EN.pdf
> > >
> > > Cc: Andrew Lunn <andrew@lunn.ch>
> > > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > > ---
> > > arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts | 2 ++
> > > 1 file changed, 2 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
> > > index 5656554ca284..e8af92a011d6 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
> > > @@ -257,6 +257,8 @@ &gmac0_tx_bus2
> > > &gmac0_rx_bus2
> > > &gmac0_rgmii_clk
> > > &gmac0_rgmii_bus>;
> > > + rx_delay = <0x15>;
> > > + tx_delay = <0x21>;
> >
> > I do not understand why defining rx/tx_delay would change anything.
>
> I was also wondering why these two properties are added but no change
> to phy-mode.
>
> >
> > Setting these should currently not have any effect on the driver code
> > when phy-mode=rgmii-id is used, see below (next-20250924, dwmac-rk.c):
> >
> >
> > switch (bsp_priv->phy_iface) {
> > case PHY_INTERFACE_MODE_RGMII:
> > dev_info(dev, "init for RGMII\n");
> > bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
> > bsp_priv->rx_delay);
> > break;
> > case PHY_INTERFACE_MODE_RGMII_ID:
> > dev_info(dev, "init for RGMII_ID\n");
> > bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
> > break;
>
> And this explains it, thanks.
>
> > I have played around with a few patches that changes this and apply the
> > rx/tx_delay for rgmii-id modes (both Linux and U-Boot), see top of [2]
> > for Linux patches. Will try to get them on ML in a few days.
>
> We should not really be expanding the use of rx_delay and
> tx_delay. The standardized properties {tx|rx}-internal-delay-ps should
> be used.
as Jonas wrote the delays do nothing for rgmii-id. So the whole thing
must have been me doing something wonky, because on re-testing
everything, it is as expected - no delays necessary and ethernet just
works.
So I'll drop this patch altogether and adapt the TS233 one.
Heiko
Heiko
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/6] arm64: dts: rockchip: describe mcu eeprom cells on rk3568-ts433
2025-09-25 9:29 [PATCH 0/6] Some cleanups and addition of another Qnap TSx33 device Heiko Stuebner
2025-09-25 9:29 ` [PATCH 1/6] arm64: dts: rockchip: move cpu_thermal node to the correct position Heiko Stuebner
2025-09-25 9:29 ` [PATCH 2/6] arm64: dts: rockchip: Fix the 1Ghz ethernet on Qnap TS433 Heiko Stuebner
@ 2025-09-25 9:29 ` Heiko Stuebner
2025-09-25 9:29 ` [PATCH 4/6] arm64: dts: rockchip: move common qnap tsx33 parts to dtsi Heiko Stuebner
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Heiko Stuebner @ 2025-09-25 9:29 UTC (permalink / raw)
To: heiko
Cc: robh, krzk+dt, conor+dt, ukleinek, devicetree, linux-kernel,
linux-arm-kernel, linux-rockchip
The MCU's eeprom contains the unit's serial and a number of slots for
mac-addresses. As the MCU seems to be used in different devices, up to
8 mac addresses can live there and the unused slots are actually
initialized with empty mac-address strings like 00:00:00:00:05:09 .
Interestingly on the TS-433, the PCIe ethernet adapter brings its own
memory to hold its mac, and the gmac0 is supposed to get its mac from
the second mac-slot, while the first one stays empty.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
.../boot/dts/rockchip/rk3568-qnap-ts433.dts | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
index e8af92a011d6..3fe9a7fce73e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
@@ -657,6 +657,68 @@ fan: fan-0 {
#cooling-cells = <2>;
cooling-levels = <0 64 89 128 166 204 221 238>;
};
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ serial-number@0 {
+ reg = <0x0 0x13>;
+ };
+
+ ext-port@22 {
+ reg = <0x22 0x2>;
+ };
+
+ mac0: mac@24 {
+ compatible = "mac-base";
+ reg = <0x24 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ mac1: mac@35 {
+ compatible = "mac-base";
+ reg = <0x35 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ mac2: mac@46 {
+ compatible = "mac-base";
+ reg = <0x46 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ mac3: mac@57 {
+ compatible = "mac-base";
+ reg = <0x57 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ mac4: mac@68 {
+ compatible = "mac-base";
+ reg = <0x68 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ mac5: mac@79 {
+ compatible = "mac-base";
+ reg = <0x79 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ mac6: mac@8a {
+ compatible = "mac-base";
+ reg = <0x8a 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ mac7: mac@9b {
+ compatible = "mac-base";
+ reg = <0x9b 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
};
};
--
2.47.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 4/6] arm64: dts: rockchip: move common qnap tsx33 parts to dtsi
2025-09-25 9:29 [PATCH 0/6] Some cleanups and addition of another Qnap TSx33 device Heiko Stuebner
` (2 preceding siblings ...)
2025-09-25 9:29 ` [PATCH 3/6] arm64: dts: rockchip: describe mcu eeprom cells on rk3568-ts433 Heiko Stuebner
@ 2025-09-25 9:29 ` Heiko Stuebner
2025-09-25 9:29 ` [PATCH 5/6] dt-bindings: arm: rockchip: add TS233 to RK3568-based QNAP NAS devices Heiko Stuebner
2025-09-25 9:29 ` [PATCH 6/6] arm64: dts: rockchip: add QNAP TS233 devicetree Heiko Stuebner
5 siblings, 0 replies; 11+ messages in thread
From: Heiko Stuebner @ 2025-09-25 9:29 UTC (permalink / raw)
To: heiko
Cc: robh, krzk+dt, conor+dt, ukleinek, devicetree, linux-kernel,
linux-arm-kernel, linux-rockchip
The NAS series based around the rk3568 contains a number of models with
1-4 drives, that reuse most of the board structure.
Therefore move the shared parts to a dtsi, to be included by the devices.
As the smallest device is the 1-bay TS133, keep everything > slot1 in
the individual devicetree.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
.../boot/dts/rockchip/rk3568-qnap-ts433.dts | 666 +-----------------
.../boot/dts/rockchip/rk3568-qnap-tsx33.dtsi | 608 ++++++++++++++++
2 files changed, 645 insertions(+), 629 deletions(-)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
index 3fe9a7fce73e..c7443748b2dc 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts
@@ -6,10 +6,7 @@
/dts-v1/;
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include "rk3568.dtsi"
+#include "rk3568-qnap-tsx33.dtsi"
/ {
model = "Qnap TS-433-4G NAS System 4-Bay";
@@ -17,83 +14,6 @@ / {
aliases {
ethernet0 = &gmac0;
- mmc0 = &sdhci;
- rtc0 = &rtc_rv8263;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <©_button_pin>, <&reset_button_pin>;
- pinctrl-names = "default";
-
- key-copy {
- label = "copy";
- gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_COPY>;
- };
-
- key-reset {
- label = "reset";
- gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_DISK;
- gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
- label = "hdd1:green:disk";
- linux,default-trigger = "disk-activity";
- pinctrl-names = "default";
- pinctrl-0 = <&hdd1_led_pin>;
- };
-
- led-1 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_DISK;
- gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
- label = "hdd2:green:disk";
- linux,default-trigger = "disk-activity";
- pinctrl-names = "default";
- pinctrl-0 = <&hdd2_led_pin>;
- };
-
- led-2 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_DISK;
- gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_LOW>;
- label = "hdd3:green:disk";
- linux,default-trigger = "disk-activity";
- pinctrl-names = "default";
- pinctrl-0 = <&hdd3_led_pin>;
- };
-
- led-3 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_DISK;
- gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
- label = "hdd4:green:disk";
- linux,default-trigger = "disk-activity";
- pinctrl-names = "default";
- pinctrl-0 = <&hdd4_led_pin>;
- };
- };
-
- dc_12v: regulator-dc-12v {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
};
vcc3v3_pcie: regulator-vcc3v3-pcie {
@@ -105,74 +25,6 @@ vcc3v3_pcie: regulator-vcc3v3-pcie {
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
vin-supply = <&dc_12v>;
};
-
- vcc3v3_sys: regulator-vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_host: regulator-vcc5v0-host {
- compatible = "regulator-fixed";
- enable-active-high;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
- regulator-name = "vcc5v0_host";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc5v0_otg: regulator-vcc5v0-otg {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_otg_en>;
- regulator-name = "vcc5v0_otg";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc5v0_sys: regulator-vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_usb: regulator-vcc5v0-usb {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-};
-
-/* connected to usb_host0_xhci */
-&combphy0 {
- status = "okay";
-};
-
-/* connected to sata1 */
-&combphy1 {
- status = "okay";
};
/* connected to sata2 */
@@ -180,70 +32,6 @@ &combphy2 {
status = "okay";
};
-&cpu0 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_cpu>;
-};
-
-/*
- * The MCU can provide system temperature too, but only by polling and of
- * course also cannot set trip points. So attach to the cpu thermal-zone
- * instead to control the fan.
- */
-&cpu_thermal {
- trips {
- case_fan0: case-fan0 {
- hysteresis = <2000>;
- temperature = <35000>;
- type = "active";
- };
-
- case_fan1: case-fan1 {
- hysteresis = <2000>;
- temperature = <45000>;
- type = "active";
- };
-
- case_fan2: case-fan2 {
- hysteresis = <2000>;
- temperature = <65000>;
- type = "active";
- };
- };
-
- cooling-maps {
- /*
- * Always provide some air movement, due to small case
- * full of harddrives.
- */
- map1 {
- cooling-device = <&fan THERMAL_NO_LIMIT 1>;
- trip = <&case_fan0>;
- };
-
- map2 {
- cooling-device = <&fan 2 3>;
- trip = <&case_fan1>;
- };
-
- map3 {
- cooling-device = <&fan 4 THERMAL_NO_LIMIT>;
- trip = <&case_fan2>;
- };
- };
-};
-
&gmac0 {
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
@@ -262,263 +50,7 @@ &gmac0_rgmii_clk
status = "okay";
};
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
- system-power-controller;
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
- wakeup-source;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-name = "vdd_gpu";
- regulator-always-on;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vdd_npu: DCDC_REG4 {
- regulator-name = "vdd_npu";
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG5 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_image: LDO_REG1 {
- regulator-name = "vdda0v9_image";
- regulator-always-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda_0v9: LDO_REG2 {
- regulator-name = "vdda_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_pmu: LDO_REG3 {
- regulator-name = "vdda0v9_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vccio_acodec: LDO_REG4 {
- regulator-name = "vccio_acodec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_pmu: LDO_REG6 {
- regulator-name = "vcc3v3_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcca_1v8: LDO_REG7 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca1v8_pmu: LDO_REG8 {
- regulator-name = "vcca1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca1v8_image: LDO_REG9 {
- regulator-name = "vcca1v8_image";
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3: SWITCH_REG1 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_sd: SWITCH_REG2 {
- regulator-name = "vcc3v3_sd";
- /*
- * turning this off, breaks access to both
- * PCIe controllers, refclk generator perhaps
- */
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-
- vdd_cpu: regulator@40 {
- compatible = "silergy,syr827";
- reg = <0x40>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1390000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
- };
-};
-
&i2c1 {
- status = "okay";
-
- rtc_rv8263: rtc@51 {
- compatible = "microcrystal,rv8263";
- reg = <0x51>;
- wakeup-source;
- };
-
- /* eeprom for vital-product-data on the mainboard */
- eeprom@54 {
- compatible = "giantec,gt24c04a", "atmel,24c04";
- reg = <0x54>;
- label = "VPD_MB";
- num-addresses = <2>;
- pagesize = <16>;
- read-only;
- };
-
/* eeprom for vital-product-data on the backplane */
eeprom@56 {
compatible = "giantec,gt24c04a", "atmel,24c04";
@@ -530,6 +62,42 @@ eeprom@56 {
};
};
+&leds {
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DISK;
+ gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
+ label = "hdd2:green:disk";
+ linux,default-trigger = "disk-activity";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdd2_led_pin>;
+ };
+
+ led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DISK;
+ gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_LOW>;
+ label = "hdd3:green:disk";
+ linux,default-trigger = "disk-activity";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdd3_led_pin>;
+ };
+
+ led-3 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DISK;
+ gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
+ label = "hdd4:green:disk";
+ linux,default-trigger = "disk-activity";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdd4_led_pin>;
+ };
+};
+
+&mcu {
+ compatible = "qnap,ts433-mcu";
+};
+
&mdio0 {
rgmii_phy0: ethernet-phy@3 {
/* Motorcomm YT8521 phy */
@@ -569,21 +137,7 @@ eth_phy0_reset_pin: eth-phy0-reset-pin {
};
};
- keys {
- copy_button_pin: copy-button-pin {
- rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- reset_button_pin: reset-button-pin {
- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
leds {
- hdd1_led_pin: hdd1-led-pin {
- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
hdd2_led_pin: hdd2-led-pin {
rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
};
@@ -596,152 +150,12 @@ hdd4_led_pin: hdd4_led-pin {
rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- vcc5v0_otg_en: vcc5v0-otg-en {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- vccio4-supply = <&vcc_1v8>;
- vccio6-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sata1 {
- status = "okay";
};
&sata2 {
status = "okay";
};
-&sdhci {
- bus-width = <8>;
- max-frequency = <200000000>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
-};
-
-/*
- * Connected to an MCU, that provides access to more LEDs,
- * buzzer, fan control and more.
- */
-&uart0 {
- status = "okay";
-
- mcu {
- compatible = "qnap,ts433-mcu";
-
- fan: fan-0 {
- #cooling-cells = <2>;
- cooling-levels = <0 64 89 128 166 204 221 238>;
- };
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- serial-number@0 {
- reg = <0x0 0x13>;
- };
-
- ext-port@22 {
- reg = <0x22 0x2>;
- };
-
- mac0: mac@24 {
- compatible = "mac-base";
- reg = <0x24 0x11>;
- #nvmem-cell-cells = <1>;
- };
-
- mac1: mac@35 {
- compatible = "mac-base";
- reg = <0x35 0x11>;
- #nvmem-cell-cells = <1>;
- };
-
- mac2: mac@46 {
- compatible = "mac-base";
- reg = <0x46 0x11>;
- #nvmem-cell-cells = <1>;
- };
-
- mac3: mac@57 {
- compatible = "mac-base";
- reg = <0x57 0x11>;
- #nvmem-cell-cells = <1>;
- };
-
- mac4: mac@68 {
- compatible = "mac-base";
- reg = <0x68 0x11>;
- #nvmem-cell-cells = <1>;
- };
-
- mac5: mac@79 {
- compatible = "mac-base";
- reg = <0x79 0x11>;
- #nvmem-cell-cells = <1>;
- };
-
- mac6: mac@8a {
- compatible = "mac-base";
- reg = <0x8a 0x11>;
- #nvmem-cell-cells = <1>;
- };
-
- mac7: mac@9b {
- compatible = "mac-base";
- reg = <0x9b 0x11>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-};
-
-/*
- * Pins available on CN3 connector at TTL voltage level (3V3).
- * ,_ _.
- * |1234| 1=TX 2=VCC
- * `----' 3=RX 4=GND
- */
-&uart2 {
- status = "okay";
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-/* connected to usb_host0_xhci */
-&usb2phy0_otg {
- phy-supply = <&vcc5v0_otg>;
- status = "okay";
-};
-
&usb2phy1 {
status = "okay";
};
@@ -767,12 +181,6 @@ &usb_host0_ohci {
status = "okay";
};
-/* front port */
-&usb_host0_xhci {
- dr_mode = "host";
- status = "okay";
-};
-
/* left port backside */
&usb_host1_ehci {
status = "okay";
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi
new file mode 100644
index 000000000000..f009275c72c8
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi
@@ -0,0 +1,608 @@
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "rk3568.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdhci;
+ rtc0 = &rtc_rv8263;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <©_button_pin>, <&reset_button_pin>;
+ pinctrl-names = "default";
+
+ key-copy {
+ label = "copy";
+ gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_COPY>;
+ };
+
+ key-reset {
+ label = "reset";
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DISK;
+ gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
+ label = "hdd1:green:disk";
+ linux,default-trigger = "disk-activity";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdd1_led_pin>;
+ };
+ };
+
+ dc_12v: regulator-dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc3v3_sys: regulator-vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_host: regulator-vcc5v0-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_otg: regulator-vcc5v0-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_otg_en>;
+ regulator-name = "vcc5v0_otg";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_sys: regulator-vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_usb: regulator-vcc5v0-usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+};
+
+/* connected to usb_host0_xhci */
+&combphy0 {
+ status = "okay";
+};
+
+/* connected to sata1 */
+&combphy1 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+/*
+ * The MCU can provide system temperature too, but only by polling and of
+ * course also cannot set trip points. So attach to the cpu thermal-zone
+ * instead to control the fan.
+ */
+&cpu_thermal {
+ trips {
+ case_fan0: case-fan0 {
+ hysteresis = <2000>;
+ temperature = <35000>;
+ type = "active";
+ };
+
+ case_fan1: case-fan1 {
+ hysteresis = <2000>;
+ temperature = <45000>;
+ type = "active";
+ };
+
+ case_fan2: case-fan2 {
+ hysteresis = <2000>;
+ temperature = <65000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ /*
+ * Always provide some air movement, due to small case
+ * full of harddrives.
+ */
+ map1 {
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ trip = <&case_fan0>;
+ };
+
+ map2 {
+ cooling-device = <&fan 2 3>;
+ trip = <&case_fan1>;
+ };
+
+ map3 {
+ cooling-device = <&fan 4 THERMAL_NO_LIMIT>;
+ trip = <&case_fan2>;
+ };
+ };
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ system-power-controller;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ /*
+ * turning this off, breaks access to both
+ * PCIe controllers, refclk generator perhaps
+ */
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ vdd_cpu: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1390000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ rtc_rv8263: rtc@51 {
+ compatible = "microcrystal,rv8263";
+ reg = <0x51>;
+ wakeup-source;
+ };
+
+ /* eeprom for vital-product-data on the mainboard */
+ eeprom@54 {
+ compatible = "giantec,gt24c04a", "atmel,24c04";
+ reg = <0x54>;
+ label = "VPD_MB";
+ num-addresses = <2>;
+ pagesize = <16>;
+ read-only;
+ };
+};
+
+&pinctrl {
+ keys {
+ copy_button_pin: copy-button-pin {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ reset_button_pin: reset-button-pin {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ hdd1_led_pin: hdd1-led-pin {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_otg_en: vcc5v0-otg-en {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ vccio4-supply = <&vcc_1v8>;
+ vccio6-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+/*
+ * Connected to an MCU, that provides access to more LEDs,
+ * buzzer, fan control and more.
+ */
+&uart0 {
+ status = "okay";
+
+ mcu: mcu {
+ fan: fan-0 {
+ #cooling-cells = <2>;
+ cooling-levels = <0 64 89 128 166 204 221 238>;
+ };
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ serial-number@0 {
+ reg = <0x0 0x13>;
+ };
+
+ ext-port@22 {
+ reg = <0x22 0x2>;
+ };
+
+ mac0: mac@24 {
+ compatible = "mac-base";
+ reg = <0x24 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ mac1: mac@35 {
+ compatible = "mac-base";
+ reg = <0x35 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ mac2: mac@46 {
+ compatible = "mac-base";
+ reg = <0x46 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ mac3: mac@57 {
+ compatible = "mac-base";
+ reg = <0x57 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ mac4: mac@68 {
+ compatible = "mac-base";
+ reg = <0x68 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ mac5: mac@79 {
+ compatible = "mac-base";
+ reg = <0x79 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ mac6: mac@8a {
+ compatible = "mac-base";
+ reg = <0x8a 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ mac7: mac@9b {
+ compatible = "mac-base";
+ reg = <0x9b 0x11>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+};
+
+/*
+ * Pins available on CN3 connector at TTL voltage level (3V3).
+ * ,_ _.
+ * |1234| 1=TX 2=VCC
+ * `----' 3=RX 4=GND
+ */
+&uart2 {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+/* connected to usb_host0_xhci */
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_otg>;
+ status = "okay";
+};
+
+/* front port */
+&usb_host0_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
--
2.47.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 5/6] dt-bindings: arm: rockchip: add TS233 to RK3568-based QNAP NAS devices
2025-09-25 9:29 [PATCH 0/6] Some cleanups and addition of another Qnap TSx33 device Heiko Stuebner
` (3 preceding siblings ...)
2025-09-25 9:29 ` [PATCH 4/6] arm64: dts: rockchip: move common qnap tsx33 parts to dtsi Heiko Stuebner
@ 2025-09-25 9:29 ` Heiko Stuebner
2025-09-25 19:27 ` Conor Dooley
2025-09-25 9:29 ` [PATCH 6/6] arm64: dts: rockchip: add QNAP TS233 devicetree Heiko Stuebner
5 siblings, 1 reply; 11+ messages in thread
From: Heiko Stuebner @ 2025-09-25 9:29 UTC (permalink / raw)
To: heiko
Cc: robh, krzk+dt, conor+dt, ukleinek, devicetree, linux-kernel,
linux-arm-kernel, linux-rockchip
QNAP builds a number of variants of the RK3568-based NAS design.
Add the 2-bay TS233 variant.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 28db6bd6aa5b..27c353c4452f 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -846,9 +846,11 @@ properties:
- const: prt,mecsbc
- const: rockchip,rk3568
- - description: QNAP TS-433-4G 4-Bay NAS
+ - description: QNAP TS-x33 NAS devices
items:
- - const: qnap,ts433
+ - enum:
+ - qnap,ts233
+ - qnap,ts433
- const: rockchip,rk3568
- description: Radxa Compute Module 3 (CM3)
--
2.47.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 5/6] dt-bindings: arm: rockchip: add TS233 to RK3568-based QNAP NAS devices
2025-09-25 9:29 ` [PATCH 5/6] dt-bindings: arm: rockchip: add TS233 to RK3568-based QNAP NAS devices Heiko Stuebner
@ 2025-09-25 19:27 ` Conor Dooley
0 siblings, 0 replies; 11+ messages in thread
From: Conor Dooley @ 2025-09-25 19:27 UTC (permalink / raw)
To: Heiko Stuebner
Cc: robh, krzk+dt, conor+dt, ukleinek, devicetree, linux-kernel,
linux-arm-kernel, linux-rockchip
[-- Attachment #1: Type: text/plain, Size: 52 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 6/6] arm64: dts: rockchip: add QNAP TS233 devicetree
2025-09-25 9:29 [PATCH 0/6] Some cleanups and addition of another Qnap TSx33 device Heiko Stuebner
` (4 preceding siblings ...)
2025-09-25 9:29 ` [PATCH 5/6] dt-bindings: arm: rockchip: add TS233 to RK3568-based QNAP NAS devices Heiko Stuebner
@ 2025-09-25 9:29 ` Heiko Stuebner
5 siblings, 0 replies; 11+ messages in thread
From: Heiko Stuebner @ 2025-09-25 9:29 UTC (permalink / raw)
To: heiko
Cc: robh, krzk+dt, conor+dt, ukleinek, devicetree, linux-kernel,
linux-arm-kernel, linux-rockchip
The TS233 is a 2 bay NAS similar to the TS433. Architecture-wise it really
seems to be the same minus the additional PCIe connected components the
TS433 has.
So it just uses two of the SoCs SATA ports and the SoC's gigabit ethernet.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3568-qnap-ts233.dts | 133 ++++++++++++++++++
2 files changed, 134 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 099520962ffb..f1b7917ae22b 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -136,6 +136,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-photonicat.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts233.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts
new file mode 100644
index 000000000000..29181de1bd26
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de>
+ */
+
+/dts-v1/;
+
+#include "rk3568-qnap-tsx33.dtsi"
+
+/ {
+ model = "Qnap TS-233-2G NAS System 2-Bay";
+ compatible = "qnap,ts233", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ };
+};
+
+/* connected to sata2 */
+&combphy2 {
+ status = "okay";
+};
+
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy0>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ rx_delay = <0x15>;
+ tx_delay = <0x21>;
+ status = "okay";
+};
+
+&i2c1 {
+ /* eeprom for vital-product-data on the backplane */
+ eeprom@56 {
+ compatible = "giantec,gt24c04a", "atmel,24c04";
+ reg = <0x56>;
+ label = "VPD_BP";
+ num-addresses = <2>;
+ pagesize = <16>;
+ read-only;
+ };
+};
+
+&leds {
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DISK;
+ gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
+ label = "hdd2:green:disk";
+ linux,default-trigger = "disk-activity";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdd2_led_pin>;
+ };
+};
+
+&mcu {
+ compatible = "qnap,ts233-mcu";
+};
+
+&mdio0 {
+ rgmii_phy0: ethernet-phy@3 {
+ /* Motorcomm YT8521 phy */
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x3>;
+ pinctrl-0 = <ð_phy0_reset_pin>;
+ pinctrl-names = "default";
+ reset-assert-us = <10000>;
+ reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ gmac0 {
+ eth_phy0_reset_pin: eth-phy0-reset-pin {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ hdd2_led_pin: hdd2-led-pin {
+ rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+/* connected to usb_host1_ehci/ohci */
+&usb2phy1_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+/* connected to usb_host0_ehci/ohci */
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+/* right port backside */
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+/* left port backside */
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
--
2.47.2
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