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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id i26-20020a50d75a000000b0041e84bb406fsm1071387edj.0.2022.04.22.08.51.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 Apr 2022 08:51:32 -0700 (PDT) Message-ID: <338344c8-1812-de27-80f2-df4c2dc3c17b@linaro.org> Date: Fri, 22 Apr 2022 17:51:31 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 3/6] dt-bindings: pci/qcom-pcie: specify reg-names explicitly Content-Language: en-US To: Dmitry Baryshkov Cc: Andy Gross , Bjorn Andersson , Rob Herring , Stanimir Varbanov , Bjorn Helgaas , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org References: <20220422114841.1854138-1-dmitry.baryshkov@linaro.org> <20220422114841.1854138-4-dmitry.baryshkov@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 22/04/2022 17:47, Dmitry Baryshkov wrote: > On Fri, 22 Apr 2022 at 15:55, Krzysztof Kozlowski > wrote: >> >> On 22/04/2022 13:48, Dmitry Baryshkov wrote: >>> Instead of specifying the enum of possible reg-names, specify them >>> explicitly. This allows us to specify which chipsets need the "atu" >>> regions, which do not. Also it clearly describes which platforms >>> enumerate PCIe cores using the dbi region and which use parf region for >>> that. >>> >>> Signed-off-by: Dmitry Baryshkov >>> --- >>> .../devicetree/bindings/pci/qcom,pcie.yaml | 96 ++++++++++++++++--- >>> 1 file changed, 81 insertions(+), 15 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >>> index 7210057d1511..e78e63ea4b25 100644 >>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >>> @@ -35,21 +35,6 @@ properties: >>> - qcom,pcie-ipq6018 >>> - const: snps,dw-pcie >>> >>> - reg: >>> - minItems: 4 >>> - maxItems: 5 >> >> This should stay. >> >>> - >>> - reg-names: >>> - minItems: 4 >>> - maxItems: 5 >>> - items: >>> - enum: >>> - - parf # Qualcomm specific registers >>> - - dbi # DesignWare PCIe registers >>> - - elbi # External local bus interface registers >>> - - config # PCIe configuration space >>> - - atu # ATU address space (optional) >> >> Move one of your lists for specific compatibles here and name last >> element optional (minItems: 4). >> >> You will need to fix the order of regs in DTS to match the one defined here. > > I see your idea. I wanted to be explicit, which platforms need atu and > which do not. You'd prefer not to. Opposite, I wish platforms to be specific, which need atu which not. However I wish the strictly defined, same order for everyone because it looks possible. > Let's probably drop this for now. The bindings proposed in patch 1 > work for now. I will work on updating reg-names later. Best regards, Krzysztof