From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC17935F61C; Mon, 2 Mar 2026 11:08:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772449702; cv=none; b=oM/UtV3apjrCs2j94MBGMFISomZdSCpz03XMWTaCY0yANRMnHiZLPTJEJ2wqggniCyv3aw3KixG/que1jQF/aeu9EQmO1YIM4OG/MOK5Q0z/Zo2ssyuto6vwSnL/CBFRfRlWvyKqh3qLGRYvNq6HszJ542pZiHcpNORl++d1gZo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772449702; c=relaxed/simple; bh=yDMWWLMS1/nTjcOgzviWbOPuhhO4mzc+lfRfkF+W9Uk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tqujRavzsYBpMeSMjaVKX5p6mfBzTV6PMB73c4oO5Z3fOJZYbq9GPT6yN4jLwXlp0muWKHIN7dMmHL9kT0uCypaHkfd9M5oMzYGK/XkmpdIf/mBpZSZIalp44u8++eAgrwYxGe7w6zpcm2HBftDXnT9Y3q+Ci8vSeXx1JvlG7oE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=Ksmu/jun; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="Ksmu/jun" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=WJ6Fp+6ND9bT9YLc0KTOaJB8aEFzkS2JdOdry7EMlC0=; b=Ksmu/junNI891rI+Ldwlu8ZOJY USTaEE9SRmuxDtB7tw1boBq1aKDP9VOpYkyP1KF8JJ8W0bsTfqSl+oFOoYEeT7netLIqrKUViXeOg s/WIYF7opi46e4TX8s0ltxDLp42GZL1CIygKM1hHpk2ksDaxM3hjdpjDRH/zQkuuOwB1QBmNKF2V3 xuh33WUrtEjXPVYQ7V014Qpx1ssy/hUE3qPNvnjNSsWrSMJZnw/x1gvTr8+rjaQ0+vMcJGncIGLKp fms8+QIHeP7QE3LBFcXiCgZ1Jxnq0YwXUaZnhZ/FOO8gtFWVz68oy1alLKIHf/iWkFq2GHrTkvQhv Zcc/KD4Q==; From: Heiko Stuebner To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , david@ixit.cz Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Filla , David Heidelberg Subject: Re: [PATCH] arm64: dts: rockchip: Fix PCIe v3 pinctrl for BPI-R2-Pro Date: Mon, 02 Mar 2026 12:08:14 +0100 Message-ID: <3404271.44csPzL39Z@phil> In-Reply-To: <20260301-rk3568-bri-r2-pro-fix-pcie-v1-1-b9ed318b4a77@ixit.cz> References: <20260301-rk3568-bri-r2-pro-fix-pcie-v1-1-b9ed318b4a77@ixit.cz> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Hi David, Am Sonntag, 1. M=C3=A4rz 2026, 16:54:41 Mitteleurop=C3=A4ische Normalzeit s= chrieb David Heidelberg via B4 Relay: > From: David Heidelberg >=20 > Add missing pinctrl for PD4 (PI6C PCIe clock enable, > PCIE_CLKEN_H_GPIO0_D4) and set output high. >=20 > This does fix freeze at initialization due pinctrl being in input > state. >=20 > Reported-by: Martin Filla # reported by private messa= ge > Signed-off-by: David Heidelberg > --- > arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 6 ++++++ > 1 file changed, 6 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/ar= m64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts > index 4d3ebe50b90ba..b4c8abe37d1f3 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts > @@ -121,6 +121,8 @@ vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { > regulator-max-microvolt =3D <3300000>; > enable-active-high; > gpios =3D <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; > + pinctrl-0 =3D <&pi6cpcie_enable_h>; > + pinctrl-names =3D "default"; please model hardware not how you want to use it. The pi6c in the pin-name suggests, that this is a Diodes clock-generator that creates the 100MHz frequency for PCIe [0] . Please see [1] for one possible variant to model this. Heiko [0] https://www.diodes.com/part/view/PI6CG33602C or some variant of it [1] http://lore.kernel.org/all/20260210080303.680403-1-heiko@sntech.de