[PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

[PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

[Geert Uytterhoeven]

Amend the DT bindings to include the optional external clock on
(H)SCI(F) and some SCIFA, where this pin can serve as a clock input,
depending on board wiring.

Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index 2c9e6b8477e92792..8efc9b6f35637fbb 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -43,6 +43,9 @@ Required properties:
   - clocks: Must contain a phandle and clock-specifier pair for each entry
     in clock-names.
   - clock-names: Must contain "fck" for the SCIx UART functional clock.
+    On (H)SCI(F) and some SCIFA, an additional clock may be specified:
+      - "hsck" for the optional external clock input (on HSCIF),
+      - "sck" for the optional external clock input (on other variants).
 
 Note: Each enabled SCIx UART should have an alias correctly numbered in the
 "aliases" node.
-- 
1.9.1

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[PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support

[Geert Uytterhoeven]

Amend the DT bindings to include the optional clock sources for the Baud
Rate Generator for External Clock (BRG), as found on some SCIF variants
and on HSCIF.

Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index 8efc9b6f35637fbb..ae907e39b11c2a5a 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -46,6 +46,12 @@ Required properties:
     On (H)SCI(F) and some SCIFA, an additional clock may be specified:
       - "hsck" for the optional external clock input (on HSCIF),
       - "sck" for the optional external clock input (on other variants).
+    On UARTs equipped with a Baud Rate Generator for External Clock (BRG)
+    (some SCIF and HSCIF), additional clocks may be specified:
+      - "int_clk" for the optional internal clock source for the frequency
+	divider (typically the (AXI or SHwy) bus clock),
+      - "scif_clk" for the optional external clock source for the frequency
+	divider (SCIF_CLK).
 
 Note: Each enabled SCIx UART should have an alias correctly numbered in the
 "aliases" node.
-- 
1.9.1

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Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

[Laurent Pinchart]

Hi Geert,

Thank you for the patch.

On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote:
> Amend the DT bindings to include the optional external clock on
> (H)SCI(F) and some SCIFA, where this pin can serve as a clock input,
> depending on board wiring.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index
> 2c9e6b8477e92792..8efc9b6f35637fbb 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> @@ -43,6 +43,9 @@ Required properties:
>    - clocks: Must contain a phandle and clock-specifier pair for each entry
>      in clock-names.
>    - clock-names: Must contain "fck" for the SCIx UART functional clock.
> +    On (H)SCI(F) and some SCIFA, an additional clock may be specified:

Could you list the SCIFA variants that support external clocks ?

> +      - "hsck" for the optional external clock input (on HSCIF),
> +      - "sck" for the optional external clock input (on other variants).
> 
>  Note: Each enabled SCIx UART should have an alias correctly numbered in the
> "aliases" node.

-- 
Regards,

Laurent Pinchart

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Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support

[Laurent Pinchart]

Hi Geert,

Thank you for the patch.

On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote:
> Amend the DT bindings to include the optional clock sources for the Baud
> Rate Generator for External Clock (BRG), as found on some SCIF variants
> and on HSCIF.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: devicetree@vger.kernel.org
> ---
>  Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index
> 8efc9b6f35637fbb..ae907e39b11c2a5a 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> @@ -46,6 +46,12 @@ Required properties:
>      On (H)SCI(F) and some SCIFA, an additional clock may be specified:
>        - "hsck" for the optional external clock input (on HSCIF),
>        - "sck" for the optional external clock input (on other variants).
> +    On UARTs equipped with a Baud Rate Generator for External Clock (BRG)
> +    (some SCIF and HSCIF), additional clocks may be specified:
> +      - "int_clk" for the optional internal clock source for the frequency
> +	divider (typically the (AXI or SHwy) bus clock),

Isn't this always the same clock as the SCIF functional clock ?

> +      - "scif_clk" for the optional external clock source for the frequency
> +	divider (SCIF_CLK).
> 
>  Note: Each enabled SCIx UART should have an alias correctly numbered in the
> "aliases" node.

-- 
Regards,

Laurent Pinchart

Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

[Laurent Pinchart]

Hi Geert,

On Thursday 19 November 2015 22:19:14 Laurent Pinchart wrote:
> On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote:
> > Amend the DT bindings to include the optional external clock on
> > (H)SCI(F) and some SCIFA, where this pin can serve as a clock input,
> > depending on board wiring.
> > 
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Cc: devicetree@vger.kernel.org
> > ---
> > 
> >  Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> > b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index
> > 2c9e6b8477e92792..8efc9b6f35637fbb 100644
> > --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> > +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> > 
> > @@ -43,6 +43,9 @@ Required properties:
> >    - clocks: Must contain a phandle and clock-specifier pair for each
> >    entry
> >    
> >      in clock-names.
> >    
> >    - clock-names: Must contain "fck" for the SCIx UART functional clock.
> > 
> > +    On (H)SCI(F) and some SCIFA, an additional clock may be specified:
> Could you list the SCIFA variants that support external clocks ?
> 
> > +      - "hsck" for the optional external clock input (on HSCIF),
> > +      - "sck" for the optional external clock input (on other variants).

Additionally, those clocks are used as inputs to the baud rate generator for 
external clocks, as the ones listed in patch 02/25 in this series. I'd merge 
the two patches and clarify the wording.

> >  Note: Each enabled SCIx UART should have an alias correctly numbered in
> >  the "aliases" node.

-- 
Regards,

Laurent Pinchart

Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

[Geert Uytterhoeven]

Hi Laurent,

On Thu, Nov 19, 2015 at 9:19 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote:
>> diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index
>> 2c9e6b8477e92792..8efc9b6f35637fbb 100644
>> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> @@ -43,6 +43,9 @@ Required properties:
>>    - clocks: Must contain a phandle and clock-specifier pair for each entry
>>      in clock-names.
>>    - clock-names: Must contain "fck" for the SCIx UART functional clock.
>> +    On (H)SCI(F) and some SCIFA, an additional clock may be specified:
>
> Could you list the SCIFA variants that support external clocks ?

The list is in the commit description of "[PATCH 19/25] serial: sh-sci: Add
support for optional external (H)SCK input": sh7723, sh7724, and r8a7740.

Note that the list is probably incomplete, so I don't know if it's that useful
to have it in the binding docs. Especially as I haven't verified yet that it
actually works ;-)

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

[Geert Uytterhoeven]

On Thu, Nov 19, 2015 at 9:27 PM, Laurent Pinchart
<laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org> wrote:
> On Thursday 19 November 2015 22:19:14 Laurent Pinchart wrote:
>> On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote:
>> > Amend the DT bindings to include the optional external clock on
>> > (H)SCI(F) and some SCIFA, where this pin can serve as a clock input,
>> > depending on board wiring.

>> > --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> > +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> >
>> > @@ -43,6 +43,9 @@ Required properties:
>> >    - clocks: Must contain a phandle and clock-specifier pair for each
>> >    entry
>> >
>> >      in clock-names.
>> >
>> >    - clock-names: Must contain "fck" for the SCIx UART functional clock.
>> >
>> > +    On (H)SCI(F) and some SCIFA, an additional clock may be specified:
>> Could you list the SCIFA variants that support external clocks ?
>>
>> > +      - "hsck" for the optional external clock input (on HSCIF),
>> > +      - "sck" for the optional external clock input (on other variants).
>
> Additionally, those clocks are used as inputs to the baud rate generator for
> external clocks, as the ones listed in patch 02/25 in this series. I'd merge
> the two patches and clarify the wording.

"SCK" predates the BRG, it even exists on SCI in H8/300.

That SCK is used as input to the BRG is just an artefact of how the BRG was
added to the SCIF. The BRG is just muxed with the existing SCK to form a clock
input, which is muxed with the BRR clock through the SCSCR.CKEx bits.
And the BRG itself can choose between SCIF_CLK and INT_CLK.

Hence that's why I split it in two parts.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support

[Geert Uytterhoeven]

Hi Laurent,

On Thu, Nov 19, 2015 at 9:26 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote:
>> Amend the DT bindings to include the optional clock sources for the Baud
>> Rate Generator for External Clock (BRG), as found on some SCIF variants
>> and on HSCIF.

>> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> @@ -46,6 +46,12 @@ Required properties:
>>      On (H)SCI(F) and some SCIFA, an additional clock may be specified:
>>        - "hsck" for the optional external clock input (on HSCIF),
>>        - "sck" for the optional external clock input (on other variants).
>> +    On UARTs equipped with a Baud Rate Generator for External Clock (BRG)
>> +    (some SCIF and HSCIF), additional clocks may be specified:
>> +      - "int_clk" for the optional internal clock source for the frequency
>> +     divider (typically the (AXI or SHwy) bus clock),
>
> Isn't this always the same clock as the SCIF functional clock ?

(On R-Car Gen2/3)

No, SCIF uses different parents for fck (p) and int_clk (zs).
HSCIF uses the same parents though (zs).

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support

[Laurent Pinchart]

Hi Geert,

On Thursday 19 November 2015 21:44:27 Geert Uytterhoeven wrote:
> On Thu, Nov 19, 2015 at 9:26 PM, Laurent Pinchart wrote:
> > On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote:
> >> Amend the DT bindings to include the optional clock sources for the Baud
> >> Rate Generator for External Clock (BRG), as found on some SCIF variants
> >> and on HSCIF.
> >> 
> >> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> >> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> >> 
> >> @@ -46,6 +46,12 @@ Required properties:
> >>      On (H)SCI(F) and some SCIFA, an additional clock may be specified:
> >>        - "hsck" for the optional external clock input (on HSCIF),
> >>        - "sck" for the optional external clock input (on other variants).
> >> 
> >> +    On UARTs equipped with a Baud Rate Generator for External Clock
> >> (BRG)
> >> +    (some SCIF and HSCIF), additional clocks may be specified:
> >> +      - "int_clk" for the optional internal clock source for the
> >> frequency
> >> +     divider (typically the (AXI or SHwy) bus clock),
> > 
> > Isn't this always the same clock as the SCIF functional clock ?
> 
> (On R-Car Gen2/3)
> 
> No, SCIF uses different parents for fck (p) and int_clk (zs).

Right, my bad.

Should we rename "int_clk" to something that makes it explicit that the clock 
is used as the BRG-EC input ? Maybe brg_clk, int_brg, int_brg_clk ? We 
probably don't need to keep the _clk suffix as it's quite evident that a clock 
name refers to a clock.

> HSCIF uses the same parents though (zs).

-- 
Regards,

Laurent Pinchart

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Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

[Laurent Pinchart]

Hi Geert,

On Thursday 19 November 2015 21:39:50 Geert Uytterhoeven wrote:
> On Thu, Nov 19, 2015 at 9:27 PM, Laurent Pinchart wrote:
> > On Thursday 19 November 2015 22:19:14 Laurent Pinchart wrote:
> >> On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote:
> >> > Amend the DT bindings to include the optional external clock on
> >> > (H)SCI(F) and some SCIFA, where this pin can serve as a clock input,
> >> > depending on board wiring.
> >> > 
> >> > --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> >> > +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> >> > 
> >> > @@ -43,6 +43,9 @@ Required properties:
> >> >    - clocks: Must contain a phandle and clock-specifier pair for each
> >> >      entry in clock-names.
> >> >    - clock-names: Must contain "fck" for the SCIx UART functional
> >> >    clock.
> >> > +    On (H)SCI(F) and some SCIFA, an additional clock may be specified:
> >>
> >> Could you list the SCIFA variants that support external clocks ?
> >> 
> >> > +      - "hsck" for the optional external clock input (on HSCIF),
> >> > +      - "sck" for the optional external clock input (on other
> >> > variants).
> > 
> > Additionally, those clocks are used as inputs to the baud rate generator
> > for external clocks, as the ones listed in patch 02/25 in this series.
> > I'd merge the two patches and clarify the wording.
> 
> "SCK" predates the BRG, it even exists on SCI in H8/300.
> 
> That SCK is used as input to the BRG is just an artefact of how the BRG was
> added to the SCIF. The BRG is just muxed with the existing SCK to form a
> clock input, which is muxed with the BRR clock through the SCSCR.CKEx bits.
> And the BRG itself can choose between SCIF_CLK and INT_CLK.
> 
> Hence that's why I split it in two parts.

It makes sense with the explanation.

I think some of the patches should be clarified to mention BRG-EC (or whatever 
you want to call it) instead of just BRG, as otherwise it's very easy to 
confuse the two BRGs. The (H)SCK clock is an input to the internal BRG, while 
the SCIF_CLK and INT_CLK are inputs to the BRG-EC. Without clarification the 
DT bindings and the code can be hard to understand.

-- 
Regards,

Laurent Pinchart

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Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support

[Geert Uytterhoeven]

Hi Laurent,

On Thu, Nov 19, 2015 at 10:13 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Thursday 19 November 2015 21:44:27 Geert Uytterhoeven wrote:
>> On Thu, Nov 19, 2015 at 9:26 PM, Laurent Pinchart wrote:
>> > On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote:
>> >> Amend the DT bindings to include the optional clock sources for the Baud
>> >> Rate Generator for External Clock (BRG), as found on some SCIF variants
>> >> and on HSCIF.
>> >>
>> >> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> >> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> >>
>> >> @@ -46,6 +46,12 @@ Required properties:
>> >>      On (H)SCI(F) and some SCIFA, an additional clock may be specified:
>> >>        - "hsck" for the optional external clock input (on HSCIF),
>> >>        - "sck" for the optional external clock input (on other variants).
>> >>
>> >> +    On UARTs equipped with a Baud Rate Generator for External Clock
>> >> (BRG)
>> >> +    (some SCIF and HSCIF), additional clocks may be specified:
>> >> +      - "int_clk" for the optional internal clock source for the
>> >> frequency
>> >> +     divider (typically the (AXI or SHwy) bus clock),
>> >
>> > Isn't this always the same clock as the SCIF functional clock ?
>>
>> (On R-Car Gen2/3)
>>
>> No, SCIF uses different parents for fck (p) and int_clk (zs).
>
> Right, my bad.
>
> Should we rename "int_clk" to something that makes it explicit that the clock
> is used as the BRG-EC input ? Maybe brg_clk, int_brg, int_brg_clk ? We
> probably don't need to keep the _clk suffix as it's quite evident that a clock
> name refers to a clock.

The documentation always uses the SoC-specific explicit clock name (e.g. zs
s3d1, or clks), or just "internal clock", so I used "int_clk".

But I agree "int_brg" sounds better.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

[Geert Uytterhoeven]

Hi Laurent,

On Thu, Nov 19, 2015 at 10:17 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Thursday 19 November 2015 21:39:50 Geert Uytterhoeven wrote:
>> On Thu, Nov 19, 2015 at 9:27 PM, Laurent Pinchart wrote:
>> > On Thursday 19 November 2015 22:19:14 Laurent Pinchart wrote:
>> >> On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote:
>> >> > Amend the DT bindings to include the optional external clock on
>> >> > (H)SCI(F) and some SCIFA, where this pin can serve as a clock input,
>> >> > depending on board wiring.
>> >> >
>> >> > --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> >> > +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>> >> >
>> >> > @@ -43,6 +43,9 @@ Required properties:
>> >> >    - clocks: Must contain a phandle and clock-specifier pair for each
>> >> >      entry in clock-names.
>> >> >    - clock-names: Must contain "fck" for the SCIx UART functional
>> >> >    clock.
>> >> > +    On (H)SCI(F) and some SCIFA, an additional clock may be specified:
>> >>
>> >> Could you list the SCIFA variants that support external clocks ?
>> >>
>> >> > +      - "hsck" for the optional external clock input (on HSCIF),
>> >> > +      - "sck" for the optional external clock input (on other
>> >> > variants).
>> >
>> > Additionally, those clocks are used as inputs to the baud rate generator
>> > for external clocks, as the ones listed in patch 02/25 in this series.
>> > I'd merge the two patches and clarify the wording.
>>
>> "SCK" predates the BRG, it even exists on SCI in H8/300.
>>
>> That SCK is used as input to the BRG is just an artefact of how the BRG was
>> added to the SCIF. The BRG is just muxed with the existing SCK to form a
>> clock input, which is muxed with the BRR clock through the SCSCR.CKEx bits.
>> And the BRG itself can choose between SCIF_CLK and INT_CLK.
>>
>> Hence that's why I split it in two parts.
>
> It makes sense with the explanation.
>
> I think some of the patches should be clarified to mention BRG-EC (or whatever
> you want to call it) instead of just BRG, as otherwise it's very easy to
> confuse the two BRGs. The (H)SCK clock is an input to the internal BRG, while
> the SCIF_CLK and INT_CLK are inputs to the BRG-EC. Without clarification the
> DT bindings and the code can be hard to understand.

The (H)SCK clock is not an input to the internal BRG: it's used directly as the
sampling clock.

I'll add more clarification...

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input

[Geert Uytterhoeven]

On Thu, Nov 19, 2015 at 9:33 PM, Geert Uytterhoeven
<geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org> wrote:
> On Thu, Nov 19, 2015 at 9:19 PM, Laurent Pinchart
> <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org> wrote:
>> On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote:
>>> diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>>> b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index
>>> 2c9e6b8477e92792..8efc9b6f35637fbb 100644
>>> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>>> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
>>> @@ -43,6 +43,9 @@ Required properties:
>>>    - clocks: Must contain a phandle and clock-specifier pair for each entry
>>>      in clock-names.
>>>    - clock-names: Must contain "fck" for the SCIx UART functional clock.
>>> +    On (H)SCI(F) and some SCIFA, an additional clock may be specified:
>>
>> Could you list the SCIFA variants that support external clocks ?
>
> The list is in the commit description of "[PATCH 19/25] serial: sh-sci: Add
> support for optional external (H)SCK input": sh7723, sh7724, and r8a7740.
>
> Note that the list is probably incomplete, so I don't know if it's that useful
> to have it in the binding docs. Especially as I haven't verified yet that it
> actually works ;-)

For the record: on r8a7740, this feature is not available on SCIFA instances
2-7. The sole pins providing access to SCIFA_SCK[01] are muxed for Ethernet use
on r8a7740/armadillo. So it's unlikely I'll be able to support and test this.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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