From: Maxime Chevallier <maxime.chevallier@bootlin.com>
To: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Richard Cochran <richardcochran@gmail.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Biao Huang <biao.huang@mediatek.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Eric Dumazet <edumazet@kernel.org>
Cc: kernel@collabora.com, netdev@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
linux-stm32@st-md-mailman.stormreply.com
Subject: Re: [PATCH net-next v3 5/9] net: stmmac: mediatek: add RX/TX delay stage divider in platform data
Date: Fri, 16 Oct 2026 13:37:37 +0200 [thread overview]
Message-ID: <34608ab8-18f3-4680-8276-cd8611c05cb1@bootlin.com> (raw)
In-Reply-To: <20261016-dwmac-mediatek-mt8189-v3-5-25daf2bbcf35@collabora.com>
Hi Louis-Alexis,
On 10/16/26 12:31, Louis-Alexis Eyraud wrote:
> In preparation of newer SoC support, that have like MT8189 SoC
> different RX and TX internal delay stage steps than MT8188/MT8195, add
> the RX and TX delay stage divider values in the variant platform data
> and replace the hardcoded value uses in mt2712_set_delay and
> mt8195_set_delay.
>
> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
> ---
> .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 46 ++++++++++++++++++----
> 1 file changed, 38 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
> index 596411d4a5b2..cb5bda53edb9 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
> @@ -108,6 +108,10 @@ struct mediatek_dwmac_variant {
>
> u32 rx_delay_max;
> u32 tx_delay_max;
> + u16 rx_rmii_delay_stage_div;
> + u16 tx_rmii_delay_stage_div;
> + u16 rx_rgmii_delay_stage_div;
> + u16 tx_rgmii_delay_stage_div;
> u8 dma_bit_mask;
> };
>
> @@ -146,14 +150,22 @@ static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)
> u32 fine_val = 0;
>
> if (phy_interface_mode_is_rgmii(plat->phy_mode)) {
> - rx_delay_stage_div = MT2712_RGMII_DLY_RXC_STAGE_DIV;
> - tx_delay_stage_div = MT2712_RGMII_DLY_TXC_STAGE_DIV;
> + rx_delay_stage_div = plat->variant->rx_rgmii_delay_stage_div;
> + tx_delay_stage_div = plat->variant->tx_rgmii_delay_stage_div;
> } else {
> - rx_delay_stage_div = MT2712_RMII_DLY_RXC_STAGE_DIV;
> - tx_delay_stage_div = MT2712_RMII_DLY_TXC_STAGE_DIV;
> + rx_delay_stage_div = plat->variant->rx_rmii_delay_stage_div;
> + tx_delay_stage_div = plat->variant->tx_rmii_delay_stage_div;
Looking closer at this, what's RMII delay ? There's no delays in RMII, and
it's a single clock not a RX and TX clock like RGMII, there's no RMII TXC/RXC.
I think it's the same as on allwinner, the delay handling has been mixed-up between
RMII and RGMII in the glue, you should be able to simplify this even more by
ditching the RMII case.
Maxime
next prev parent reply other threads:[~2026-10-16 11:37 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-16 10:31 [PATCH net-next v3 0/9] net/stmmac: Add Mediatek MT8189 support Louis-Alexis Eyraud
2026-10-16 10:31 ` [PATCH net-next v3 1/9] dt-bindings: net: mediatek-dwmac: fix unit in rx/tx delay property description Louis-Alexis Eyraud
2026-10-16 15:33 ` Andrew Lunn
2026-10-16 10:31 ` [PATCH net-next v3 2/9] dt-bindings: net: mediatek-dwmac: add support for MT8189 SoC Louis-Alexis Eyraud
2026-10-16 15:40 ` Andrew Lunn
2026-10-16 10:31 ` [PATCH net-next v3 3/9] net: stmmac: mediatek: simplify TX/RX delay handling in mt8195_set_delay Louis-Alexis Eyraud
2026-10-16 10:31 ` [PATCH net-next v3 4/9] net: stmmac: mediatek: simplify TX/RX delay handling in mt2712_set_delay Louis-Alexis Eyraud
2026-10-16 10:31 ` [PATCH net-next v3 5/9] net: stmmac: mediatek: add RX/TX delay stage divider in platform data Louis-Alexis Eyraud
2026-10-16 11:37 ` Maxime Chevallier [this message]
2026-10-16 10:31 ` [PATCH net-next v3 6/9] net: stmmac: mediatek: add PERI_ETH_CTRLx register offset " Louis-Alexis Eyraud
2026-10-16 10:31 ` [PATCH net-next v3 7/9] net: stmmac: mediatek: use TX clock phase shift in RGMII mode with 1Gbps speed Louis-Alexis Eyraud
2026-10-16 11:41 ` Maxime Chevallier
2026-10-16 15:48 ` Andrew Lunn
2026-10-16 10:31 ` [PATCH net-next v3 8/9] net: stmmac: mediatek: add support for TX clock output enable feature Louis-Alexis Eyraud
2026-10-16 10:31 ` [PATCH net-next v3 9/9] net: stmmac: mediatek: add support for MT8189 SoC Louis-Alexis Eyraud
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