From: Heiko Stuebner <heiko@sntech.de>
To: Elaine Zhang <zhangqing@rock-chips.com>
Cc: xf@rock-chips.com, linux-clk@vger.kernel.org,
huangtao@rock-chips.com, xxx@rock-chips.com, cl@rock-chips.com,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
robh+dt@kernel.org, mark.rutland@arm.com,
mturquette@baylibre.com, sboyd@codeaurora.org,
zhengxing@rock-chips.com
Subject: Re: [PATCH v2 2/3] dt-bindings: add bindings for rk3128 clock controller
Date: Fri, 19 May 2017 12:31:18 +0200 [thread overview]
Message-ID: <3487841.3AV9ZOvb54@phil> (raw)
In-Reply-To: <1495073819-4160-3-git-send-email-zhangqing@rock-chips.com>
Hi Elaine,
Am Donnerstag, 18. Mai 2017, 10:16:58 CEST schrieb Elaine Zhang:
> Add devicetree bindings for Rockchip cru which found on
> Rockchip SoCs.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
> .../bindings/clock/rockchip,rk3128-cru.txt | 56 ++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt
> new file mode 100644
> index 000000000000..455a9a00a623
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt
> @@ -0,0 +1,56 @@
> +* Rockchip RK3128 Clock and Reset Unit
> +
> +The RK3128 clock controller generates and supplies clock to various
> +controllers within the SoC and also implements a reset controller for SoC
> +peripherals.
> +
> +Required Properties:
> +
> +- compatible: should be "rockchip,rk3128-cru"
> +- reg: physical base address of the controller and length of memory mapped
> + region.
> +- #clock-cells: should be 1.
> +- #reset-cells: should be 1.
> +
> +Optional Properties:
> +
> +- rockchip,grf: phandle to the syscon managing the "general register files"
> + If missing pll rates are not changeable, due to the missing pll lock status.
> +
> +Each clock is assigned an identifier and client nodes can use this identifier
> +to specify the clock which they consume. All available clocks are defined as
> +preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
> +used in device tree sources. Similar macros exist for the reset sources in
> +these files.
> +
> +External clocks:
> +
> +There are several clocks that are generated outside the SoC. It is expected
> +that they are defined using standard clock bindings with following
> +clock-output-names:
> + - "xin24m" - crystal input - required,
> + - "ext_i2s" - external I2S clock - optional,
> + - "gmac_clkin" - external GMAC clock - optional
missing usb480m_phy as external clock, that comes back from the usbphy block.
Otherwise looks good
Heiko
next prev parent reply other threads:[~2017-05-19 10:31 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-18 2:16 [PATCH v2 0/3] clk: rockchip: support clk controller for RK3128 SoC Elaine Zhang
2017-05-18 2:16 ` [PATCH v2 1/3] clk: rockchip: add dt-binding header for rk3128 Elaine Zhang
2017-05-18 2:16 ` [PATCH v2 2/3] dt-bindings: add bindings for rk3128 clock controller Elaine Zhang
2017-05-19 10:31 ` Heiko Stuebner [this message]
[not found] ` <1495073819-4160-3-git-send-email-zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2017-05-23 14:08 ` Rob Herring
2017-05-18 2:16 ` [PATCH v2 3/3] clk: rockchip: add clock controller for rk3128 Elaine Zhang
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