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From: Florian Eckert <fe@dev.tdt.de>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Johan Hovold" <johan+linaro@kernel.org>,
	"Sajid Dalvi" <sdalvi@google.com>,
	"Ajay Agarwal" <ajayagarwal@google.com>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Rahul Tanwar" <rtanwar@maxlinear.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, Eckert.Florian@googlemail.com,
	ms@dev.tdt.de
Subject: Re: [PATCH v2 6/7] dt-bindings: PCI: intel,lgm-pcie: Make atu resource mandatory
Date: Mon, 30 Mar 2026 12:52:16 +0200	[thread overview]
Message-ID: <34a5e88249cf895cfa1132a29343ab90@dev.tdt.de> (raw)
In-Reply-To: <b8c60db1-7b72-410e-95a1-f13052af7256@kernel.org>



On 2026-03-30 11:50, Krzysztof Kozlowski wrote:
> On 30/03/2026 11:07, Florian Eckert wrote:
>> The ATU information is already set in the dwc core if it is specified 
>> in
>> the DTS. The driver uses its own value here [1]. This information is
>> hardware specific and should therefore be maintained in the DTS rather
>> than in the source.
>> 
>> Backwards compatibility is not an issue here [5], as the driver is
>> exclusively used by Maxlinear.
> 
> What does that mean exactly? It is not used outside of Maxlinear
> company, so it is purely internal device and no one outside of 
> Maxlinear
> has it?

Background information:

The PCIe IP core is only available for Maxlinear’s URX851 and
URX850 SoCs. However, the chip was originally developed by Intel when
they acquired Lantiq’s home networking division in 2015 [1] for this
SoCs. In 2020 the home network division was sold to Maxlinear [2].

Since then, Maxlinear has been responsible for the driver. However,
their SDK is outdated and based on kernel 5.15. Other than that, not
much is happening! Even the developers listed as maintainers can no
longer be reached. When it came to the patch set, the email couldn't
be delivered  to the responsible developer
'Chuanhua Lei <lchuanhua@maxlinear.com>' either. The email bounced
back.

The company I work for is using the chip and is currently in the
process  of extracting the key components from the SDK so that the
SoC URX851/URX850 can work again with a mainline kernel again.

[1] 
https://www.intc.com/news-events/press-releases/detail/364/intel-to-acquire-lantiq-advancing-the-connected-home
[2] 
https://investors.maxlinear.com/press-releases/detail/395/maxlinear-to-acquire-intels-home-gateway-platform

> Then we can as well remove it and I don't quite get why you are working
> on this (since no one can use it outside of Maxlinear...).

Maxlinear continues to sell that SoC. They are *not' EOL.
It’s just that their Board Support Package (SDK) is no longer
up to date.

>> 
>> Old DTS entry for PCIe:
>> 
>> reg = <0xd1000000 0x1000>,
>>       <0xd3000000 0x20000>,
>>       <0xd0c41000.0x1000>;
>> reg-names = "dbi", "config", "app";
>> 
>> New DTS entry for PCIe:
>> 
>> reg = <0xd1000000 0x1000>,
>>       <0xd10c0000 0x1000>,
>>       <0xd3000000 0x20000>,
>>      <0xd0c41000.0x1000>;
>> reg-names = "dbi", "atu", "config", "app";
> 
> Drop, irrelevant. You still break all users of this binding.

As noted in link [3], a Maxlinear developer has stated that
backwards compatibility is not necessary here, as the IP core
is used exclusively by Maxlinear`s URX851 and URX850 SoC`s.

We use these SoCs in our Produkt for internet home gateway
routers.

[3] 
https://lore.kernel.org/all/BY3PR19MB507667CE7531D863E1E5F8AEBDD82@BY3PR19MB5076.namprd19.prod.outlook.com/

> Best regards,
> Krzysztof

  reply	other threads:[~2026-03-30 10:52 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-30  9:07 [PATCH v2 0/7] PCI: intel-gw: Fixes to make the driver working again Florian Eckert
2026-03-30  9:07 ` [PATCH v2 1/7] PCI: intel-gw: Remove unused define Florian Eckert
2026-03-30  9:07 ` [PATCH v2 2/7] PCI: intel-gw: Move interrupt enable to own function Florian Eckert
2026-03-30  9:07 ` [PATCH v2 3/7] PCI: intel-gw: Enable clock before phy init Florian Eckert
2026-03-30  9:07 ` [PATCH v2 4/7] PCI: intel-gw: Add start_link callback function Florian Eckert
2026-03-30  9:07 ` [PATCH v2 5/7] PCI: intel-gw: Remove atu base assignment Florian Eckert
2026-03-30  9:07 ` [PATCH v2 6/7] dt-bindings: PCI: intel,lgm-pcie: Make atu resource mandatory Florian Eckert
2026-03-30  9:50   ` Krzysztof Kozlowski
2026-03-30 10:52     ` Florian Eckert [this message]
2026-03-30 10:35   ` Rob Herring (Arm)
2026-03-30  9:07 ` [PATCH v2 7/7] MAINTAINERS: Remove bouncing intel-gw maintainer Florian Eckert

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