[PATCH 0/3] dt-bindings: clock: xilinx: Update VCU bindings

[PATCH 0/3] dt-bindings: clock: xilinx: Update VCU bindings

[Rohit Visavalia]

This patch series converts dt-binding to dtschema and adds reset GPIO
as optional property. 

Rohit Visavalia (3):
  dt-bindings: clock: xilinx: move xlnx_vcu dt-binding to clock from soc
  dt-bindings: clock: xilinx: Convert VCU bindings to dtschema
  dt-bindings: clock: xilinx: Update VCU bindings for reset GPIO

 .../devicetree/bindings/clock/xlnx,vcu.yaml   | 64 +++++++++++++++++++
 .../bindings/soc/xilinx/xlnx,vcu.txt          | 26 --------
 2 files changed, 64 insertions(+), 26 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
 delete mode 100644 Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt

-- 
2.25.1

[PATCH 1/3] dt-bindings: clock: xilinx: move xlnx_vcu dt-binding to clock from soc

[Rohit Visavalia]

From: Rohit Visavalia <rohit.visavalia@xilinx.com>

As per commit a2fe7baa27a4 ("clk: xilinx: move xlnx_vcu clock
driver from soc"), xlnx_vcu driver code is moved to clock from soc,
so moving the dt-binding.

Signed-off-by: Rohit Visavalia <rohit.visavalia@xilinx.com>
---
 .../devicetree/bindings/{soc/xilinx => clock}/xlnx,vcu.txt        | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename Documentation/devicetree/bindings/{soc/xilinx => clock}/xlnx,vcu.txt (100%)

diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt b/Documentation/devicetree/bindings/clock/xlnx,vcu.txt
similarity index 100%
rename from Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt
rename to Documentation/devicetree/bindings/clock/xlnx,vcu.txt
-- 
2.25.1

[PATCH 2/3] dt-bindings: clock: xilinx: Convert VCU bindings to dtschema

[Rohit Visavalia]

Convert AMD (Xilinx) VCU bindings to yaml format.

Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com>
---
 .../devicetree/bindings/clock/xlnx,vcu.txt    | 26 ---------
 .../devicetree/bindings/clock/xlnx,vcu.yaml   | 58 +++++++++++++++++++
 2 files changed, 58 insertions(+), 26 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/xlnx,vcu.txt
 create mode 100644 Documentation/devicetree/bindings/clock/xlnx,vcu.yaml

diff --git a/Documentation/devicetree/bindings/clock/xlnx,vcu.txt b/Documentation/devicetree/bindings/clock/xlnx,vcu.txt
deleted file mode 100644
index 2417b13ba468..000000000000
--- a/Documentation/devicetree/bindings/clock/xlnx,vcu.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-LogicoreIP designed compatible with Xilinx ZYNQ family.
--------------------------------------------------------
-
-General concept
----------------
-
-LogicoreIP design to provide the isolation between processing system
-and programmable logic. Also provides the list of register set to configure
-the frequency.
-
-Required properties:
-- compatible: shall be one of:
-	"xlnx,vcu"
-	"xlnx,vcu-logicoreip-1.0"
-- reg : The base offset and size of the VCU_PL_SLCR register space.
-- clocks: phandle for aclk and pll_ref clocksource
-- clock-names: The identification string, "aclk", is always required for
-   the axi clock. "pll_ref" is required for pll.
-Example:
-
-	xlnx_vcu: vcu@a0040000 {
-		compatible = "xlnx,vcu-logicoreip-1.0";
-		reg = <0x0 0xa0040000 0x0 0x1000>;
-		clocks = <&si570_1>, <&clkc 71>;
-		clock-names = "pll_ref", "aclk";
-	};
diff --git a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
new file mode 100644
index 000000000000..bdb14594c40b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/xlnx,vcu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: LogicoreIP designed compatible with Xilinx ZYNQ family.
+
+maintainers:
+  - Rohit Visavalia <rohit.visavalia@amd.com>
+
+description:
+  LogicoreIP design to provide the isolation between processing system
+  and programmable logic. Also provides the list of register set to configure
+  the frequency.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - xlnx,vcu
+          - xlnx,vcu-logicoreip-1.0
+
+  reg:
+    description:
+      The base offset and size of the VCU_PL_SLCR register space.
+    minItems: 1
+
+  clocks:
+    description: List of clock specifiers
+    items:
+      - description: pll ref clocksource
+      - description: aclk
+
+  clock-names:
+    items:
+      - const: pll_ref
+      - const: aclk
+
+required:
+  - reg
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    fpga {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        xlnx_vcu: vcu@a0040000 {
+            compatible = "xlnx,vcu-logicoreip-1.0";
+            reg = <0x0 0xa0040000 0x0 0x1000>;
+            clocks = <&si570_1>, <&clkc 71>;
+            clock-names = "pll_ref", "aclk";
+        };
+    };
-- 
2.25.1

[PATCH 3/3] dt-bindings: clock: xilinx: Update VCU bindings for reset GPIO

[Rohit Visavalia]

Updated VCU binding for reset GPIO pin as optional property.
It is marked as optional as some of the ZynqMP designs are having vcu_reset
(reset pin of VCU IP) is driven by proc_sys_reset, proc_sys_reset is another
PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by
axi_gpio or PS GPIO so there will be no GPIO entry.

Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com>
---
 Documentation/devicetree/bindings/clock/xlnx,vcu.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
index bdb14594c40b..b3061309f8dd 100644
--- a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
+++ b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
@@ -36,6 +36,11 @@ properties:
       - const: pll_ref
       - const: aclk
 
+  reset-gpios:
+    description: Optional GPIO used to reset the VCU, if available. Need use this
+      reset gpio when in design 'vcu_resetn' is driven by gpio.
+    maxItems: 1
+
 required:
   - reg
   - clocks
@@ -52,6 +57,7 @@ examples:
         xlnx_vcu: vcu@a0040000 {
             compatible = "xlnx,vcu-logicoreip-1.0";
             reg = <0x0 0xa0040000 0x0 0x1000>;
+            reset-gpios = <&gpio 0x4e GPIO_ACTIVE_HIGH>;
             clocks = <&si570_1>, <&clkc 71>;
             clock-names = "pll_ref", "aclk";
         };
-- 
2.25.1

Re: [PATCH 2/3] dt-bindings: clock: xilinx: Convert VCU bindings to dtschema

[Krzysztof Kozlowski]

On 02/01/2025 17:36, Rohit Visavalia wrote:
> Convert AMD (Xilinx) VCU bindings to yaml format.
> 


...

> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - xlnx,vcu
> +          - xlnx,vcu-logicoreip-1.0
> +
> +  reg:
> +    description:
> +      The base offset and size of the VCU_PL_SLCR register space.

Drop description, redundant.

> +    minItems: 1

There is no code like this. maxItems instead. Please use example-schema
or other recently reviewed bindings as starting point.

> +
> +  clocks:
> +    description: List of clock specifiers

Drop description.

> +    items:
> +      - description: pll ref clocksource
> +      - description: aclk

Original binding said different order. Mention change in commit msg with
explanation why.

Best regards,
Krzysztof

Re: [PATCH 3/3] dt-bindings: clock: xilinx: Update VCU bindings for reset GPIO

[Krzysztof Kozlowski]

On 02/01/2025 17:37, Rohit Visavalia wrote:
> Updated VCU binding for reset GPIO pin as optional property.

Subject and here: everything is an update. Be specific and drop all
redundant things making this unnecessary long: add reset GPIO

> It is marked as optional as some of the ZynqMP designs are having vcu_reset
> (reset pin of VCU IP) is driven by proc_sys_reset, proc_sys_reset is another

"are having is" looks like two verbs.

I don't get here mainly why SoC has something driven by its own GPIO.
That's unusual pattern.


> PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by
> axi_gpio or PS GPIO so there will be no GPIO entry.

Anyway, this has to be constrained per SoC.

> 
> Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com>
> ---
>  Documentation/devicetree/bindings/clock/xlnx,vcu.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
> index bdb14594c40b..b3061309f8dd 100644
> --- a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
> +++ b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
> @@ -36,6 +36,11 @@ properties:
>        - const: pll_ref
>        - const: aclk
>  
> +  reset-gpios:
> +    description: Optional GPIO used to reset the VCU, if available. Need use this

Drop redundant parts. Not being part of required defines "optional"
already. Don't repeat the schema but say something which we cannot
deduce from this.

> +      reset gpio when in design 'vcu_resetn' is driven by gpio.
> +    maxItems: 1
> +
>  required:
>    - reg
>    - clocks
> @@ -52,6 +57,7 @@ examples:
>          xlnx_vcu: vcu@a0040000 {
>              compatible = "xlnx,vcu-logicoreip-1.0";
>              reg = <0x0 0xa0040000 0x0 0x1000>;
> +            reset-gpios = <&gpio 0x4e GPIO_ACTIVE_HIGH>;

GPIO numbers are not hex... unless this is not GPIO :/

>              clocks = <&si570_1>, <&clkc 71>;
>              clock-names = "pll_ref", "aclk";
>          };


Best regards,
Krzysztof

Re: [PATCH 1/3] dt-bindings: clock: xilinx: move xlnx_vcu dt-binding to clock from soc

[Krzysztof Kozlowski]

On 02/01/2025 17:36, Rohit Visavalia wrote:
> From: Rohit Visavalia <rohit.visavalia@xilinx.com>
> 
> As per commit a2fe7baa27a4 ("clk: xilinx: move xlnx_vcu clock
> driver from soc"), xlnx_vcu driver code is moved to clock from soc,
> so moving the dt-binding.
> 
Drop commit, does not make sense. Just move the file during conversion.

Best regards,
Krzysztof

RE: [PATCH 1/3] dt-bindings: clock: xilinx: move xlnx_vcu dt-binding to clock from soc

[Visavalia, Rohit]

Hi Krzysztof,

Thanks for the review.

>-----Original Message-----
>From: Krzysztof Kozlowski <krzk@kernel.org>
>Sent: Friday, January 3, 2025 12:01 AM
>To: Visavalia, Rohit <rohit.visavalia@amd.com>; mturquette@baylibre.com;
>sboyd@kernel.org; robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org
>Cc: linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
>kernel@vger.kernel.org; Rohit Visavalia <rohit.visavalia@xilinx.com>
>Subject: Re: [PATCH 1/3] dt-bindings: clock: xilinx: move xlnx_vcu dt-binding to
>clock from soc
>
>On 02/01/2025 17:36, Rohit Visavalia wrote:
>> From: Rohit Visavalia <rohit.visavalia@xilinx.com>
>>
>> As per commit a2fe7baa27a4 ("clk: xilinx: move xlnx_vcu clock driver
>> from soc"), xlnx_vcu driver code is moved to clock from soc, so moving
>> the dt-binding.
>>
>Drop commit, does not make sense. Just move the file during conversion.
Sure, I will do in v2 patch series.

>
>Best regards,
>Krzysztof

Thanks
Rohit

RE: [PATCH 2/3] dt-bindings: clock: xilinx: Convert VCU bindings to dtschema

[Visavalia, Rohit]

Hi Krzysztof,

Thanks for the review.

>-----Original Message-----
>From: Krzysztof Kozlowski <krzk@kernel.org>
>Sent: Thursday, January 2, 2025 11:56 PM
>To: Visavalia, Rohit <rohit.visavalia@amd.com>; mturquette@baylibre.com;
>sboyd@kernel.org; robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org
>Cc: linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
>kernel@vger.kernel.org
>Subject: Re: [PATCH 2/3] dt-bindings: clock: xilinx: Convert VCU bindings to
>dtschema
>
>On 02/01/2025 17:36, Rohit Visavalia wrote:
>> Convert AMD (Xilinx) VCU bindings to yaml format.
>>
>
>
>...
>
>> +
>> +properties:
>> +  compatible:
>> +    items:
>> +      - enum:
>> +          - xlnx,vcu
>> +          - xlnx,vcu-logicoreip-1.0
>> +
>> +  reg:
>> +    description:
>> +      The base offset and size of the VCU_PL_SLCR register space.
>
>Drop description, redundant.
I will take care in v2 patch series.
>
>> +    minItems: 1
>
>There is no code like this. maxItems instead. Please use example-schema or other
>recently reviewed bindings as starting point.
I will update in v2 patch.

>> +
>> +  clocks:
>> +    description: List of clock specifiers
>
>Drop description.
I will remove in v2 patch series.
>
>> +    items:
>> +      - description: pll ref clocksource
>> +      - description: aclk
>
>Original binding said different order. Mention change in commit msg with
>explanation why.
I will update commit msg in v2 patch.
>
>Best regards,
>Krzysztof

Thanks
Rohit

RE: [PATCH 3/3] dt-bindings: clock: xilinx: Update VCU bindings for reset GPIO

[Visavalia, Rohit]

Hi Krzysztof,

Thanks for the review.

>-----Original Message-----
>From: Krzysztof Kozlowski <krzk@kernel.org>
>Sent: Friday, January 3, 2025 12:00 AM
>To: Visavalia, Rohit <rohit.visavalia@amd.com>; mturquette@baylibre.com;
>sboyd@kernel.org; robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org
>Cc: linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
>kernel@vger.kernel.org
>Subject: Re: [PATCH 3/3] dt-bindings: clock: xilinx: Update VCU bindings for reset
>GPIO
>
>On 02/01/2025 17:37, Rohit Visavalia wrote:
>> Updated VCU binding for reset GPIO pin as optional property.
>
>Subject and here: everything is an update. Be specific and drop all redundant
>things making this unnecessary long: add reset GPIO
Sure. I will take care in v2.

>
>> It is marked as optional as some of the ZynqMP designs are having
>> vcu_reset (reset pin of VCU IP) is driven by proc_sys_reset,
>> proc_sys_reset is another
>
>"are having is" looks like two verbs.
I will correct in v2 patch.

>
>I don't get here mainly why SoC has something driven by its own GPIO.
>That's unusual pattern.

VCU IP is in PL not part of PS.
>
>
>> PL IP driven by the PS pl_reset. So, here the VCU reset is not driven
>> by axi_gpio or PS GPIO so there will be no GPIO entry.
>
>Anyway, this has to be constrained per SoC.
As VCU IP is in PL, it depends on PL design creator how connection of VCU reset pin is done.

>
>>
>> Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com>
>> ---
>>  Documentation/devicetree/bindings/clock/xlnx,vcu.yaml | 6 ++++++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
>> b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
>> index bdb14594c40b..b3061309f8dd 100644
>> --- a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
>> +++ b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
>> @@ -36,6 +36,11 @@ properties:
>>        - const: pll_ref
>>        - const: aclk
>>
>> +  reset-gpios:
>> +    description: Optional GPIO used to reset the VCU, if available.
>> + Need use this
>
>Drop redundant parts. Not being part of required defines "optional"
>already. Don't repeat the schema but say something which we cannot deduce from
>this.
Got it.

>
>> +      reset gpio when in design 'vcu_resetn' is driven by gpio.
>> +    maxItems: 1
>> +
>>  required:
>>    - reg
>>    - clocks
>> @@ -52,6 +57,7 @@ examples:
>>          xlnx_vcu: vcu@a0040000 {
>>              compatible = "xlnx,vcu-logicoreip-1.0";
>>              reg = <0x0 0xa0040000 0x0 0x1000>;
>> +            reset-gpios = <&gpio 0x4e GPIO_ACTIVE_HIGH>;
>
>GPIO numbers are not hex... unless this is not GPIO :/
Sure, I will update in v2 patch series.

>
>>              clocks = <&si570_1>, <&clkc 71>;
>>              clock-names = "pll_ref", "aclk";
>>          };
>
>
>Best regards,
>Krzysztof

Thanks
Rohit